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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id k24sm4301988wmj.19.2020.09.03.06.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 06:32:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZSYYIuhZbs62/xiGmWlQgE9F1UvNn4/kf3VtqXYNpHc=; b=UqBVKU3QuGzw82p38DBkf96SOkOr7tAHsCrbHXlhxw0W8awZc4egS2jlm15/4bC65/ RBQtXRsqafTdc7kkF6U/NeWy0/3XIwYEHcGn2UEhSxg3s2YIxNx67VSP7rFqF3SWsWFJ NA+atITgFxqEnDExUHFb/Loxgn36txZWEBKgZoYwjdURXouF8QrOGlY6Rh4X9QKvEh2j U/KzEts/FRe9sKBUgfpCWaPN6uGF6YaAER0wDvwvraxeGS1SOru9yVP31B3lRU6fe0u6 Li6VBLIG3H7Q7aGJWqKm0Jt/jj1ZP4daktsMTQIcUMDlKdVH5CNY/81ecg/ghJCzTjWb TUlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZSYYIuhZbs62/xiGmWlQgE9F1UvNn4/kf3VtqXYNpHc=; b=K/o3kmx433oRWZzKvC0WeJVY3arIn+i7UqBGYfUpU/rIGhebVoQhBTB89Hf4SwtxPT PhOOYlZjRau6jYdDnByQn7FD1UxnuMspFsWUwn95yFhAEQmoG84g4T28Nz3BN5EfaIuR BkjNYoxEl0P/O+TlUxEMtNz5cJ2Q+kcuF4rd1hkhDeme54xQkuGHmfrguemyTsIH9pjL DggIAjyOg+qDPMcOUq4l0bNtZoRvluE4Ep7c6yxevdE87N+C25+z7yJMj8i+alSOlFRD hkUWStAI82VVAn5WuzijYzgebue2DEpT+p8VlIqEMQJ/WL4/mMPRdRfTNeHNcDBaRTKu MQHA== X-Gm-Message-State: AOAM530FY+AfS2Lx338qUPjTeywYRPsJILg56ilYQmSa6o1j6B3JVR7j f4EJcurStk1hVrf9vOO4nVE4cg== X-Google-Smtp-Source: ABdhPJx8yckDexcediHvV5DSFCoGgkujjaYCoJDpFjooaeapIOVAsHHviza72mq1eNJvCmw+4jH0QA== X-Received: by 2002:a7b:c3da:: with SMTP id t26mr2435537wmj.23.1599139933162; Thu, 03 Sep 2020 06:32:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Convert Neon 3-same-fp size field to MO_* in decode Date: Thu, 3 Sep 2020 14:32:07 +0100 Message-Id: <20200903133209.5141-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200903133209.5141-1-peter.maydell@linaro.org> References: <20200903133209.5141-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In the Neon instructions, some instruction formats have a 2-bit size field which corresponds exactly to QEMU's MO_8/16/32/64. However the floating-point insns in the 3-same group have a 1-bit size field which is "0 for 32-bit float and 1 for 16-bit float". Currently we pass these values directly through to trans_ functions, which means that when reading a particular trans_ function you need to know if that insn uses a 2-bit size or a 1-bit size. Move the handling of the 1-bit size to the decodetree file, so that all these insns consistently pass a size to the trans_ function which is an MO_8/16/32/64 value. In this commit we switch over the insns using the 3same_fp and 3same_fp_q0 formats. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I wanted to call the field %3same_fp_size, but decodetree doesn't seem to allow a field starting with a digit, even though it does allow a format that starts with a digit. So it's %fp_3same_size... --- target/arm/neon-dp.decode | 15 ++++++++++----- target/arm/translate-neon.c.inc | 16 +++++++++++----- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 1e9e8592917..f453833396f 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -45,11 +45,16 @@ @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \ &3same vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp q=3D0 =20 -# For FP insns the high bit of 'size' is used as part of opcode decode -@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \ - &3same vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp -@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \ - &3same vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp q=3D0 +# For FP insns the high bit of 'size' is used as part of opcode decode, +# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float. +# This converts this encoding to the same MO_8/16/32/64 values that the +# integer neon insns use. +%fp_3same_size 20:1 !function=3Dneon_3same_fp_size + +@3same_fp .... ... . . . . . .... .... .... . q:1 . . .... \ + &3same vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp size=3D%fp_3sa= me_size +@3same_fp_q0 .... ... . . . . . .... .... .... . 0 . . .... \ + &3same vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp q=3D0 size=3D%= fp_3same_size =20 VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 2d4926316a4..255c1cf8a2a 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -49,6 +49,12 @@ static inline int rsub_8(DisasContext *s, int x) return 8 - x; } =20 +static inline int neon_3same_fp_size(DisasContext *s, int x) +{ + /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ + return MO_32 - x; +} + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" @@ -1049,7 +1055,7 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC) \ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ { \ - if (a->size !=3D 0) { \ + if (a->size =3D=3D MO_16) { = \ if (!dc_isar_feature(aa32_fp16_arith, s)) { \ return false; \ } \ @@ -1088,7 +1094,7 @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3= same *a) return false; } =20 - if (a->size !=3D 0) { + if (a->size =3D=3D MO_16) { if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -1103,7 +1109,7 @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3= same *a) return false; } =20 - if (a->size !=3D 0) { + if (a->size =3D=3D MO_16) { if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -1135,7 +1141,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3sa= me *a, assert(a->q =3D=3D 0); /* enforced by decode patterns */ =20 =20 - fpstatus =3D fpstatus_ptr(a->size !=3D 0 ? FPST_STD_F16 : FPST_STD); + fpstatus =3D fpstatus_ptr(a->size =3D=3D MO_16 ? FPST_STD_F16 : FPST_S= TD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -1152,7 +1158,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3sa= me *a, #define DO_3S_FP_PAIR(INSN,FUNC) \ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ { \ - if (a->size !=3D 0) { \ + if (a->size =3D=3D MO_16) { \ if (!dc_isar_feature(aa32_fp16_arith, s)) { \ return false; \ } \ --=20 2.20.1