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[83.52.54.50]) by smtp.gmail.com with ESMTPSA id s124sm4227408wme.29.2020.09.03.05.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 05:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1599136107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EBREVqe86w/qV8xj/jHdOJ+D9gTNwJHNOwqeZKQd6RY=; b=GXyRWn+IFC5SWCcgC3FjtbSsT+ZALiCJLE0g9fFz3/hP81iIDdA/nHxGrJc8Ty+JfRnMKg 7FPYApK5vlUvx8i+eK+tEflteSi1KYxBF9dQgixC8E/05IEd4OJ0x+5+Spng6q8WB3Ai6C ggqMKZ9bxqb+Xa29Cj4mJzeJOmFvjGA= X-MC-Unique: 3rW6a5-mMdqW24qVkIwVeQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EBREVqe86w/qV8xj/jHdOJ+D9gTNwJHNOwqeZKQd6RY=; b=Tb9S0y75WsxNsX4e1AFzQYIQ0nihozW9tj1QfVhWM3styVf+fedBdi/jcAWZa2dqUq mfV1Js2Ob0ox4cj0sb7GmSL/FtOGSez72z6zuvMJnBVLDbVREMc4ZLAWTfER8eo3s0Qi nYoznDRV/tHCFIfeDtUfy+ef/VBBFsZYQ0th6JQq5n59+3QOlTVQOU3yplYUIoYlGCrp DL5YsHzpgf7y9I55+dn2DL7ymJyZ6ZrvNGtCv0Qaob2PGT5aXOmHAqMichv3yEVu3PzY EBunfPbIUL4axgxOFf2JORMrAF3Zx8R7S46T/VPq97g1Yi/u21o9B461ObJXLHIA5Ust mLBA== X-Gm-Message-State: AOAM533faoe614ovEcZHJL8v7oEbzJc8zfJJJMHg7f+OvMBybMli/3x8 yOr9EvOiNvQ0MBb7NuoNjjfGYO+PBijJZRnXrKe4zpsIRF5t0cYaABlEWAjKgqwYq2b2K6Dx/rQ EQsWjyAUDQLM0Yg== X-Received: by 2002:adf:f149:: with SMTP id y9mr2152341wro.93.1599136105025; Thu, 03 Sep 2020 05:28:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJym8SdPMuTrQF/qKRC4BamPWHAPQNevAOuB6lz85pdqrdqAmnSUHoQARZi2v12uTEjpcCjfkQ== X-Received: by 2002:adf:f149:: with SMTP id y9mr2152315wro.93.1599136104771; Thu, 03 Sep 2020 05:28:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Klaus Jensen , Fam Zheng , Max Reitz , Keith Busch , Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Stefan Hajnoczi , Stefano Garzarella Subject: [PATCH v7 04/15] block/nvme: Define INDEX macros to ease code review Date: Thu, 3 Sep 2020 14:27:52 +0200 Message-Id: <20200903122803.405265-5-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200903122803.405265-1-philmd@redhat.com> References: <20200903122803.405265-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Use definitions instead of '0' or '1' indexes. Also this will be useful when using multi-queues later. Reviewed-by: Stefan Hajnoczi Reviewed-by: Stefano Garzarella Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index ca8b039f4f0..488d4ddb3b8 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -103,6 +103,9 @@ typedef volatile struct { =20 QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells) !=3D 0x1000); =20 +#define INDEX_ADMIN 0 +#define INDEX_IO(n) (1 + n) + struct BDRVNVMeState { AioContext *aio_context; QEMUVFIOState *vfio; @@ -531,7 +534,7 @@ static void nvme_identify(BlockDriverState *bs, int nam= espace, Error **errp) } cmd.dptr.prp1 =3D cpu_to_le64(iova); =20 - if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { + if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { error_setg(errp, "Failed to identify controller"); goto out; } @@ -555,7 +558,7 @@ static void nvme_identify(BlockDriverState *bs, int nam= espace, Error **errp) =20 cmd.cdw10 =3D 0; cmd.nsid =3D cpu_to_le32(namespace); - if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { + if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { error_setg(errp, "Failed to identify namespace"); goto out; } @@ -644,7 +647,7 @@ static bool nvme_add_io_queue(BlockDriverState *bs, Err= or **errp) .cdw10 =3D cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), .cdw11 =3D cpu_to_le32(0x3), }; - if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { + if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { error_setg(errp, "Failed to create io queue [%d]", n); nvme_free_queue_pair(q); return false; @@ -655,7 +658,7 @@ static bool nvme_add_io_queue(BlockDriverState *bs, Err= or **errp) .cdw10 =3D cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), .cdw11 =3D cpu_to_le32(0x1 | (n << 16)), }; - if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { + if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { error_setg(errp, "Failed to create io queue [%d]", n); nvme_free_queue_pair(q); return false; @@ -739,16 +742,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, =20 /* Set up admin queue. */ s->queues =3D g_new(NVMeQueuePair *, 1); - s->queues[0] =3D nvme_create_queue_pair(bs, 0, NVME_QUEUE_SIZE, errp); - if (!s->queues[0]) { + s->queues[INDEX_ADMIN] =3D nvme_create_queue_pair(bs, 0, + NVME_QUEUE_SIZE, + errp); + if (!s->queues[INDEX_ADMIN]) { ret =3D -EINVAL; goto out; } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); s->regs->aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE= ); - s->regs->asq =3D cpu_to_le64(s->queues[0]->sq.iova); - s->regs->acq =3D cpu_to_le64(s->queues[0]->cq.iova); + s->regs->asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); + s->regs->acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ s->regs->cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | @@ -839,7 +844,7 @@ static int nvme_enable_disable_write_cache(BlockDriverS= tate *bs, bool enable, .cdw11 =3D cpu_to_le32(enable ? 0x01 : 0x00), }; =20 - ret =3D nvme_cmd_sync(bs, s->queues[0], &cmd); + ret =3D nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd); if (ret) { error_setg(errp, "Failed to configure NVMe write cache"); } @@ -1056,7 +1061,7 @@ static coroutine_fn int nvme_co_prw_aligned(BlockDriv= erState *bs, { int r; BDRVNVMeState *s =3D bs->opaque; - NVMeQueuePair *ioq =3D s->queues[1]; + NVMeQueuePair *ioq =3D s->queues[INDEX_IO(0)]; NVMeRequest *req; =20 uint32_t cdw12 =3D (((bytes >> s->blkshift) - 1) & 0xFFFF) | @@ -1171,7 +1176,7 @@ static coroutine_fn int nvme_co_pwritev(BlockDriverSt= ate *bs, static coroutine_fn int nvme_co_flush(BlockDriverState *bs) { BDRVNVMeState *s =3D bs->opaque; - NVMeQueuePair *ioq =3D s->queues[1]; + NVMeQueuePair *ioq =3D s->queues[INDEX_IO(0)]; NVMeRequest *req; NvmeCmd cmd =3D { .opcode =3D NVME_CMD_FLUSH, @@ -1202,7 +1207,7 @@ static coroutine_fn int nvme_co_pwrite_zeroes(BlockDr= iverState *bs, BdrvRequestFlags flags) { BDRVNVMeState *s =3D bs->opaque; - NVMeQueuePair *ioq =3D s->queues[1]; + NVMeQueuePair *ioq =3D s->queues[INDEX_IO(0)]; NVMeRequest *req; =20 uint32_t cdw12 =3D ((bytes >> s->blkshift) - 1) & 0xFFFF; @@ -1255,7 +1260,7 @@ static int coroutine_fn nvme_co_pdiscard(BlockDriverS= tate *bs, int bytes) { BDRVNVMeState *s =3D bs->opaque; - NVMeQueuePair *ioq =3D s->queues[1]; + NVMeQueuePair *ioq =3D s->queues[INDEX_IO(0)]; NVMeRequest *req; NvmeDsmRange *buf; QEMUIOVector local_qiov; @@ -1398,7 +1403,7 @@ static void nvme_aio_unplug(BlockDriverState *bs) BDRVNVMeState *s =3D bs->opaque; assert(s->plugged); s->plugged =3D false; - for (i =3D 1; i < s->nr_queues; i++) { + for (i =3D INDEX_IO(0); i < s->nr_queues; i++) { NVMeQueuePair *q =3D s->queues[i]; qemu_mutex_lock(&q->lock); nvme_kick(q); --=20 2.26.2