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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reindent; remove dead/commented code. Use D_FLAG to set ESS[DS]. Sink MSR adjustment for kernel entry, iflags and res_addr clear. Improve CPU_LOG_INT formatting; report pc and msr before and after. Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 209 ++++++++++++++++--------------------- 1 file changed, 91 insertions(+), 118 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 00090526da..27a24bb99a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -111,6 +111,7 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; uint32_t t, msr =3D mb_cpu_read_msr(env); + bool set_esr; =20 /* IMM flag cannot propagate across a branch and into the dslot. */ assert((env->iflags & (D_FLAG | IMM_FLAG)) !=3D (D_FLAG | IMM_FLAG)); @@ -118,142 +119,114 @@ void mb_cpu_do_interrupt(CPUState *cs) assert((env->iflags & (D_FLAG | BIMM_FLAG)) !=3D BIMM_FLAG); /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); - env->res_addr =3D RES_ADDR_NONE; + switch (cs->exception_index) { - case EXCP_HW_EXCP: - if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { - qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system= without exceptions!\n"); - return; - } + case EXCP_HW_EXCP: + if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Exception raised on system without exceptions!\= n"); + return; + } =20 - env->regs[17] =3D env->pc + 4; - env->esr &=3D ~(1 << 12); + qemu_log_mask(CPU_LOG_INT, + "INT: HWE at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); =20 - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |=3D 1 << 12 ; - env->btr =3D env->btarget; - } + /* Exception breaks branch + dslot sequence? */ + set_esr =3D true; + env->esr &=3D ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |=3D D_FLAG; + env->btr =3D env->btarget; + } =20 - /* Disable the MMU. */ - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - /* Exception in progress. */ - msr |=3D MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Exception in progress. */ + msr |=3D MSR_EIP; + env->regs[17] =3D env->pc + 4; + env->pc =3D cpu->cfg.base_vectors + 0x20; + break; =20 - qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=3D%x ear=3D%" PRIx64 " " - "esr=3D%x iflags=3D%x\n", - env->pc, env->ear, - env->esr, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x20; - break; + case EXCP_MMU: + qemu_log_mask(CPU_LOG_INT, + "INT: MMU at pc=3D%08x msr=3D%08x " + "ear=3D%" PRIx64 " iflags=3D%x\n", + env->pc, msr, env->ear, env->iflags); =20 - case EXCP_MMU: + /* Exception breaks branch + dslot sequence? */ + set_esr =3D true; + env->esr &=3D ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |=3D D_FLAG; + env->btr =3D env->btarget; + /* Reexecute the branch. */ + env->regs[17] =3D env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); + } else if (env->iflags & IMM_FLAG) { + /* Reexecute the imm. */ + env->regs[17] =3D env->pc - 4; + } else { env->regs[17] =3D env->pc; + } =20 - qemu_log_mask(CPU_LOG_INT, - "MMU exception at pc=3D%x iflags=3D%x ear=3D%" P= RIx64 "\n", - env->pc, env->iflags, env->ear); + /* Exception in progress. */ + msr |=3D MSR_EIP; + env->pc =3D cpu->cfg.base_vectors + 0x20; + break; =20 - env->esr &=3D ~(1 << 12); - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |=3D 1 << 12 ; - env->btr =3D env->btarget; + case EXCP_IRQ: + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 - /* Reexecute the branch. */ - env->regs[17] -=3D 4; - /* was the branch immprefixed?. */ - if (env->iflags & BIMM_FLAG) { - env->regs[17] -=3D 4; - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - } - } else if (env->iflags & IMM_FLAG) { - env->regs[17] -=3D 4; - } + qemu_log_mask(CPU_LOG_INT, + "INT: DEV at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); + set_esr =3D false; =20 - /* Disable the MMU. */ - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - /* Exception in progress. */ - msr |=3D MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Disable interrupts. */ + msr &=3D ~MSR_IE; + env->regs[14] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x10; + break; =20 - qemu_log_mask(CPU_LOG_INT, - "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", - env->pc, env->ear, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x20; - break; + case EXCP_HW_BREAK: + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 - case EXCP_IRQ: - assert(!(msr & (MSR_EIP | MSR_BIP))); - assert(msr & MSR_IE); - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + qemu_log_mask(CPU_LOG_INT, + "INT: BRK at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); + set_esr =3D false; =20 - t =3D (msr & (MSR_VM | MSR_UM)) << 1; + /* Break in progress. */ + msr |=3D MSR_BIP; + env->regs[16] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x18; + break; =20 -#if 0 -#include "disas/disas.h" + default: + cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_ind= ex); + /* not reached */ + } =20 -/* Useful instrumentation when debugging interrupt issues in either - the models or in sw. */ - { - const char *sym; + /* Save previous mode, disable mmu, disable user-mode. */ + t =3D (msr & (MSR_VM | MSR_UM)) << 1; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |=3D t; + mb_cpu_write_msr(env, msr); =20 - sym =3D lookup_symbol(env->pc); - if (sym - && (!strcmp("netif_rx", sym) - || !strcmp("process_backlog", sym))) { + env->res_addr =3D RES_ADDR_NONE; + env->iflags =3D 0; =20 - qemu_log("interrupt at pc=3D%x msr=3D%x %x iflags=3D%x= sym=3D%s\n", - env->pc, msr, t, env->iflags, sym); - - log_cpu_state(cs, 0); - } - } -#endif - qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, msr, t, env->iflags); - - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - msr |=3D t; - mb_cpu_write_msr(env, msr); - - env->regs[14] =3D env->pc; - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, cs, 0); - break; - - case EXCP_HW_BREAK: - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); - - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - qemu_log_mask(CPU_LOG_INT, - "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, msr, t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - msr |=3D MSR_BIP; - env->regs[16] =3D env->pc; - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x18; - mb_cpu_write_msr(env, msr); - break; - default: - cpu_abort(cs, "unhandled exception type=3D%d\n", - cs->exception_index); - break; + if (!set_esr) { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x\n", env->pc, msr); + } else if (env->esr & D_FLAG) { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x esr=3D%04x btr=3D%= 08x\n", + env->pc, msr, env->esr, env->btr); + } else { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x esr=3D%04x\n", + env->pc, msr, env->esr); } } =20 --=20 2.25.1