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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" There are several problems here that can result in soft lockup, depending on exactly where an interrupt or exception is delivered: Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG. Ensure that iflags is 0 when entering an interrupt/exception handler. Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags. The change to t_sync_flags is cosmetic, but makes the code clearer. This fixes the reported regression in acceptance/replay_kernel.py. Fixes: 683a247ed7a4 ("target/microblaze: Store "current" iflags in insn_sta= rt") Reported-by: Thomas Huth Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- target/microblaze/cpu.c | 11 +++++++++++ target/microblaze/helper.c | 17 +++++++++++------ target/microblaze/translate.c | 4 ++-- 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d11b6fa995..a25a2b427f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -270,7 +270,8 @@ struct CPUMBState { #define D_FLAG (1 << 19) /* Bit in ESR. */ =20 /* TB dependent CPUMBState. */ -#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_= FLAG) +#define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ + DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) =20 uint32_t iflags; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 67017ecc33..6392524135 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -80,6 +80,16 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 cpu->env.pc =3D value; + /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ + cpu->env.iflags =3D 0; +} + +static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + cpu->env.pc =3D tb->pc; + cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 static bool mb_cpu_has_work(CPUState *cs) @@ -321,6 +331,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; + cc->synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tlb_fill =3D mb_cpu_tlb_fill; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 48547385b0..00090526da 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -113,7 +113,10 @@ void mb_cpu_do_interrupt(CPUState *cs) uint32_t t, msr =3D mb_cpu_read_msr(env); =20 /* IMM flag cannot propagate across a branch and into the dslot. */ - assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); + assert((env->iflags & (D_FLAG | IMM_FLAG)) !=3D (D_FLAG | IMM_FLAG)); + /* BIMM flag cannot be set without D_FLAG. */ + assert((env->iflags & (D_FLAG | BIMM_FLAG)) !=3D BIMM_FLAG); + /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); env->res_addr =3D RES_ADDR_NONE; switch (cs->exception_index) { @@ -146,7 +149,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &=3D ~(IMM_FLAG | D_FLAG); + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 @@ -186,14 +189,14 @@ void mb_cpu_do_interrupt(CPUState *cs) "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &=3D ~(IMM_FLAG | D_FLAG); + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 case EXCP_IRQ: assert(!(msr & (MSR_EIP | MSR_BIP))); assert(msr & MSR_IE); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 t =3D (msr & (MSR_VM | MSR_UM)) << 1; =20 @@ -226,13 +229,14 @@ void mb_cpu_do_interrupt(CPUState *cs) mb_cpu_write_msr(env, msr); =20 env->regs[14] =3D env->pc; + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; =20 case EXCP_HW_BREAK: - assert(!(env->iflags & IMM_FLAG)); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + t =3D (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", @@ -242,6 +246,7 @@ void mb_cpu_do_interrupt(CPUState *cs) msr |=3D t; msr |=3D MSR_BIP; env->regs[16] =3D env->pc; + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a377818b5e..a8a3249185 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -91,8 +91,8 @@ static int typeb_imm(DisasContext *dc, int x) static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); + if ((dc->tb_flags ^ dc->base.tb->flags) & IFLAGS_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & IFLAGS_TB_MASK); } } =20 --=20 2.25.1