From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599118081; cv=none; d=zohomail.com; s=zohoarc; b=FevYvGte2kuRyhrxHrdL43HZUAP59rm0puzUehWWCBajzqpAF0hHJdmAFTS79zcZqvzdtcWSFShZWS7sHzESE/lgY0+WWIbnlQ96Shx6Vr8jrbPm3R/TfmOZ5qLLkSwjIMM2PhSbHCugOiwgJpmDgWft7bC2OTjksnCEcpEXWqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599118081; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bF4Mg8kcTZXoqQQUyRlGmfPMUb1QHX4VgeyA3hgWEws=; b=OF1Mny5kUxNqYiv40KBRbAv5RozXRiaKr+5/J0gtMriqb9nG7KQzdJmaxRdjsKUHgRuPHI1iU81kQXHVBDgadYrV6WubjgZ+PgdcPALaYsaXmYmOaziLvZmou9J5AdWiWZ1gJBxaRk4W14wQlU9LpNqcYmXVjPHCMTmG4r3usg8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599118079601234.42531685428582; Thu, 3 Sep 2020 00:27:59 -0700 (PDT) Received: from localhost ([::1]:38462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kDjf4-0003kD-LW for importer@patchew.org; Thu, 03 Sep 2020 03:27:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kDje5-0001mD-T6 for qemu-devel@nongnu.org; Thu, 03 Sep 2020 03:26:57 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kDje4-0001lB-1V for qemu-devel@nongnu.org; Thu, 03 Sep 2020 03:26:57 -0400 Received: by mail-pg1-x541.google.com with SMTP id 31so1390525pgy.13 for ; Thu, 03 Sep 2020 00:26:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.141.89]) by smtp.gmail.com with ESMTPSA id x185sm1930229pfc.188.2020.09.03.00.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 00:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bF4Mg8kcTZXoqQQUyRlGmfPMUb1QHX4VgeyA3hgWEws=; b=BNUCe9OGdtJ6H+UdrcrIx1AoZdoJF6WKOsllsZANixGvj7lKVoM1fVXoPQjsth24Uv /TlFU2DggIeQ8bQlphdfpCN48lSW/oBmCC0e4fD1pckV3qI5NKvwTQXejVwUpOaICN7A l3u+Fr9BaR0b5TfVjs12eHurmZPC9PWG/GFRCBAcpNR0QxGFFEf+QmRBanN6X554B8+8 DLNTo/1l1JhdV4zO1YOlyfrYIhFfBL8PBc1M7tZsKW857g8Bq9bBsF2Suh7BADZlSPJa SEe3KR4OojBZbTlymWWjKKYFlUtwsJacJXcd7fUwCLpYF/qp0/RJCKovQ4Z7Dk6FkHnM wFzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bF4Mg8kcTZXoqQQUyRlGmfPMUb1QHX4VgeyA3hgWEws=; b=RYx4hMgCKumNoWaFSOHmDzkaTSLRIQegPRKwagchvUgtfBQMOnnx/Id7C2dFtzAekE kwwsqvRHPILg/Uehy0XZktahWxvXXkMG8vXVRZyARRaOfyX9HZEw8tNutju3o+rDmgms EYaEDYoX9Y3DuQvtFi5ILONMQT/OQatZwqulR/kANLiR1wYj70BSV9zNDXHaPoOO7yUq ujEjqFwur+8uCZ6FBHnk8UnJNwkxd6xInNbEGcWJ/Wf7EtJNHjO+3GMJ38Uqj8+2v1SI czodpvmDxnkgl1aFK102Rm2dL2QyiPyP8G6Ko3Z5+q7MGcRWPymvFB+F7RC0Z8fRdkPs mCOA== X-Gm-Message-State: AOAM533FmVDmucdscEXzjzw4QNK/L161gTwpGLST6PIcJvDTUuS+jWOu oKmTqmHqSsq6L1b1WcFbkPsB6bzL9C6nSQ== X-Google-Smtp-Source: ABdhPJxU/etOyyLiODyCbINHSnKa+AkbE8nHJswFicxTJndaNk9h64997V1X6U31S3o5sJBOR8CfbQ== X-Received: by 2002:aa7:83cf:: with SMTP id j15mr2472327pfn.251.1599118013988; Thu, 03 Sep 2020 00:26:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/12] target/microblaze: Collected fixes for env->iflags Date: Thu, 3 Sep 2020 00:26:39 -0700 Message-Id: <20200903072650.1360454-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" There are several problems here that can result in soft lockup, depending on exactly where an interrupt or exception is delivered: Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG. Ensure that iflags is 0 when entering an interrupt/exception handler. Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags. The change to t_sync_flags is cosmetic, but makes the code clearer. This fixes the reported regression in acceptance/replay_kernel.py. Fixes: 683a247ed7a4 ("target/microblaze: Store "current" iflags in insn_sta= rt") Reported-by: Thomas Huth Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/cpu.h | 3 ++- target/microblaze/cpu.c | 11 +++++++++++ target/microblaze/helper.c | 17 +++++++++++------ target/microblaze/translate.c | 4 ++-- 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d11b6fa995..a25a2b427f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -270,7 +270,8 @@ struct CPUMBState { #define D_FLAG (1 << 19) /* Bit in ESR. */ =20 /* TB dependent CPUMBState. */ -#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_= FLAG) +#define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ + DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) =20 uint32_t iflags; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 67017ecc33..6392524135 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -80,6 +80,16 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 cpu->env.pc =3D value; + /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ + cpu->env.iflags =3D 0; +} + +static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + cpu->env.pc =3D tb->pc; + cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 static bool mb_cpu_has_work(CPUState *cs) @@ -321,6 +331,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; + cc->synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tlb_fill =3D mb_cpu_tlb_fill; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 48547385b0..00090526da 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -113,7 +113,10 @@ void mb_cpu_do_interrupt(CPUState *cs) uint32_t t, msr =3D mb_cpu_read_msr(env); =20 /* IMM flag cannot propagate across a branch and into the dslot. */ - assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); + assert((env->iflags & (D_FLAG | IMM_FLAG)) !=3D (D_FLAG | IMM_FLAG)); + /* BIMM flag cannot be set without D_FLAG. */ + assert((env->iflags & (D_FLAG | BIMM_FLAG)) !=3D BIMM_FLAG); + /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); env->res_addr =3D RES_ADDR_NONE; switch (cs->exception_index) { @@ -146,7 +149,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &=3D ~(IMM_FLAG | D_FLAG); + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 @@ -186,14 +189,14 @@ void mb_cpu_do_interrupt(CPUState *cs) "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags &=3D ~(IMM_FLAG | D_FLAG); + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 case EXCP_IRQ: assert(!(msr & (MSR_EIP | MSR_BIP))); assert(msr & MSR_IE); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 t =3D (msr & (MSR_VM | MSR_UM)) << 1; =20 @@ -226,13 +229,14 @@ void mb_cpu_do_interrupt(CPUState *cs) mb_cpu_write_msr(env, msr); =20 env->regs[14] =3D env->pc; + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; =20 case EXCP_HW_BREAK: - assert(!(env->iflags & IMM_FLAG)); - assert(!(env->iflags & D_FLAG)); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + t =3D (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", @@ -242,6 +246,7 @@ void mb_cpu_do_interrupt(CPUState *cs) msr |=3D t; msr |=3D MSR_BIP; env->regs[16] =3D env->pc; + env->iflags =3D 0; env->pc =3D cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a377818b5e..a8a3249185 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -91,8 +91,8 @@ static int typeb_imm(DisasContext *dc, int x) static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); + if ((dc->tb_flags ^ dc->base.tb->flags) & IFLAGS_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & IFLAGS_TB_MASK); } } =20 --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599118082; cv=none; d=zohomail.com; s=zohoarc; b=MkeX5/5mp4vnjRNGIJti6L5UBcErv4m+2k4FMBzkMI4PTqJdOpfYCYUoYByEI6JEcMzAFJXigUcd0ZPcID3GK5n1qAF9/FyPcD9TaK8kcHwscXFYx5hynpDObsVlVfzix1RvoCHzAxfDd5d+vyj6S026gVnFpxAXwuRcTrIyyXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599118082; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" ESS[DS] is bit 19 in the manual, but the manual uses big-endian bit numbering. This corresponds to bit 12 in little-endian numbering. Let the comment about matching the ESR be true by renumbering it. Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a25a2b427f..32811f773d 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -264,10 +264,10 @@ struct CPUMBState { /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp= */ +#define D_FLAG (1 << 12) /* Bit in ESR. */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) -#define D_FLAG (1 << 19) /* Bit in ESR. */ =20 /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2020 00:26:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/12] target/microblaze: Cleanup mb_cpu_do_interrupt Date: Thu, 3 Sep 2020 00:26:41 -0700 Message-Id: <20200903072650.1360454-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reindent; remove dead/commented code. Use D_FLAG to set ESS[DS]. Sink MSR adjustment for kernel entry, iflags and res_addr clear. Improve CPU_LOG_INT formatting; report pc and msr before and after. Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/helper.c | 209 ++++++++++++++++--------------------- 1 file changed, 91 insertions(+), 118 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 00090526da..27a24bb99a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -111,6 +111,7 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; uint32_t t, msr =3D mb_cpu_read_msr(env); + bool set_esr; =20 /* IMM flag cannot propagate across a branch and into the dslot. */ assert((env->iflags & (D_FLAG | IMM_FLAG)) !=3D (D_FLAG | IMM_FLAG)); @@ -118,142 +119,114 @@ void mb_cpu_do_interrupt(CPUState *cs) assert((env->iflags & (D_FLAG | BIMM_FLAG)) !=3D BIMM_FLAG); /* RTI flags are private to translate. */ assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); - env->res_addr =3D RES_ADDR_NONE; + switch (cs->exception_index) { - case EXCP_HW_EXCP: - if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { - qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system= without exceptions!\n"); - return; - } + case EXCP_HW_EXCP: + if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Exception raised on system without exceptions!\= n"); + return; + } =20 - env->regs[17] =3D env->pc + 4; - env->esr &=3D ~(1 << 12); + qemu_log_mask(CPU_LOG_INT, + "INT: HWE at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); =20 - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |=3D 1 << 12 ; - env->btr =3D env->btarget; - } + /* Exception breaks branch + dslot sequence? */ + set_esr =3D true; + env->esr &=3D ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |=3D D_FLAG; + env->btr =3D env->btarget; + } =20 - /* Disable the MMU. */ - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - /* Exception in progress. */ - msr |=3D MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Exception in progress. */ + msr |=3D MSR_EIP; + env->regs[17] =3D env->pc + 4; + env->pc =3D cpu->cfg.base_vectors + 0x20; + break; =20 - qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=3D%x ear=3D%" PRIx64 " " - "esr=3D%x iflags=3D%x\n", - env->pc, env->ear, - env->esr, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x20; - break; + case EXCP_MMU: + qemu_log_mask(CPU_LOG_INT, + "INT: MMU at pc=3D%08x msr=3D%08x " + "ear=3D%" PRIx64 " iflags=3D%x\n", + env->pc, msr, env->ear, env->iflags); =20 - case EXCP_MMU: + /* Exception breaks branch + dslot sequence? */ + set_esr =3D true; + env->esr &=3D ~D_FLAG; + if (env->iflags & D_FLAG) { + env->esr |=3D D_FLAG; + env->btr =3D env->btarget; + /* Reexecute the branch. */ + env->regs[17] =3D env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); + } else if (env->iflags & IMM_FLAG) { + /* Reexecute the imm. */ + env->regs[17] =3D env->pc - 4; + } else { env->regs[17] =3D env->pc; + } =20 - qemu_log_mask(CPU_LOG_INT, - "MMU exception at pc=3D%x iflags=3D%x ear=3D%" P= RIx64 "\n", - env->pc, env->iflags, env->ear); + /* Exception in progress. */ + msr |=3D MSR_EIP; + env->pc =3D cpu->cfg.base_vectors + 0x20; + break; =20 - env->esr &=3D ~(1 << 12); - /* Exception breaks branch + dslot sequence? */ - if (env->iflags & D_FLAG) { - env->esr |=3D 1 << 12 ; - env->btr =3D env->btarget; + case EXCP_IRQ: + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 - /* Reexecute the branch. */ - env->regs[17] -=3D 4; - /* was the branch immprefixed?. */ - if (env->iflags & BIMM_FLAG) { - env->regs[17] -=3D 4; - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - } - } else if (env->iflags & IMM_FLAG) { - env->regs[17] -=3D 4; - } + qemu_log_mask(CPU_LOG_INT, + "INT: DEV at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); + set_esr =3D false; =20 - /* Disable the MMU. */ - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - /* Exception in progress. */ - msr |=3D MSR_EIP; - mb_cpu_write_msr(env, msr); + /* Disable interrupts. */ + msr &=3D ~MSR_IE; + env->regs[14] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x10; + break; =20 - qemu_log_mask(CPU_LOG_INT, - "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", - env->pc, env->ear, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x20; - break; + case EXCP_HW_BREAK: + assert(!(env->iflags & (D_FLAG | IMM_FLAG))); =20 - case EXCP_IRQ: - assert(!(msr & (MSR_EIP | MSR_BIP))); - assert(msr & MSR_IE); - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); + qemu_log_mask(CPU_LOG_INT, + "INT: BRK at pc=3D%08x msr=3D%08x iflags=3D%x\n", + env->pc, msr, env->iflags); + set_esr =3D false; =20 - t =3D (msr & (MSR_VM | MSR_UM)) << 1; + /* Break in progress. */ + msr |=3D MSR_BIP; + env->regs[16] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x18; + break; =20 -#if 0 -#include "disas/disas.h" + default: + cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_ind= ex); + /* not reached */ + } =20 -/* Useful instrumentation when debugging interrupt issues in either - the models or in sw. */ - { - const char *sym; + /* Save previous mode, disable mmu, disable user-mode. */ + t =3D (msr & (MSR_VM | MSR_UM)) << 1; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |=3D t; + mb_cpu_write_msr(env, msr); =20 - sym =3D lookup_symbol(env->pc); - if (sym - && (!strcmp("netif_rx", sym) - || !strcmp("process_backlog", sym))) { + env->res_addr =3D RES_ADDR_NONE; + env->iflags =3D 0; =20 - qemu_log("interrupt at pc=3D%x msr=3D%x %x iflags=3D%x= sym=3D%s\n", - env->pc, msr, t, env->iflags, sym); - - log_cpu_state(cs, 0); - } - } -#endif - qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, msr, t, env->iflags); - - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - msr |=3D t; - mb_cpu_write_msr(env, msr); - - env->regs[14] =3D env->pc; - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, cs, 0); - break; - - case EXCP_HW_BREAK: - assert(!(env->iflags & (D_FLAG | IMM_FLAG))); - - t =3D (msr & (MSR_VM | MSR_UM)) << 1; - qemu_log_mask(CPU_LOG_INT, - "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, msr, t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, cs, 0); - msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - msr |=3D t; - msr |=3D MSR_BIP; - env->regs[16] =3D env->pc; - env->iflags =3D 0; - env->pc =3D cpu->cfg.base_vectors + 0x18; - mb_cpu_write_msr(env, msr); - break; - default: - cpu_abort(cs, "unhandled exception type=3D%d\n", - cs->exception_index); - break; + if (!set_esr) { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x\n", env->pc, msr); + } else if (env->esr & D_FLAG) { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x esr=3D%04x btr=3D%= 08x\n", + env->pc, msr, env->esr, env->btr); + } else { + qemu_log_mask(CPU_LOG_INT, + " to pc=3D%08x msr=3D%08x esr=3D%04x\n", + env->pc, msr, env->esr); } } =20 --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Introduce typedefs and follow CODING_STYLE for naming. Rename struct microblaze_mmu to MicroBlazeMMU. Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Thomas Huth --- target/microblaze/cpu.h | 2 +- target/microblaze/mmu.h | 15 ++++++--------- target/microblaze/helper.c | 4 ++-- target/microblaze/mmu.c | 11 +++++------ 4 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 32811f773d..20c2979396 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -278,7 +278,7 @@ struct CPUMBState { =20 #if !defined(CONFIG_USER_ONLY) /* Unified MMU. */ - struct microblaze_mmu mmu; + MicroBlazeMMU mmu; #endif =20 /* Fields up to this point are cleared by a CPU reset */ diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 75e5301c79..c1feb811b9 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -63,8 +63,7 @@ =20 #define TLB_ENTRIES 64 =20 -struct microblaze_mmu -{ +typedef struct { /* Data and tag brams. */ uint64_t rams[2][TLB_ENTRIES]; /* We keep a separate ram for the tids to avoid the 48 bit tag width. = */ @@ -76,10 +75,9 @@ struct microblaze_mmu int c_mmu_tlb_access; int c_mmu_zones; uint64_t c_addr_mask; /* Mask to apply to physical addresses. */ -}; +} MicroBlazeMMU; =20 -struct microblaze_mmu_lookup -{ +typedef struct { uint32_t paddr; uint32_t vaddr; unsigned int size; @@ -88,13 +86,12 @@ struct microblaze_mmu_lookup enum { ERR_PROT, ERR_MISS, ERR_HIT } err; -}; +} MicroBlazeMMULookup; =20 -unsigned int mmu_translate(struct microblaze_mmu *mmu, - struct microblaze_mmu_lookup *lu, +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx); uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); -void mmu_init(struct microblaze_mmu *mmu); +void mmu_init(MicroBlazeMMU *mmu); =20 #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 27a24bb99a..3c2fd388fb 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -52,7 +52,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int siz= e, { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; unsigned int hit; int prot; =20 @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr a= ddr) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; target_ulong vaddr, paddr =3D 0; - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; int mmu_idx =3D cpu_mmu_index(env, false); unsigned int hit; =20 diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6e583d78d9..0546cfd0bc 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -35,7 +35,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { CPUState *cs =3D env_cpu(env); - struct microblaze_mmu *mmu =3D &env->mmu; + MicroBlazeMMU *mmu =3D &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; =20 @@ -55,7 +55,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int i= dx) =20 static void mmu_change_pid(CPUMBState *env, unsigned int newpid)=20 { - struct microblaze_mmu *mmu =3D &env->mmu; + MicroBlazeMMU *mmu =3D &env->mmu; unsigned int i; uint32_t t; =20 @@ -73,8 +73,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int = newpid) } =20 /* rw - 0 =3D read, 1 =3D write, 2 =3D fetch. */ -unsigned int mmu_translate(struct microblaze_mmu *mmu, - struct microblaze_mmu_lookup *lu, +unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu, target_ulong vaddr, int rw, int mmu_idx) { unsigned int i, hit =3D 0; @@ -290,7 +289,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) break; case MMU_R_TLBSX: { - struct microblaze_mmu_lookup lu; + MicroBlazeMMULookup lu; int hit; =20 if (env->mmu.c_mmu_tlb_access <=3D 1) { @@ -314,7 +313,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) } } =20 -void mmu_init(struct microblaze_mmu *mmu) +void mmu_init(MicroBlazeMMU *mmu) { int i; for (i =3D 0; i < ARRAY_SIZE(mmu->regs); i++) { --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Tested-by: Thomas Huth --- target/microblaze/cpu.h | 4 ++ target/microblaze/cpu.c | 8 +-- target/microblaze/machine.c | 112 ++++++++++++++++++++++++++++++++++ target/microblaze/meson.build | 5 +- 4 files changed, 121 insertions(+), 8 deletions(-) create mode 100644 target/microblaze/machine.c diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 20c2979396..133ebaa4d4 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -419,4 +419,8 @@ static inline int cpu_mmu_index(CPUMBState *env, bool i= fetch) return MMU_KERNEL_IDX; } =20 +#ifndef CONFIG_USER_ONLY +extern const VMStateDescription vmstate_mb_cpu; +#endif + #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6392524135..388605ccca 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -26,7 +26,6 @@ #include "cpu.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -#include "migration/vmstate.h" #include "exec/exec-all.h" #include "fpu/softfloat-helpers.h" =20 @@ -254,11 +253,6 @@ static void mb_cpu_initfn(Object *obj) #endif } =20 -static const VMStateDescription vmstate_mb_cpu =3D { - .name =3D "cpu", - .unmigratable =3D 1, -}; - static Property mb_properties[] =3D { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, @@ -338,8 +332,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; -#endif dc->vmsd =3D &vmstate_mb_cpu; +#endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; =20 diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c new file mode 100644 index 0000000000..aad3c5d1d3 --- /dev/null +++ b/target/microblaze/machine.c @@ -0,0 +1,112 @@ +/* + * Microblaze VMState for qemu. + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "migration/cpu.h" + + +static VMStateField vmstate_mmu_fields[] =3D { + VMSTATE_UINT64_2DARRAY(rams, MicroBlazeMMU, 2, TLB_ENTRIES), + VMSTATE_UINT8_ARRAY(tids, MicroBlazeMMU, TLB_ENTRIES), + VMSTATE_UINT32_ARRAY(regs, MicroBlazeMMU, 3), + VMSTATE_INT32(c_mmu, MicroBlazeMMU), + VMSTATE_INT32(c_mmu_tlb_access, MicroBlazeMMU), + VMSTATE_INT32(c_mmu_zones, MicroBlazeMMU), + VMSTATE_UINT64(c_addr_mask, MicroBlazeMMU), + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_mmu =3D { + .name =3D "mmu", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D vmstate_mmu_fields, +}; + +static int get_msr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + CPUMBState *env =3D container_of(opaque, CPUMBState, msr); + + mb_cpu_write_msr(env, qemu_get_be32(f)); + return 0; +} + +static int put_msr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + CPUMBState *env =3D container_of(opaque, CPUMBState, msr); + + qemu_put_be32(f, mb_cpu_read_msr(env)); + return 0; +} + +static const VMStateInfo vmstate_msr =3D { + .name =3D "msr", + .get =3D get_msr, + .put =3D put_msr, +}; + +static VMStateField vmstate_env_fields[] =3D { + VMSTATE_UINT32_ARRAY(regs, CPUMBState, 32), + + VMSTATE_UINT32(pc, CPUMBState), + VMSTATE_SINGLE(msr, CPUMBState, 0, vmstate_msr, uint32_t), + VMSTATE_UINT32(esr, CPUMBState), + VMSTATE_UINT32(fsr, CPUMBState), + VMSTATE_UINT32(btr, CPUMBState), + VMSTATE_UINT32(edr, CPUMBState), + VMSTATE_UINT32(slr, CPUMBState), + VMSTATE_UINT32(shr, CPUMBState), + VMSTATE_UINT64(ear, CPUMBState), + + VMSTATE_UINT32(btarget, CPUMBState), + VMSTATE_UINT32(imm, CPUMBState), + VMSTATE_UINT32(iflags, CPUMBState), + + VMSTATE_UINT32(res_val, CPUMBState), + VMSTATE_UINTTL(res_addr, CPUMBState), + + VMSTATE_UINT32_ARRAY(pvr.regs, CPUMBState, 13), + + VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU), + + VMSTATE_END_OF_LIST() +}; + +static const VMStateDescription vmstate_env =3D { + .name =3D "env", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D vmstate_env_fields, +}; + +static VMStateField vmstate_cpu_fields[] =3D { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, MicroBlazeCPU, 1, vmstate_env, CPUMBState), + VMSTATE_END_OF_LIST() +}; + +const VMStateDescription vmstate_mb_cpu =3D { + .name =3D "cpu", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D vmstate_cpu_fields, +}; diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 639c3f73a8..05ee0ec163 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -11,7 +11,10 @@ microblaze_ss.add(files( )) =20 microblaze_softmmu_ss =3D ss.source_set() -microblaze_softmmu_ss.add(files('mmu.c')) +microblaze_softmmu_ss.add(files( + 'mmu.c', + 'machine.c', +)) =20 target_arch +=3D {'microblaze': microblaze_ss} target_softmmu_arch +=3D {'microblaze': microblaze_softmmu_ss} --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The name "update" suggests that something needs updating, but this is not the case. Use "exit" to emphasize that nothing needs doing except to exit. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Thomas Huth --- target/microblaze/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a8a3249185..8ceb04f4f0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -37,7 +37,7 @@ =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically= */ =20 static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -1161,7 +1161,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br = *arg) tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); tcg_gen_movi_tl(cpu_res_addr, -1); =20 - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; return true; } =20 @@ -1202,7 +1202,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br= *arg) ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); } tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; #endif =20 return true; @@ -1712,7 +1712,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } } @@ -1733,7 +1733,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUS= tate *cs) gen_goto_tb(dc, 0, dc->base.pc_next); return; =20 - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2020 00:27:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/12] target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP Date: Thu, 3 Sep 2020 00:26:45 -0700 Message-Id: <20200903072650.1360454-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Like DISAS_EXIT, except we need to update cpu_pc, either to pc_next or to btarget respectively. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/translate.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8ceb04f4f0..2abef328a3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -39,6 +39,11 @@ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically= */ =20 +/* cpu state besides pc was modified dynamically; update pc to next */ +#define DISAS_EXIT_NEXT DISAS_TARGET_2 +/* cpu state besides pc was modified dynamically; update pc to btarget */ +#define DISAS_EXIT_JUMP DISAS_TARGET_3 + static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1712,8 +1717,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_EXIT; - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + dc->base.is_jmp =3D DISAS_EXIT_NEXT; } } =20 @@ -1734,12 +1738,14 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CP= UState *cs) return; =20 case DISAS_EXIT: - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - return; + break; + case DISAS_EXIT_NEXT: + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + break; + case DISAS_EXIT_JUMP: + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + break; =20 case DISAS_JUMP: if (dc->jmp_dest !=3D -1 && !cs->singlestep_enabled) { @@ -1781,6 +1787,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPU= State *cs) default: g_assert_not_reached(); } + + /* Finish DISAS_EXIT_* */ + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } } =20 static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Rather than look for the combination of DISAS_NEXT with a separate variable, go ahead and set is_jmp to the desired state. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/translate.c | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2abef328a3..6bf299a826 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -70,7 +70,6 @@ typedef struct DisasContext { =20 /* Decoder. */ uint32_t ext_imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1255,7 +1254,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *ar= g) * * Therefore, choose to end the TB always. */ - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; return true; } =20 @@ -1307,19 +1306,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } =20 -#ifndef CONFIG_USER_ONLY -static void msr_write(DisasContext *dc, TCGv_i32 v) -{ - dc->cpustate_changed =3D 1; - - /* Install MSR_C. */ - tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); - - /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clea= r. */ - tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); -} -#endif - static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { uint32_t imm =3D arg->imm; @@ -1352,7 +1338,7 @@ static bool do_msrclrset(DisasContext *dc, arg_type_m= sr *arg, bool set) } else { tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); } - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; } return true; } @@ -1385,7 +1371,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) TCGv_i32 src =3D reg_for_read(dc, arg->ra); switch (arg->rs) { case SR_MSR: - msr_write(dc, src); + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, src, 2, 1); + /* + * Clear MSR_C and MSR_CC; + * MSR_PVR is not writable, and is always clear. + */ + tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR)); break; case SR_FSR: tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); @@ -1417,7 +1409,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); return true; } - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; return true; #endif } @@ -1629,7 +1621,6 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) =20 dc->cpu =3D cpu; dc->tb_flags =3D dc->base.tb->flags; - dc->cpustate_changed =3D 0; dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; @@ -1714,11 +1705,6 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) } dc->base.is_jmp =3D DISAS_JUMP; } - - /* Force an exit if the per-tb cpu state has changed. */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_EXIT_NEXT; - } } =20 static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2020 00:27:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/12] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot Date: Thu, 3 Sep 2020 00:26:47 -0700 Message-Id: <20200903072650.1360454-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" It is legal to put an mts instruction into a delay slot. We should continue to return to the main loop in that case so that we recognize any pending interrupts. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/translate.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6bf299a826..608d413c83 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1696,6 +1696,10 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) dc->base.pc_next +=3D 4; =20 if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { + /* + * Finish any return-from branch. + * TODO: Diagnose rtXd in delay slot of rtYd earlier. + */ if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } else if (dc->tb_flags & DRTB_FLAG) { @@ -1703,7 +1707,35 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - dc->base.is_jmp =3D DISAS_JUMP; + + /* Complete the branch, ending the TB. */ + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + /* + * E.g. illegal insn in a delay slot. We've already exited + * and will handle D_FLAG in mb_cpu_do_interrupt. + */ + break; + case DISAS_EXIT: + /* + * TODO: diagnose brk/brki in delay slot earlier. + * This would then fold into the illegal insn case above. + */ + break; + case DISAS_NEXT: + /* Normal insn a delay slot. */ + dc->base.is_jmp =3D DISAS_JUMP; + break; + case DISAS_EXIT_NEXT: + /* + * E.g. mts insn in a delay slot. Continue with btarget, + * but still return to the main loop. + */ + dc->base.is_jmp =3D DISAS_EXIT_JUMP; + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599118158; cv=none; d=zohomail.com; s=zohoarc; b=UOdxM+mXKznxnzFjwCIke/K38zNlnG8noh1lBqsyddo1WQDQZFLPvpNZuzTIPoNuVcd5fimCWApBM1hL3ZkFJz1DnXCgRuhQkI2NMb+y+o4OTavAPogKdrBau7nUqTTsSXM6cybxbZRSaprgsDzQfU9bGcF+oifBceRgLkY1eeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599118158; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These return-from-exception type instructions have modified MSR to re-enable various forms of interrupt. Force a return to the main loop. Consolidate the cleanup of tb_flags into mb_tr_translate_insn. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/translate.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 608d413c83..da84fdb20b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1518,7 +1518,6 @@ static void do_rti(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTI_FLAG; } =20 static void do_rtb(DisasContext *dc) @@ -1531,7 +1530,6 @@ static void do_rtb(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTB_FLAG; } =20 static void do_rte(DisasContext *dc) @@ -1545,7 +1543,6 @@ static void do_rte(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTE_FLAG; } =20 /* Insns connected to FSL or AXI stream attached devices. */ @@ -1700,12 +1697,16 @@ static void mb_tr_translate_insn(DisasContextBase *= dcb, CPUState *cs) * Finish any return-from branch. * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ - if (dc->tb_flags & DRTI_FLAG) { - do_rti(dc); - } else if (dc->tb_flags & DRTB_FLAG) { - do_rtb(dc); - } else if (dc->tb_flags & DRTE_FLAG) { - do_rte(dc); + uint32_t rt_ibe =3D dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_F= LAG); + if (unlikely(rt_ibe !=3D 0)) { + dc->tb_flags &=3D ~(DRTI_FLAG | DRTB_FLAG | DRTE_FLAG); + if (rt_ibe & DRTI_FLAG) { + do_rti(dc); + } else if (rt_ibe & DRTB_FLAG) { + do_rtb(dc); + } else { + do_rte(dc); + } } =20 /* Complete the branch, ending the TB. */ @@ -1723,8 +1724,12 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) */ break; case DISAS_NEXT: - /* Normal insn a delay slot. */ - dc->base.is_jmp =3D DISAS_JUMP; + /* + * Normal insn a delay slot. + * However, the return-from-exception type insns should + * return to the main loop, as they have adjusted MSR. + */ + dc->base.is_jmp =3D (rt_ibe ? DISAS_EXIT_JUMP : DISAS_JUMP); break; case DISAS_EXIT_NEXT: /* --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599118360; cv=none; d=zohomail.com; s=zohoarc; b=SBdPlCjybeYDj5T5sxzvlB6vG8UtlVOb0OUz09+tSXYnd4S/IxjS/PmIbvegnxcK/gpUm1nU+HmyiD3PN4G1YNLp8bKGSkB1C9ZnHIWHOpMwXwwOquHBuvXssew5TxCVLiauDICb3LiGpCRKuN5X6RGcW9PDOjOcql50V0sKYSw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599118360; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hA0Q3ZvS9ZMt8mExwk35iB2Bwjpw4Nf408fgP9XSgOU=; b=Pvs2rqRgIjmSiz6kOxucRlA0esjqNfTFQkjteX37reDNctcO2eubGR9mrYO6bSyL1xviWgKv2zUsW7MEkKGbU4anW1nD15NwlnRPwPn70cEp6XHHj7BqQ2fxAvguq62D7ioO9np62U194hCx9bwJa/DvxoUpgqrVvkX15EDpZW4= ARC-Authentication-Results: i=1; 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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hA0Q3ZvS9ZMt8mExwk35iB2Bwjpw4Nf408fgP9XSgOU=; b=kAaonSp8KH5UcDwprlO7jpi8Drp2K50sqke0wbbR9LFwM+RhagJQ+U2omKyn+eWyJr td2b5hIbvZC1sbtj4thatHBiaRJq50r+rurcDKi59xL2w+6bG1rk5lmOt0INNtz3rdUO eN/FvHdbWifRHGPitqSIy8e5vVW+CWQzj0n0iXCqoX9uK7//PpDffyqBl9j17NzQhapK aq7wILlK5aWIoNV1AzgHolEGVj+bxeGf6rVtsfnKX0vaOMJc4PgAOdTiATL/elWnzvdv vLxN15GI213lSQQRgSaslAG5r26xXUWJu4Mfs6RRxNcLlws5n0NULDnsMfwGjjI7CvgY IEBQ== X-Gm-Message-State: AOAM532x9qynuMVUrb02E/VmNLMZUFyTtxth+DihaWWZZhWYtdUX1Py9 qKSwMGGR1VDZmprS+/ptaDP4VS41Vj0GLQ== X-Google-Smtp-Source: ABdhPJz0K0qsPjhdvOiAKvQ3ZIhi/y8KhOiLhZ7QhQwmM8S4CeQlASG0ZAd59+YjniIpo+3w7ouluQ== X-Received: by 2002:a17:902:9a44:: with SMTP id x4mr2542364plv.31.1599118027052; Thu, 03 Sep 2020 00:27:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/12] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Date: Thu, 3 Sep 2020 00:26:49 -0700 Message-Id: <20200903072650.1360454-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Normal indirect jumps, or page-crossing direct jumps, can use tcg_gen_lookup_and_goto_ptr to avoid returning to the main loop simply to find an existing TB for the next pc. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Tested-by: Thomas Huth --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index da84fdb20b..d98572fab9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -147,7 +147,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp =3D DISAS_NORETURN; } @@ -1803,7 +1803,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUS= tate *cs) if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } return; =20 --=20 2.25.1 From nobody Sun Nov 16 05:40:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Sep 2020 00:27:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/12] target/microblaze: Diagnose invalid insns in delay slots Date: Thu, 3 Sep 2020 00:26:50 -0700 Message-Id: <20200903072650.1360454-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903072650.1360454-1-richard.henderson@linaro.org> References: <20200903072650.1360454-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, thuth@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) These cases result in undefined and undocumented behaviour but the behaviour is deterministic, i.e cores will not lock-up or expose security issues. However, RTL will not raise exceptions either. Therefore, log a GUEST_ERROR and treat these cases as nops, to avoid corner cases which could put qemu into an invalid state. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Tested-by: Thomas Huth --- v2: Log pc as well. --- target/microblaze/translate.c | 48 ++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d98572fab9..ff0cb7dbb6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,21 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } =20 +/* + * Return true, and log an error, if the current insn is + * within a delay slot. + */ +static bool invalid_delay_slot(DisasContext *dc, const char *insn_type) +{ + if (dc->tb_flags & D_FLAG) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid insn in delay slot: %s at %08x\n", + insn_type, (uint32_t)dc->base.pc_next); + return true; + } + return false; +} + static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg !=3D 0)) { @@ -500,6 +515,9 @@ DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) =20 static bool trans_imm(DisasContext *dc, arg_imm *arg) { + if (invalid_delay_slot(dc, "imm")) { + return true; + } dc->ext_imm =3D arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags_to_set =3D IMM_FLAG; @@ -1067,6 +1085,9 @@ static bool do_branch(DisasContext *dc, int dest_rb, = int dest_imm, { uint32_t add_pc; =20 + if (invalid_delay_slot(dc, "branch")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1106,6 +1127,9 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int= dest_imm, { TCGv_i32 zero, next; =20 + if (invalid_delay_slot(dc, "bcc")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1158,6 +1182,10 @@ static bool trans_brk(DisasContext *dc, arg_typea_br= *arg) if (trap_userspace(dc, true)) { return true; } + if (invalid_delay_slot(dc, "brk")) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1176,6 +1204,10 @@ static bool trans_brki(DisasContext *dc, arg_typeb_b= r *arg) if (trap_userspace(dc, imm !=3D 0x8 && imm !=3D 0x18)) { return true; } + if (invalid_delay_slot(dc, "brki")) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1216,6 +1248,11 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *a= rg) { int mbar_imm =3D arg->imm; =20 + /* Note that mbar is a specialized branch instruction. */ + if (invalid_delay_slot(dc, "mbar")) { + return true; + } + /* Data access memory barrier. */ if ((mbar_imm & 2) =3D=3D 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1263,6 +1300,10 @@ static bool do_rts(DisasContext *dc, arg_typeb_bc *a= rg, int to_set) if (trap_userspace(dc, to_set)) { return true; } + if (invalid_delay_slot(dc, "rts")) { + return true; + } + dc->tb_flags_to_set |=3D to_set; setup_dslot(dc, true); =20 @@ -1695,7 +1736,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { /* * Finish any return-from branch. - * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ uint32_t rt_ibe =3D dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_F= LAG); if (unlikely(rt_ibe !=3D 0)) { @@ -1717,12 +1757,6 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) * and will handle D_FLAG in mb_cpu_do_interrupt. */ break; - case DISAS_EXIT: - /* - * TODO: diagnose brk/brki in delay slot earlier. - * This would then fold into the illegal insn case above. - */ - break; case DISAS_NEXT: /* * Normal insn a delay slot. --=20 2.25.1