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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These cases result in undefined and undocumented behaviour but the behaviour is deterministic, i.e cores will not lock-up or expose security issues. However, RTL will not raise exceptions either. Therefore, log a GUEST_ERROR and treat these cases as nops, to avoid corner cases which could put qemu into an invalid state. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/translate.c | 47 +++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4416361d08..caa4831aed 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,20 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } =20 +/* + * Return true, and log an error, if the current insn is + * within a delay slot. + */ +static bool invalid_delay_slot(DisasContext *dc, const char *insn_type) +{ + if (dc->tb_flags & D_FLAG) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid insn in delay slot: %s\n", insn_type); + return true; + } + return false; +} + static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg !=3D 0)) { @@ -500,6 +514,9 @@ DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) =20 static bool trans_imm(DisasContext *dc, arg_imm *arg) { + if (invalid_delay_slot(dc, "imm")) { + return true; + } dc->ext_imm =3D arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags_to_set =3D IMM_FLAG; @@ -1067,6 +1084,9 @@ static bool do_branch(DisasContext *dc, int dest_rb, = int dest_imm, { uint32_t add_pc; =20 + if (invalid_delay_slot(dc, "branch")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1106,6 +1126,9 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int= dest_imm, { TCGv_i32 zero, next; =20 + if (invalid_delay_slot(dc, "bcc")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1158,6 +1181,10 @@ static bool trans_brk(DisasContext *dc, arg_typea_br= *arg) if (trap_userspace(dc, true)) { return true; } + if (invalid_delay_slot(dc, "brk")) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1176,6 +1203,10 @@ static bool trans_brki(DisasContext *dc, arg_typeb_b= r *arg) if (trap_userspace(dc, imm !=3D 0x8 && imm !=3D 0x18)) { return true; } + if (invalid_delay_slot(dc, "brki")) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1216,6 +1247,11 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *a= rg) { int mbar_imm =3D arg->imm; =20 + /* Note that mbar is a specialized branch instruction. */ + if (invalid_delay_slot(dc, "mbar")) { + return true; + } + /* Data access memory barrier. */ if ((mbar_imm & 2) =3D=3D 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1263,6 +1299,10 @@ static bool do_rts(DisasContext *dc, arg_typeb_bc *a= rg, int to_set) if (trap_userspace(dc, to_set)) { return true; } + if (invalid_delay_slot(dc, "rts")) { + return true; + } + dc->tb_flags_to_set |=3D to_set; setup_dslot(dc, true); =20 @@ -1695,7 +1735,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { /* * Finish any return-from branch. - * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ uint32_t rt_ibe =3D dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_F= LAG); if (unlikely(rt_ibe !=3D 0)) { @@ -1717,12 +1756,6 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) * and will handle D_FLAG in mb_cpu_do_interrupt. */ break; - case DISAS_EXIT: - /* - * TODO: diagnose brk/brki in delay slot earlier. - * This would then fold into the illegal insn case above. - */ - break; case DISAS_NEXT: /* * Normal insn a delay slot. --=20 2.25.1