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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The name "update" suggests that something needs updating, but this is not the case. Use "exit" to emphasize that nothing needs doing except to exit. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a377818b5e..03fc653ce2 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -37,7 +37,7 @@ =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically= */ =20 static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -1161,7 +1161,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br = *arg) tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); tcg_gen_movi_tl(cpu_res_addr, -1); =20 - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; return true; } =20 @@ -1202,7 +1202,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br= *arg) ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); } tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; #endif =20 return true; @@ -1712,7 +1712,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_EXIT; tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } } @@ -1733,7 +1733,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUS= tate *cs) gen_goto_tb(dc, 0, dc->base.pc_next); return; =20 - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 02 Sep 2020 09:36:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/7] target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP Date: Wed, 2 Sep 2020 09:35:54 -0700 Message-Id: <20200902163559.1077728-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200902163559.1077728-1-richard.henderson@linaro.org> References: <20200902163559.1077728-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Like DISAS_EXIT, except we need to update cpu_pc, either to pc_next or to btarget respectively. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 03fc653ce2..0733728794 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -39,6 +39,11 @@ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_EXIT DISAS_TARGET_1 /* all cpu state modified dynamically= */ =20 +/* cpu state besides pc was modified dynamically; update pc to next */ +#define DISAS_EXIT_NEXT DISAS_TARGET_2 +/* cpu state besides pc was modified dynamically; update pc to btarget */ +#define DISAS_EXIT_JUMP DISAS_TARGET_3 + static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1712,8 +1717,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 /* Force an exit if the per-tb cpu state has changed. */ if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_EXIT; - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + dc->base.is_jmp =3D DISAS_EXIT_NEXT; } } =20 @@ -1734,12 +1738,14 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CP= UState *cs) return; =20 case DISAS_EXIT: - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - return; + break; + case DISAS_EXIT_NEXT: + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + break; + case DISAS_EXIT_JUMP: + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + break; =20 case DISAS_JUMP: if (dc->jmp_dest !=3D -1 && !cs->singlestep_enabled) { @@ -1781,6 +1787,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPU= State *cs) default: g_assert_not_reached(); } + + /* Finish DISAS_EXIT_* */ + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } } =20 static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Rather than look for the combination of DISAS_NEXT with a separate variable, go ahead and set is_jmp to the desired state. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0733728794..9c52448c06 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -70,7 +70,6 @@ typedef struct DisasContext { =20 /* Decoder. */ uint32_t ext_imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1255,7 +1254,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *ar= g) * * Therefore, choose to end the TB always. */ - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; return true; } =20 @@ -1307,19 +1306,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } =20 -#ifndef CONFIG_USER_ONLY -static void msr_write(DisasContext *dc, TCGv_i32 v) -{ - dc->cpustate_changed =3D 1; - - /* Install MSR_C. */ - tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); - - /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clea= r. */ - tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); -} -#endif - static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { uint32_t imm =3D arg->imm; @@ -1352,7 +1338,7 @@ static bool do_msrclrset(DisasContext *dc, arg_type_m= sr *arg, bool set) } else { tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); } - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; } return true; } @@ -1385,7 +1371,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) TCGv_i32 src =3D reg_for_read(dc, arg->ra); switch (arg->rs) { case SR_MSR: - msr_write(dc, src); + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, src, 2, 1); + /* + * Clear MSR_C and MSR_CC; + * MSR_PVR is not writable, and is always clear. + */ + tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR)); break; case SR_FSR: tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); @@ -1417,7 +1409,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); return true; } - dc->cpustate_changed =3D 1; + dc->base.is_jmp =3D DISAS_EXIT_NEXT; return true; #endif } @@ -1629,7 +1621,6 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) =20 dc->cpu =3D cpu; dc->tb_flags =3D dc->base.tb->flags; - dc->cpustate_changed =3D 0; dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; @@ -1714,11 +1705,6 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) } dc->base.is_jmp =3D DISAS_JUMP; } - - /* Force an exit if the per-tb cpu state has changed. */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { - dc->base.is_jmp =3D DISAS_EXIT_NEXT; - } } =20 static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 02 Sep 2020 09:36:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/7] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot Date: Wed, 2 Sep 2020 09:35:56 -0700 Message-Id: <20200902163559.1077728-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200902163559.1077728-1-richard.henderson@linaro.org> References: <20200902163559.1077728-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" It is legal to put an mts instruction into a delay slot. We should continue to return to the main loop in that case so that we recognize any pending interrupts. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9c52448c06..459b25f8b9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1696,6 +1696,10 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) dc->base.pc_next +=3D 4; =20 if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { + /* + * Finish any return-from branch. + * TODO: Diagnose rtXd in delay slot of rtYd earlier. + */ if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } else if (dc->tb_flags & DRTB_FLAG) { @@ -1703,7 +1707,35 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - dc->base.is_jmp =3D DISAS_JUMP; + + /* Complete the branch, ending the TB. */ + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + /* + * E.g. illegal insn in a delay slot. We've already exited + * and will handle D_FLAG in mb_cpu_do_interrupt. + */ + break; + case DISAS_EXIT: + /* + * TODO: diagnose brk/brki in delay slot earlier. + * This would then fold into the illegal insn case above. + */ + break; + case DISAS_NEXT: + /* Normal insn a delay slot. */ + dc->base.is_jmp =3D DISAS_JUMP; + break; + case DISAS_EXIT_NEXT: + /* + * E.g. mts insn in a delay slot. Continue with btarget, + * but still return to the main loop. + */ + dc->base.is_jmp =3D DISAS_EXIT_JUMP; + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599064795; cv=none; d=zohomail.com; s=zohoarc; b=c75F65BC4avNMHc4igR1kHEPI+kPZfip6TKf7GggCr2TUWE2xJns+8L5ie5uXrkus3feJLm20g/lSFqF5Vzstv9FT6FLF2uKiLYS6l7CDBgGma+XHm2AadUV3oVR/upz8kn9Q8rrKE0+q3rBV0gdQnuhAEtpnoMGZfVXlzBnEGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599064795; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These return-from-exception type instructions have modified MSR to re-enable various forms of interrupt. Force a return to the main loop. Consolidate the cleanup of tb_flags into mb_tr_translate_insn. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 459b25f8b9..a94f3e340e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1518,7 +1518,6 @@ static void do_rti(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTI_FLAG; } =20 static void do_rtb(DisasContext *dc) @@ -1531,7 +1530,6 @@ static void do_rtb(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTB_FLAG; } =20 static void do_rte(DisasContext *dc) @@ -1545,7 +1543,6 @@ static void do_rte(DisasContext *dc) tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 tcg_temp_free_i32(tmp); - dc->tb_flags &=3D ~DRTE_FLAG; } =20 /* Insns connected to FSL or AXI stream attached devices. */ @@ -1700,12 +1697,16 @@ static void mb_tr_translate_insn(DisasContextBase *= dcb, CPUState *cs) * Finish any return-from branch. * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ - if (dc->tb_flags & DRTI_FLAG) { - do_rti(dc); - } else if (dc->tb_flags & DRTB_FLAG) { - do_rtb(dc); - } else if (dc->tb_flags & DRTE_FLAG) { - do_rte(dc); + uint32_t rt_ibe =3D dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_F= LAG); + if (unlikely(rt_ibe !=3D 0)) { + dc->tb_flags &=3D ~(DRTI_FLAG | DRTB_FLAG | DRTE_FLAG); + if (rt_ibe & DRTI_FLAG) { + do_rti(dc); + } else if (rt_ibe & DRTB_FLAG) { + do_rtb(dc); + } else { + do_rte(dc); + } } =20 /* Complete the branch, ending the TB. */ @@ -1723,8 +1724,12 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) */ break; case DISAS_NEXT: - /* Normal insn a delay slot. */ - dc->base.is_jmp =3D DISAS_JUMP; + /* + * Normal insn a delay slot. + * However, the return-from-exception type insns should + * return to the main loop, as they have adjusted MSR. + */ + dc->base.is_jmp =3D (rt_ibe ? DISAS_EXIT_JUMP : DISAS_JUMP); break; case DISAS_EXIT_NEXT: /* --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599064947; cv=none; d=zohomail.com; s=zohoarc; b=UOBK0Vr1W1532pIvOislJX+XOKx6Wu3uTVA1mlKYSrGG6+B7C+xffJF8a9RnjhaZF//w3iI65nw+1x6BSACZc0vYhkUooeTxEgT79UX/vktnvT/CKsj+Iya7ZkIPrizdJNvwb71dEEFj0/DkH3j+//Ajt0akuB54gX9TIjHwjB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599064947; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T5+4Hm8QKZkxl4HUg0KhrOXM6aaOJZgbxYaiAZNZh2c=; b=QRndRXQpN9J9X4Sfu7ywOSvDqJ/11EshN7eGRPfcRCGwpWaI0Sb3yyS8VjD5Pm3l4S54eHRld3kW7CL6J12cFV1wRDDtk5z1vofuSW9iopJzI9g8xlHrhPSMQJ3NgSDd5ZJTK7/l6YDB64vX58KkbNPEbW+f6oudZKzG1Uy+YKo= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Normal indirect jumps, or page-crossing direct jumps, can use tcg_gen_lookup_and_goto_ptr to avoid returning to the main loop simply to find an existing TB for the next pc. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a94f3e340e..4416361d08 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -147,7 +147,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp =3D DISAS_NORETURN; } @@ -1803,7 +1803,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUS= tate *cs) if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } return; =20 --=20 2.25.1 From nobody Sun Nov 16 05:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 02 Sep 2020 09:36:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 7/7] target/microblaze: Diagnose invalid insns in delay slots Date: Wed, 2 Sep 2020 09:35:59 -0700 Message-Id: <20200902163559.1077728-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200902163559.1077728-1-richard.henderson@linaro.org> References: <20200902163559.1077728-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These cases result in undefined and undocumented behaviour but the behaviour is deterministic, i.e cores will not lock-up or expose security issues. However, RTL will not raise exceptions either. Therefore, log a GUEST_ERROR and treat these cases as nops, to avoid corner cases which could put qemu into an invalid state. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/translate.c | 47 +++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4416361d08..caa4831aed 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -179,6 +179,20 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } =20 +/* + * Return true, and log an error, if the current insn is + * within a delay slot. + */ +static bool invalid_delay_slot(DisasContext *dc, const char *insn_type) +{ + if (dc->tb_flags & D_FLAG) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid insn in delay slot: %s\n", insn_type); + return true; + } + return false; +} + static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg !=3D 0)) { @@ -500,6 +514,9 @@ DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) =20 static bool trans_imm(DisasContext *dc, arg_imm *arg) { + if (invalid_delay_slot(dc, "imm")) { + return true; + } dc->ext_imm =3D arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags_to_set =3D IMM_FLAG; @@ -1067,6 +1084,9 @@ static bool do_branch(DisasContext *dc, int dest_rb, = int dest_imm, { uint32_t add_pc; =20 + if (invalid_delay_slot(dc, "branch")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1106,6 +1126,9 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int= dest_imm, { TCGv_i32 zero, next; =20 + if (invalid_delay_slot(dc, "bcc")) { + return true; + } if (delay) { setup_dslot(dc, dest_rb < 0); } @@ -1158,6 +1181,10 @@ static bool trans_brk(DisasContext *dc, arg_typea_br= *arg) if (trap_userspace(dc, true)) { return true; } + if (invalid_delay_slot(dc, "brk")) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1176,6 +1203,10 @@ static bool trans_brki(DisasContext *dc, arg_typeb_b= r *arg) if (trap_userspace(dc, imm !=3D 0x8 && imm !=3D 0x18)) { return true; } + if (invalid_delay_slot(dc, "brki")) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); if (arg->rd) { tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); @@ -1216,6 +1247,11 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *a= rg) { int mbar_imm =3D arg->imm; =20 + /* Note that mbar is a specialized branch instruction. */ + if (invalid_delay_slot(dc, "mbar")) { + return true; + } + /* Data access memory barrier. */ if ((mbar_imm & 2) =3D=3D 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1263,6 +1299,10 @@ static bool do_rts(DisasContext *dc, arg_typeb_bc *a= rg, int to_set) if (trap_userspace(dc, to_set)) { return true; } + if (invalid_delay_slot(dc, "rts")) { + return true; + } + dc->tb_flags_to_set |=3D to_set; setup_dslot(dc, true); =20 @@ -1695,7 +1735,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { /* * Finish any return-from branch. - * TODO: Diagnose rtXd in delay slot of rtYd earlier. */ uint32_t rt_ibe =3D dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_F= LAG); if (unlikely(rt_ibe !=3D 0)) { @@ -1717,12 +1756,6 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) * and will handle D_FLAG in mb_cpu_do_interrupt. */ break; - case DISAS_EXIT: - /* - * TODO: diagnose brk/brki in delay slot earlier. - * This would then fold into the illegal insn case above. - */ - break; case DISAS_NEXT: /* * Normal insn a delay slot. --=20 2.25.1