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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm2242317wma.4.2020.09.01.08.18.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 08:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rXGC6L9myFmYS2wUnlHsK7hg9ZJdOSE4jVlndthBJQE=; b=FFKv7Bs5Zh6uNvsI5iJa/CFcWOik6hT9Lyc8yzbOa0R40CktuOhAji0OxyiDLAnVUY eu17sNbffrPNoavxTUHT/e1SfosNGvRfoJMVZzdEeSKlxE+Btukj7yD0P59yt7QztusL HHaayxmEmTmr/JPYE1SoHMehhgCFMbckAQMACeL7DX1VeahNF6/eUIRNVHU2er3xAFHS 586+DBJPVcKnNTtycFlAtlJ9oxPrPUVd95qLv4qfwJFo4KcMtQyLPHyuQcRlgCBDUAp7 fAsn8HixarR7Ipi4VEp7Y8BxganTdbbH5/k4Ju7B0eS+/Nk1rj1xIcYfIubmDXXjIREb TBSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rXGC6L9myFmYS2wUnlHsK7hg9ZJdOSE4jVlndthBJQE=; b=qbZhK9L9OdcFF71P4mkf87OoFJ8OedGs7GkZdyNHIrdVa8JivfOZjqyRm4IY8xhkM2 kA9JZiHbRJuDdBJCsYvXaIEx87XDwBJwM6cgqmJbDDC3HFCYzclQfPQ11VX84xOWsfSh S15weQoBNfqZaEo6G4tBMswA2I0WEfhgJadvcs147GozKLH/dFfB0K8e3bpTnq2tZThQ XBfjds7/lKrCrB0waQGbC65Wd9G+1hxDtTh3Tlqhl/S0Ijgi+dfZY7HIO2BOOb+EOTb0 vHwfdRJTMJBtM/UaY2ksMPqLNyHzW6+LP6RtIM5UPVCRbIJ3UePKe0ZqtsF249xvJqnU N4VQ== X-Gm-Message-State: AOAM532h3/P6Gu0jJxSe8935Nz2kISCLmglZIHwpu/Uw93q5hDl9fG+G wfsHh/0Pf9qMFRhN3OMvXaQx1S3IPZBXTepk X-Google-Smtp-Source: ABdhPJxTuLhBTTzb2F8Fh3AD7461pjyGQ6/FYdZ9imB42SIqlFziC0wYkRf8aJYJuSC7uDfkYk7hYQ== X-Received: by 2002:a1c:e256:: with SMTP id z83mr2325238wmg.33.1598973508003; Tue, 01 Sep 2020 08:18:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/47] target/arm: Use correct ID register check for aa32_fp16_arith Date: Tue, 1 Sep 2020 16:17:38 +0100 Message-Id: <20200901151823.29785-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200901151823.29785-1-peter.maydell@linaro.org> References: <20200901151823.29785-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The aa32_fp16_arith feature check function currently looks at the AArch64 ID_AA64PFR0 register. This is (as the comment notes) not correct. The bogus check was put in mostly to allow testing of the fp16 variants of the VCMLA instructions and it was something of a mistake that we allowed them to exist in master. Switch the feature check function to testing VMFR1.FPHP, which is what it ought to be. This will remove emulation of the VCMLA and VCADD insns from AArch32 code running on an AArch64 '-cpu max' using system emulation. (They were never enabled for aarch32 linux-user and system-emulation.) Since we weren't advertising their existence via the AArch32 ID register, well-behaved guests wouldn't have been using them anyway. Once we have implemented all the AArch32 support for the FP16 extension we will advertise it in the MVFR1 ID register field, which will reenable these insns along with all the others. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200828183354.27913-3-peter.maydell@linaro.org --- target/arm/cpu.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ac857bdc2c1..a1c7d8ebae5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3519,12 +3519,7 @@ static inline bool isar_feature_aa32_predinv(const A= RMISARegisters *id) =20 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { - /* - * This is a placeholder for use by VCMA until the rest of - * the ARMv8.2-FP16 extension is implemented for aa32 mode. - * At which point we can properly set and check MVFR1.FPHP. - */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >=3D 3; } =20 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) --=20 2.20.1