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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm2242317wma.4.2020.09.01.08.18.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 08:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=znDMfNw/x+bDEAmrLcSJSrfAUXdWqj8CB9fQetbEyRQ=; b=nmgEjulrwo9cv8E8ovavPp9sw/kN27Xb1Q2QlKxBmdIAxN8meruOOMga3C3XLhnaxp Ss/FUp0ZamJmY3uLUjy+ksMmVKbuKlk6yE33Tr56xeDET2zPLBhUo31YaQAIhiR7msRj NkO3BbeI4eFtSAnq9Z7gsMt5iIfbppf0oOeCKGd7J38J9GF/X2loSbAenfWHlfwImFy6 4dSS5rskysygAFnswNj/eYQ25Yx45Sszx52mZXvE4F+U8BimLnfvptjy8hqchwHbtTWH c7wL0EmEPNQPa/kX7aar4rOrXCchFlQiwJP7ZFZ6lgdX/UK05+vZpMB5br99ch50hX/S J3TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=znDMfNw/x+bDEAmrLcSJSrfAUXdWqj8CB9fQetbEyRQ=; b=F4uHnXQzC2yQit2r0V5ANbeJI/PMAVwR8I4zB/A8dODZpjlM8n5zciLM3+teigLBtU RkwQXrGwoerbpLHXrcS/fzPMmQJe1U4b1JQQgpa/0qnGmsoCN54gG5zf5EKtMaX9tnHB sGo/1s7DT+iGPMqoNpoi0BZSFAeTAqK5SJb42hROTmb76jfkcsLRWX/8mW1Y6FB8naOK fdNiGv76HLUl68QapHY+oahUXIzbH80Mn+xg/lAl02tiaNvaGIt5l/pbtxjpmbPh6OoW iQZBrdkBdykq4PX51r6M9rcqFrk6sOddc8B93rv8nxWbHQ+Wu+KgDUk0FZSB9dmt5qgq umgw== X-Gm-Message-State: AOAM530yriM0e9HqS1LdH1lRGSdc92wiV6vZ3yW0/LT5+J3SecGHBfZT +UIjMroXxxphD1kJl2Bx6YbcvYWyRgSPvK3A X-Google-Smtp-Source: ABdhPJwO04cjPWlaAIgHqkZgXXd+trAkF5BgB6dmwBWdK5whUqB/A11XFdnoBqd3Ve9bvCIHDQCQpQ== X-Received: by 2002:a7b:c84a:: with SMTP id c10mr2227363wml.139.1598973532092; Tue, 01 Sep 2020 08:18:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/47] target/arm: Implement new VFP fp16 insn VMOVX Date: Tue, 1 Sep 2020 16:17:56 +0100 Message-Id: <20200901151823.29785-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200901151823.29785-1-peter.maydell@linaro.org> References: <20200901151823.29785-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The fp16 extension includes a new instruction VMOVX, which copies the upper 16 bits of a 32-bit source VFP register into the lower 16 bits of the destination and zeroes the high half of the destination. Implement it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200828183354.27913-21-peter.maydell@linaro.org --- target/arm/vfp-uncond.decode | 3 +++ target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 39dc8f6373a..8891ab3d549 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -75,5 +75,8 @@ VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 ...= . \ VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ vm=3D%vm_dp vd=3D%vd_sp sz=3D3 =20 +VMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \ + vd=3D%vd_sp vm=3D%vm_sp + VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \ vd=3D%vd_sp vm=3D%vm_sp diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index bda3dd25136..4b26156eccc 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3482,3 +3482,28 @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) tcg_temp_free_i32(rd); return true; } + +static bool trans_VMOVX(DisasContext *s, arg_VINS *a) +{ + TCGv_i32 rm; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Set Vd to high half of Vm */ + rm =3D tcg_temp_new_i32(); + neon_load_reg32(rm, a->vm); + tcg_gen_shri_i32(rm, rm, 16); + neon_store_reg32(rm, a->vd); + tcg_temp_free_i32(rm); + return true; +} --=20 2.20.1