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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm2242317wma.4.2020.09.01.08.18.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 08:18:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LYksQpOrC4uDUd5NAXsivhjz1yQJ3P5MVc1zocuiPzY=; b=Sv3ZBdhV7snhiS4X/1NbvHdKleBdTf7pFVtm4TegSeHW9Ht5AgZPCEI5iumBRjO28T 3SjydRDd/LQKAdE5UtCLmR/EZ8wyKcCdS0m5YQbJ4TQrfdtvxmCqF3jzGPfHCDa51AOa /ZvVdghHTh377SiAV6qW3M1E2vpwElEb0YqrnQiIKm4ET2MDL/+5pRCPE3snkRVCkuBn JF9bk5SAVxBD1oEthcPZe3cVO/Noi8xuMoDbAWNBwR8PJoO0u9Y/rzdSrKPcCN0ysJ0M bN6q4SYzd7JXVfXQG175/GGBoizXs1+7JU5hpo+tQL4agPu8DpdsPZpxN8JRM7z8hPH9 FXmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LYksQpOrC4uDUd5NAXsivhjz1yQJ3P5MVc1zocuiPzY=; b=gnfWCHUilnlG9u2gqeoiz1xhYk7mc2H1qiGjTw9JmiE2CnxKPR+JYgY61xlWsDE1k9 gZAYbu5mul95J5qlBIoDNkFqmCNLBlCFwWolJPPaUIGj4EIBlCAzN7rVI4A9kPgE80a6 4Injk/n4cvjxA5gLm5wrsE89lY63g+hwxbd1fZfFEOsBy/7me2uovAht7Lxr47/S1lFe N01SZC6YgeYxsUsQcEfhabFZAELDySrKR3HBqArsBG+zYKi15vfmbmD65J3O73CbiCFy i0fFQR9+2yrly5YBp0X60Hp5IzeNaYjnW418CCTAFXWeHQxllcZD0yXKwN6YVUcmDIh7 5qjw== X-Gm-Message-State: AOAM5305ZBD3bfCO+Lh8Q89pgS/6UQD+97Pm/El+lG4zpPWneVr3nftL Jmf2Hns83M9UZ9mD8O0YJ/fvDMBF4MtmM4t5 X-Google-Smtp-Source: ABdhPJzi6Y5TbsqwZOAmNr+bVpuCuJhl+Xi9n9f4ndoSpdqMzMxEgzMJsD0XjXw1Wa9mAvlVlDfgjw== X-Received: by 2002:a7b:c056:: with SMTP id u22mr2300067wmc.188.1598973522280; Tue, 01 Sep 2020 08:18:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/47] target/arm: Implement VFP fp16 VCVT between float and integer Date: Tue, 1 Sep 2020 16:17:48 +0100 Message-Id: <20200901151823.29785-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200901151823.29785-1-peter.maydell@linaro.org> References: <20200901151823.29785-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200828183354.27913-13-peter.maydell@linaro.org --- target/arm/vfp.decode | 4 +++ target/arm/translate-vfp.c.inc | 65 ++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 37f96e2d261..642ec039e3c 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -210,6 +210,8 @@ VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... = @vfp_dm_ds VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT from integer to floating point: Vm always single; Vd depends on size +VCVT_int_hp ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ @@ -229,6 +231,8 @@ VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ vd=3D%vd_dp imm=3D%vm_sp opc=3D%vcvt_fix_op =20 # VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on = size +VCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 59ef4d4fbc3..0140822d183 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -2845,6 +2845,35 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_= dp *a) return true; } =20 +static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm =3D tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + if (a->s) { + /* i32 -> f16 */ + gen_helper_vfp_sitoh(vm, vm, fpst); + } else { + /* u32 -> f16 */ + gen_helper_vfp_uitoh(vm, vm, fpst); + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) { TCGv_i32 vm; @@ -3067,6 +3096,42 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return true; } =20 +static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + vm =3D tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizh(vm, vm, fpst); + } else { + gen_helper_vfp_tosih(vm, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizh(vm, vm, fpst); + } else { + gen_helper_vfp_touih(vm, vm, fpst); + } + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) { TCGv_i32 vm; --=20 2.20.1