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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/translate.c | 24 +++++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a5df1fa28f..83fadd36a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + struct CPUMBState { uint32_t btaken; uint32_t btarget; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 97a436c8d5..d2ee163294 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; =20 + /* TCG op of the current insn_start. */ + TCGOp *insn_start; + TCGv_i32 r0; bool r0_set; =20 @@ -71,7 +74,7 @@ typedef struct DisasContext { =20 unsigned int cpustate_changed; unsigned int delayed_branch; - unsigned int tb_flags, synced_flags; /* tb dependent flags. */ + unsigned int tb_flags; unsigned int clear_imm; int mem_index; =20 @@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" =20 -static inline void t_sync_flags(DisasContext *dc) +static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if (dc->tb_flags !=3D dc->synced_flags) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); - dc->synced_flags =3D dc->tb_flags; + if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); } } =20 @@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr= , MemOp mop, } } =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 /* @@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); @@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, } } =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); @@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) TCGLabel *swx_fail =3D gen_new_label(); TCGv_i32 tval; =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 /* swx does not throw unaligned access errors, so force alignment */ @@ -1655,7 +1653,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) int bound; =20 dc->cpu =3D cpu; - dc->synced_flags =3D dc->tb_flags =3D dc->base.tb->flags; + dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; @@ -1675,7 +1673,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CP= UState *cs) =20 static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) { - tcg_gen_insn_start(dcb->pc_next); + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + dc->insn_start =3D tcg_last_op(); } =20 static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, @@ -1917,4 +1918,5 @@ void restore_state_to_opc(CPUMBState *env, Translatio= nBlock *tb, target_ulong *data) { env->pc =3D data[0]; + env->iflags =3D data[1]; } --=20 2.25.1