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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 92 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 73e8973597..e65ec051a5 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,58 +21,80 @@ #include "cpu.h" #include "exec/gdbstub.h" =20 +/* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + +enum { + GDB_PC =3D 32 + 0, + GDB_MSR =3D 32 + 1, + GDB_EAR =3D 32 + 2, + GDB_ESR =3D 32 + 3, + GDB_FSR =3D 32 + 4, + GDB_BTR =3D 32 + 5, + GDB_PVR0 =3D 32 + 6, + GDB_PVR11 =3D 32 + 17, + GDB_EDR =3D 32 + 18, + GDB_SLR =3D 32 + 25, + GDB_SHR =3D 32 + 26, +}; + int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUClass *cc =3D CPU_GET_CLASS(cs); CPUMBState *env =3D &cpu->env; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLB= HI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything and return a value of 0 instead. - */ - static const uint8_t sreg_map[6] =3D { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; + uint32_t val; =20 - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { - return gdb_get_reg32(mem_buf, env->regs[n]); - } else { - n -=3D 32; - switch (n) { - case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); - /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -=3D 6; - return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18: - return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); - /* Other SRegs aren't modeled, so report a value of 0 */ - case 19 ... 24: - return gdb_get_reg32(mem_buf, 0); - case 25: - return gdb_get_reg32(mem_buf, env->slr); - case 26: - return gdb_get_reg32(mem_buf, env->shr); - default: - return 0; - } + if (n > cc->gdb_num_core_regs) { + return 0; } + + switch (n) { + case 1 ... 31: + val =3D env->regs[n]; + break; + case GDB_PC: + val =3D env->sregs[SR_PC]; + break; + case GDB_MSR: + val =3D env->sregs[SR_MSR]; + break; + case GDB_EAR: + val =3D env->sregs[SR_EAR]; + break; + case GDB_ESR: + val =3D env->sregs[SR_ESR]; + break; + case GDB_FSR: + val =3D env->sregs[SR_FSR]; + break; + case GDB_BTR: + val =3D env->sregs[SR_BTR]; + break; + case GDB_PVR0 ... GDB_PVR11: + /* PVR12 is intentionally skipped */ + val =3D env->pvr.regs[n - GDB_PVR0]; + break; + case GDB_EDR: + val =3D env->sregs[SR_EDR]; + break; + case GDB_SLR: + val =3D env->slr; + break; + case GDB_SHR: + val =3D env->shr; + break; + default: + /* Other SRegs aren't modeled, so report a value of 0 */ + val =3D 0; + break; + } + return gdb_get_reg32(mem_buf, val); } =20 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) CPUMBState *env =3D &cpu->env; uint32_t tmp; =20 - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLB= HI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything. - */ - static const uint8_t sreg_map[6] =3D { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; - if (n > cc->gdb_num_core_regs) { return 0; } =20 tmp =3D ldl_p(mem_buf); =20 - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { + switch (n) { + case 1 ... 31: env->regs[n] =3D tmp; - } else { - n -=3D 32; - switch (n) { - case 0 ... 5: - env->sregs[sreg_map[n]] =3D tmp; - break; + break; + case GDB_PC: + env->sregs[SR_PC] =3D tmp; + break; + case GDB_MSR: + env->sregs[SR_MSR] =3D tmp; + break; + case GDB_EAR: + env->sregs[SR_EAR] =3D tmp; + break; + case GDB_ESR: + env->sregs[SR_ESR] =3D tmp; + break; + case GDB_FSR: + env->sregs[SR_FSR] =3D tmp; + break; + case GDB_BTR: + env->sregs[SR_BTR] =3D tmp; + break; + case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -=3D 6; - env->pvr.regs[n] =3D tmp; - break; - /* Only EDR is modeled in these indeces, so ignore the rest */ - case 18: - env->sregs[SR_EDR] =3D tmp; - break; - case 25: - env->slr =3D tmp; - break; - case 26: - env->shr =3D tmp; - break; - } + env->pvr.regs[n - GDB_PVR0] =3D tmp; + break; + case GDB_EDR: + env->sregs[SR_EDR] =3D tmp; + break; + case GDB_SLR: + env->slr =3D tmp; + break; + case GDB_SHR: + env->shr =3D tmp; + break; } return 4; } --=20 2.25.1