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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Restore the correct PC when an exception must be raised. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d99d98051a..2c59d4492d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -104,13 +104,16 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uin= t32_t b) } =20 /* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env) +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) { + CPUState *cs =3D env_cpu(env); + env->esr =3D ESR_EC_FPU; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } =20 -static void update_fpu_flags(CPUMBState *env, int flags) +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) { int raise =3D 0; =20 @@ -133,7 +136,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { - raise_fpu_exception(env); + raise_fpu_exception(env, ra); } } =20 @@ -148,7 +151,7 @@ uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint3= 2_t b) fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); =20 flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } =20 @@ -162,7 +165,7 @@ uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint= 32_t b) fb.l =3D b; fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } =20 @@ -176,7 +179,7 @@ uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint3= 2_t b) fb.l =3D b; fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } @@ -191,7 +194,7 @@ uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint3= 2_t b) fb.l =3D b; fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } @@ -206,7 +209,7 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, ui= nt32_t b) =20 if (float32_is_signaling_nan(fa.f, &env->fp_status) || float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid); + update_fpu_flags(env, float_flag_invalid, GETPC()); r =3D 1; } =20 @@ -229,7 +232,7 @@ uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, ui= nt32_t b) fb.l =3D b; r =3D float32_lt(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -245,7 +248,7 @@ uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, ui= nt32_t b) fb.l =3D b; r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -261,7 +264,7 @@ uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D float32_le(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 =20 return r; @@ -277,7 +280,7 @@ uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D float32_lt(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } =20 @@ -291,7 +294,7 @@ uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -306,7 +309,7 @@ uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D !float32_lt(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -330,7 +333,7 @@ uint32_t helper_fint(CPUMBState *env, uint32_t a) fa.l =3D a; r =3D float32_to_int32(fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return r; } @@ -344,7 +347,7 @@ uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) fa.l =3D a; fd.l =3D float32_sqrt(fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } --=20 2.25.1