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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer with a specified rounding mode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/vfp-uncond.decode | 6 ++++-- target/arm/translate-vfp.c.inc | 32 ++++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index ee700e51972..b7cd9d11ed5 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -64,7 +64,9 @@ VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ vm=3D%vm_dp vd=3D%vd_dp dp=3D1 =20 # VCVT float to int with specified rounding mode; Vd is always single-prec= ision +VCVT 1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \ + vm=3D%vm_sp vd=3D%vd_sp sz=3D1 VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ - vm=3D%vm_sp vd=3D%vd_sp dp=3D0 + vm=3D%vm_sp vd=3D%vd_sp sz=3D2 VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ - vm=3D%vm_dp vd=3D%vd_sp dp=3D1 + vm=3D%vm_dp vd=3D%vd_sp sz=3D3 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index fdf486b7c15..583e7ccdb20 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -396,7 +396,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) static bool trans_VCVT(DisasContext *s, arg_VCVT *a) { uint32_t rd, rm; - bool dp =3D a->dp; + int sz =3D a->sz; TCGv_ptr fpst; TCGv_i32 tcg_rmode, tcg_shift; int rounding =3D fp_decode_rm[a->rm]; @@ -406,12 +406,16 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + if (sz =3D=3D 3 && !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (sz =3D=3D 1 && !dc_isar_feature(aa32_fp16_arith, s)) { return false; } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (sz =3D=3D 3 && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10= )) { return false; } =20 @@ -422,14 +426,18 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + if (sz =3D=3D 1) { + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + } else { + fpst =3D fpstatus_ptr(FPST_FPCR); + } =20 tcg_shift =3D tcg_const_i32(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 - if (dp) { + if (sz =3D=3D 3) { TCGv_i64 tcg_double, tcg_res; TCGv_i32 tcg_tmp; tcg_double =3D tcg_temp_new_i64(); @@ -451,10 +459,18 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) tcg_single =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); neon_load_reg32(tcg_single, rm); - if (is_signed) { - gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); + if (sz =3D=3D 1) { + if (is_signed) { + gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); + } else { + gen_helper_vfp_toulh(tcg_res, tcg_single, tcg_shift, fpst); + } } else { - gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); + if (is_signed) { + gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); + } else { + gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); + } } neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_res); --=20 2.20.1