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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 18 +++++++++--------- target/microblaze/op_helper.c | 17 ++++++++--------- target/microblaze/translate.c | 6 ++++-- 6 files changed, 27 insertions(+), 25 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c9035b410e..7d94af43ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,6 +239,7 @@ struct CPUMBState { uint64_t pc; uint64_t msr; uint64_t ear; + uint64_t esr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 3c693086f4..c10e3e0261 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env) case EXCP_HW_EXCP: env->regs[17] =3D env->pc + 4; if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |=3D 1 << 12; + env->esr |=3D 1 << 12; env->pc -=3D 4; /* FIXME: if branch was immed, replay the imm as well. */ } =20 env->iflags &=3D ~(IMM_FLAG | D_FLAG); =20 - switch (env->sregs[SR_ESR] & 31) { + switch (env->esr & 31) { case ESR_EC_DIVZERO: info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; @@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env) break; default: fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "= \n", - env->sregs[SR_ESR] & ESR_EC_MASK); + env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e33a613efe..05e22f233d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->ear; break; case GDB_ESR: - val =3D env->sregs[SR_ESR]; + val =3D env->esr; break; case GDB_FSR: val =3D env->sregs[SR_FSR]; @@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->ear =3D tmp; break; case GDB_ESR: - env->sregs[SR_ESR] =3D tmp; + env->esr =3D tmp; break; case GDB_FSR: env->sregs[SR_FSR] =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634781..ea290be780 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, env->ear =3D address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; + env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; + env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 env->regs[17] =3D env->pc + 4; - env->sregs[SR_ESR] &=3D ~(1 << 12); + env->esr &=3D ~(1 << 12); =20 /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |=3D 1 << 12 ; + env->esr |=3D 1 << 12 ; env->sregs[SR_BTR] =3D env->btarget; } =20 @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " "esr=3D%" PRIx64 " iflags=3D%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); env->pc =3D cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] =3D env->pc; =20 - env->sregs[SR_ESR] &=3D ~(1 << 12); + env->esr &=3D ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=3D%d\n", env->bim= m)); - env->sregs[SR_ESR] |=3D 1 << 12 ; + env->esr |=3D 1 << 12 ; env->sregs[SR_BTR] =3D env->btarget; =20 /* Reexecute the branch. */ diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29663..f01cf9be64 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=3D%" PRIx64 "\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%s) eip= =3D%d ie=3D%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t= a, uint32_t b) env->msr |=3D MSR_DZ; =20 if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] =3D ESR_EC_DIVZERO; + env->esr =3D ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint3= 2_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] =3D ESR_EC_FPU; + env->esr =3D ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } =20 @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong add= r, " mask=3D%x, wr=3D%d dr=3Dr%d\n", addr, mask, wr, dr); env->ear =3D addr; - env->sregs[SR_ESR] =3D ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr =3D ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) <<= 5; if (mask =3D=3D 3) { - env->sregs[SR_ESR] |=3D 1 << 11; + env->esr |=3D 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong add= r) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear =3D addr; - env->sregs[SR_ESR] =3D ESR_EC_STACKPROT; + env->esr =3D ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, env->ear =3D addr; if (access_type =3D=3D MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] =3D ESR_EC_INSN_BUS; + env->esr =3D ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] =3D ESR_EC_DATA_BUS; + env->esr =3D ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 62747b02f3..411c7b6e49 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " @@ -1875,8 +1875,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_SR[SR_EAR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); + cpu_SR[SR_ESR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); =20 - for (i =3D SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1