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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 111 ++++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 46 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7066878ac7..013858b8e0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env= , target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; - *cs_base =3D 0; *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 133ec24870..65ce8f3cd6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -61,6 +61,7 @@ typedef struct DisasContext { /* Decoder. */ int type_b; uint32_t ir; + uint32_t ext_imm; uint8_t opcode; uint8_t rd, ra, rb; uint16_t imm; @@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool con= d) return cond_user; } =20 -/* True if ALU operand b is a small immediate that may deserve - faster treatment. */ -static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) +static int32_t dec_alu_typeb_imm(DisasContext *dc) { - /* Immediate insn without the imm prefix ? */ - return dc->type_b && !(dc->tb_flags & IMM_FLAG); + tcg_debug_assert(dc->type_b); + if (dc->tb_flags & IMM_FLAG) { + return dc->ext_imm | dc->imm; + } else { + return (int16_t)dc->imm; + } } =20 static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { - if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); - else - tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); return &cpu_imm; - } else - return &cpu_R[dc->rb]; + } + return &cpu_R[dc->rb]; } =20 static void dec_add(DisasContext *dc) @@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc) =20 static void dec_imm(DisasContext *dc) { - tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); + dc->ext_imm =3D dc->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags |=3D IMM_FLAG; dc->clear_imm =3D 0; } =20 static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { - bool extimm =3D dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot =3D false; TCGv_i32 t32; @@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc,= bool ea, TCGv t) } /* Immediate. */ t32 =3D tcg_temp_new_i32(); - if (!extimm) { - tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); - } else { - tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); tcg_gen_extu_i32_tl(t, t32); tcg_temp_free_i32(t32); =20 @@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } =20 - if (dec_alu_op_b_is_small_imm(dc)) { - int32_t offset =3D (int32_t)((int16_t)dc->imm); /* sign-extend. */ - - tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); + if (dc->type_b) { dc->jmp =3D JMP_DIRECT_CC; - dc->jmp_pc =3D dc->base.pc_next + offset; + dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp =3D JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc) return; } =20 + if (abs && link && !dslot) { + if (dc->type_b) { + /* BRKI */ + uint32_t imm =3D dec_alu_typeb_imm(dc); + if (trap_userspace(dc, imm !=3D 8 && imm !=3D 0x18)) { + return; + } + } else { + /* BRK */ + if (trap_userspace(dc, true)) { + return; + } + } + } + dc->delayed_branch =3D 1; if (dslot) { dec_setup_dslot(dc); } - if (link && dc->rd) + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); + } =20 - dc->jmp =3D JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); - if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && - (dc->imm =3D=3D 8 || dc->imm =3D=3D 0x18)) { + if (dc->type_b) { + uint32_t dest =3D dec_alu_typeb_imm(dc); + + dc->jmp =3D JMP_DIRECT; + dc->jmp_pc =3D dest; + tcg_gen_movi_i32(cpu_btarget, dest); + if (link && !dslot) { + switch (dest) { + case 8: + case 0x18: + gen_raise_exception_sync(dc, EXCP_BREAK); + break; + case 0: + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + } + } + } else { + dc->jmp =3D JMP_INDIRECT; + tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); + if (link && !dslot) { gen_raise_exception_sync(dc, EXCP_BREAK); } - if (dc->imm =3D=3D 0) { - if (trap_userspace(dc, true)) { - return; - } - gen_raise_exception_sync(dc, EXCP_DEBUG); - } } + } else if (dc->type_b) { + dc->jmp =3D JMP_DIRECT; + dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { - if (dec_alu_op_b_is_small_imm(dc)) { - dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D dc->base.pc_next + (int32_t)((int16_t)dc->imm); - } else { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_n= ext); - } + dc->jmp =3D JMP_INDIRECT; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } + tcg_gen_movi_i32(cpu_btaken, 1); } =20 static inline void do_rti(DisasContext *dc) @@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; + dc->ext_imm =3D dc->base.tb->cs_base; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); @@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 dc->clear_imm =3D 1; decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) { + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &=3D ~IMM_FLAG; + tcg_gen_discard_i32(cpu_imm); } dc->base.pc_next +=3D 4; =20 --=20 2.25.1