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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 16 ++++++++-------- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 019e5dfa26..aaac0c9a6c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; uint64_t ear; - uint64_t esr; + uint32_t esr; uint64_t fsr; uint64_t btr; uint64_t edr; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "= \n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) =20 qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%x ear=3D%" PRIx64 " " - "esr=3D%" PRIx64 " iflags=3D%x\n", + "esr=3D%x iflags=3D%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a7f6cb71f1..dc2bec0c99 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; =20 qemu_log("PC=3D%08x\n", env->pc); - qemu_log("rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " + qemu_log("rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e71e7ed01..f63aae6de9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,7 +58,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; -static TCGv_i64 cpu_esr; +static TCGv_i32 cpu_esr; static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; @@ -182,7 +182,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -198,7 +198,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; =20 if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -539,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); break; case SR_ESR: - tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); @@ -580,7 +580,7 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); @@ -1399,7 +1399,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu !=3D 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); + tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu =3D=3D 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1797,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) =20 qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " + qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1866,7 +1866,7 @@ void mb_tcg_init(void) cpu_ear =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_fsr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr =3D --=20 2.25.1