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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t13sm912304wru.65.2020.08.28.02.24.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2020 02:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=R9aJ6ZzsAt8r/J9YsHCHCH48yC3gV9MTgkevSI5WBYE=; b=esPBCtH8k6zN2+mjrIlu+7aSnkyGB53KouSMFOYPQGycSFIYaZUSwMuTVCgA3Yaz3b M3iieF2o/qki/KWEjObITwfFcr6hIVwyRjSFGtIYLmfqntKF7VpAM9RK2fREz5FJOm/g ZSa/GIWQXUonHBZnPGpvIgm0po5C/S7ltszBX9dNOO5q6PzdE5auFsPS/ekyN9EixpSJ mMy+9Yjdj8khfgINzUF/KDdWub+h0s9VTcG4bTS9ymrxQahf4mgqzC1k976FwbQZ96c8 XBxowEdFzR7k10S7R8aDcvWfw876/z4JxcHBP+/DN2QLEvOFgSU6oApcyaHp7tWSfxWp yM0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R9aJ6ZzsAt8r/J9YsHCHCH48yC3gV9MTgkevSI5WBYE=; b=U14zS9VkecApSi4smwJfZsH5R600L1dd1no9Bu9n9jAWcIWRzCBfI5OajKPLuYu08J TZ4f39eHn+kYv/IvkCGmGpBRvE42LdyIb/6KIflH9csnSC4NKtYQj7IDWW2vqmD0TRWn a8JkoMpKGmf1PkhIRFdO13Np0G/GIV59dy24y1FN6ea+iwI4acLnfylok24GEhG8Q90+ UBZRXDVRPX8GOUf8rLOVF37gR6jtaXu3rSJBMqFev+g0c+3kZcDK17wklTBBI7oQrpJH 4TI0RwGND0ys29EnNovBju0JW1qZQrwgTlEBJbO/GnXdMyYuRuUwkJvDIH5Fdl0ZJXwn aoAg== X-Gm-Message-State: AOAM530EGmCisymivRnrhQO/Fz+O2us4s4ENzijhkWfiPPCqH3vYYfxU mue0nzVBQ6ZhX+jOUmiAJjs5daRKrJ8nH/4N X-Google-Smtp-Source: ABdhPJygwu4rUeH+VLpGoELJq/Ad2/OO4utv/AXAr6/zTsaqjrV5LAS4d1QLiErN7r+LAR887Ly/+g== X-Received: by 2002:a5d:5383:: with SMTP id d3mr661370wrv.42.1598606684002; Fri, 28 Aug 2020 02:24:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/35] target/arm: Clean up 4-operand predicate expansion Date: Fri, 28 Aug 2020 10:24:02 +0100 Message-Id: <20200828092413.22206-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200828092413.22206-1-peter.maydell@linaro.org> References: <20200828092413.22206-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move the check for !S into do_pppp_flags, which allows to merge in do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check, to mirror gen_gvec_fn_zzz. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200815013145.539409-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 111 ++++++++++++++----------------------- 1 file changed, 43 insertions(+), 68 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6dac70359b6..5dfc129e73b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -179,31 +179,13 @@ static void do_dupi_z(DisasContext *s, int rd, uint64= _t word) } =20 /* Invoke a vector expander on three Pregs. */ -static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn, - int esz, int rd, int rn, int rm) +static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn, + int rd, int rn, int rm) { - if (sve_access_check(s)) { - unsigned psz =3D pred_gvec_reg_size(s); - gvec_fn(esz, pred_full_reg_offset(s, rd), - pred_full_reg_offset(s, rn), - pred_full_reg_offset(s, rm), psz, psz); - } - return true; -} - -/* Invoke a vector operation on four Pregs. */ -static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op, - int rd, int rn, int rm, int rg) -{ - if (sve_access_check(s)) { - unsigned psz =3D pred_gvec_reg_size(s); - tcg_gen_gvec_4(pred_full_reg_offset(s, rd), - pred_full_reg_offset(s, rn), - pred_full_reg_offset(s, rm), - pred_full_reg_offset(s, rg), - psz, psz, gvec_op); - } - return true; + unsigned psz =3D pred_gvec_reg_size(s); + gvec_fn(MO_64, pred_full_reg_offset(s, rd), + pred_full_reg_offset(s, rn), + pred_full_reg_offset(s, rm), psz, psz); } =20 /* Invoke a vector move on two Pregs. */ @@ -1067,6 +1049,11 @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_= s *a, int mofs =3D pred_full_reg_offset(s, a->rm); int gofs =3D pred_full_reg_offset(s, a->pg); =20 + if (!a->s) { + tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); + return true; + } + if (psz =3D=3D 8) { /* Do the operation and the flags generation in temps. */ TCGv_i64 pd =3D tcg_temp_new_i64(); @@ -1126,19 +1113,24 @@ static bool trans_AND_pppp(DisasContext *s, arg_rpr= r_s *a) .fno =3D gen_helper_sve_and_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else if (a->rn =3D=3D a->rm) { - if (a->pg =3D=3D a->rn) { - return do_mov_p(s, a->rd, a->rn); - } else { - return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->p= g); + + if (!a->s) { + if (!sve_access_check(s)) { + return true; + } + if (a->rn =3D=3D a->rm) { + if (a->pg =3D=3D a->rn) { + do_mov_p(s, a->rd, a->rn); + } else { + gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg); + } + return true; + } else if (a->pg =3D=3D a->rn || a->pg =3D=3D a->rm) { + gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm); + return true; } - } else if (a->pg =3D=3D a->rn || a->pg =3D=3D a->rm) { - return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); } + return do_pppp_flags(s, a, &op); } =20 static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1162,13 +1154,14 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rpr= r_s *a) .fno =3D gen_helper_sve_bic_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else if (a->pg =3D=3D a->rn) { - return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); + + if (!a->s && a->pg =3D=3D a->rn) { + if (sve_access_check(s)) { + gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm); + } + return true; } + return do_pppp_flags(s, a, &op); } =20 static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1192,11 +1185,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr= _s *a) .fno =3D gen_helper_sve_eor_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); - } + return do_pppp_flags(s, a, &op); } =20 static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1222,11 +1211,11 @@ static bool trans_SEL_pppp(DisasContext *s, arg_rpr= r_s *a) .fno =3D gen_helper_sve_sel_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; + if (a->s) { return false; - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); } + return do_pppp_flags(s, a, &op); } =20 static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1250,13 +1239,11 @@ static bool trans_ORR_pppp(DisasContext *s, arg_rpr= r_s *a) .fno =3D gen_helper_sve_orr_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else if (a->pg =3D=3D a->rn && a->rn =3D=3D a->rm) { + + if (!a->s && a->pg =3D=3D a->rn && a->rn =3D=3D a->rm) { return do_mov_p(s, a->rd, a->rn); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); } + return do_pppp_flags(s, a, &op); } =20 static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1280,11 +1267,7 @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr= _s *a) .fno =3D gen_helper_sve_orn_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); - } + return do_pppp_flags(s, a, &op); } =20 static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64= pg) @@ -1308,11 +1291,7 @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr= _s *a) .fno =3D gen_helper_sve_nor_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); - } + return do_pppp_flags(s, a, &op); } =20 static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i6= 4 pg) @@ -1336,11 +1315,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rpr= r_s *a) .fno =3D gen_helper_sve_nand_pppp, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - if (a->s) { - return do_pppp_flags(s, a, &op); - } else { - return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); - } + return do_pppp_flags(s, a, &op); } =20 /* --=20 2.20.1