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bh=vMdcVRwhQd9CouGEQ6Nwb6Zou1IpZmtonS7yQKdyIqI=; b=QJYR3jzZwbbXb29OFdocAWMZ9u2Qj8wtUEiPdQbj0k+Gu1ZGZEJcUXAT5pNFiU+BVkCnRg uYDlSXMhYd/An6XbmXACVd/zQ1JXEZuGwiIin+AtnTkRnkTkxpLaphOcFTmXxJ+gsnnMRh ka9107j7NnidypWv1kc2e8go7WC6q2A= X-MC-Unique: PxMRfwl-Oam7upEgykw6Xw-1 From: Eduardo Habkost To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 07/53] aspeed_soc: Rename memmap/irqmap enum constants Date: Thu, 27 Aug 2020 15:20:36 -0400 Message-Id: <20200827192122.658035-8-ehabkost@redhat.com> In-Reply-To: <20200827192122.658035-1-ehabkost@redhat.com> References: <20200827192122.658035-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.81; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 00:53:04 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.959, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Roman Bolshakov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Igor Mammedov , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Some of the enum constant names conflict with the QOM type check macros: ASPEED_GPIO ASPEED_I2C ASPEED_RTC ASPEED_SCU ASPEED_SDHCI ASPEED_SDMC ASPEED_VIC ASPEED_WDT ASPEED_XDMA This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to ASPEED_DEV_*, to avoid conflicts. Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel P. Berrang=C3=A9 Signed-off-by: Eduardo Habkost Tested-By: Roman Bolshakov Message-Id: <20200825192110.3528606-7-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost --- include/hw/arm/aspeed_soc.h | 92 +++++++-------- hw/arm/aspeed.c | 4 +- hw/arm/aspeed_ast2600.c | 208 ++++++++++++++++---------------- hw/arm/aspeed_soc.c | 228 ++++++++++++++++++------------------ 4 files changed, 266 insertions(+), 266 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 914115f3ef..d46f197cbe 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -87,52 +87,52 @@ typedef struct AspeedSoCClass { OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) =20 enum { - ASPEED_IOMEM, - ASPEED_UART1, - ASPEED_UART2, - ASPEED_UART3, - ASPEED_UART4, - ASPEED_UART5, - ASPEED_VUART, - ASPEED_FMC, - ASPEED_SPI1, - ASPEED_SPI2, - ASPEED_EHCI1, - ASPEED_EHCI2, - ASPEED_VIC, - ASPEED_SDMC, - ASPEED_SCU, - ASPEED_ADC, - ASPEED_VIDEO, - ASPEED_SRAM, - ASPEED_SDHCI, - ASPEED_GPIO, - ASPEED_GPIO_1_8V, - ASPEED_RTC, - ASPEED_TIMER1, - ASPEED_TIMER2, - ASPEED_TIMER3, - ASPEED_TIMER4, - ASPEED_TIMER5, - ASPEED_TIMER6, - ASPEED_TIMER7, - ASPEED_TIMER8, - ASPEED_WDT, - ASPEED_PWM, - ASPEED_LPC, - ASPEED_IBT, - ASPEED_I2C, - ASPEED_ETH1, - ASPEED_ETH2, - ASPEED_ETH3, - ASPEED_ETH4, - ASPEED_MII1, - ASPEED_MII2, - ASPEED_MII3, - ASPEED_MII4, - ASPEED_SDRAM, - ASPEED_XDMA, - ASPEED_EMMC, + ASPEED_DEV_IOMEM, + ASPEED_DEV_UART1, + ASPEED_DEV_UART2, + ASPEED_DEV_UART3, + ASPEED_DEV_UART4, + ASPEED_DEV_UART5, + ASPEED_DEV_VUART, + ASPEED_DEV_FMC, + ASPEED_DEV_SPI1, + ASPEED_DEV_SPI2, + ASPEED_DEV_EHCI1, + ASPEED_DEV_EHCI2, + ASPEED_DEV_VIC, + ASPEED_DEV_SDMC, + ASPEED_DEV_SCU, + ASPEED_DEV_ADC, + ASPEED_DEV_VIDEO, + ASPEED_DEV_SRAM, + ASPEED_DEV_SDHCI, + ASPEED_DEV_GPIO, + ASPEED_DEV_GPIO_1_8V, + ASPEED_DEV_RTC, + ASPEED_DEV_TIMER1, + ASPEED_DEV_TIMER2, + ASPEED_DEV_TIMER3, + ASPEED_DEV_TIMER4, + ASPEED_DEV_TIMER5, + ASPEED_DEV_TIMER6, + ASPEED_DEV_TIMER7, + ASPEED_DEV_TIMER8, + ASPEED_DEV_WDT, + ASPEED_DEV_PWM, + ASPEED_DEV_LPC, + ASPEED_DEV_IBT, + ASPEED_DEV_I2C, + ASPEED_DEV_ETH1, + ASPEED_DEV_ETH2, + ASPEED_DEV_ETH3, + ASPEED_DEV_ETH4, + ASPEED_DEV_MII1, + ASPEED_DEV_MII2, + ASPEED_DEV_MII3, + ASPEED_DEV_MII4, + ASPEED_DEV_SDRAM, + ASPEED_DEV_XDMA, + ASPEED_DEV_EMMC, }; =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index fcb1a7cd87..8109cc6d2d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -309,7 +309,7 @@ static void aspeed_machine_init(MachineState *machine) qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 memory_region_add_subregion(get_system_memory(), - sc->memmap[ASPEED_SDRAM], + sc->memmap[ASPEED_DEV_SDRAM], &bmc->ram_container); =20 max_ram_size =3D object_property_get_uint(OBJECT(&bmc->soc), "max-ram-= size", @@ -360,7 +360,7 @@ static void aspeed_machine_init(MachineState *machine) } =20 aspeed_board_binfo.ram_size =3D ram_size; - aspeed_board_binfo.loader_start =3D sc->memmap[ASPEED_SDRAM]; + aspeed_board_binfo.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; aspeed_board_binfo.nb_cpus =3D sc->num_cpus; =20 if (amc->i2c_init) { diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3767f7d8d0..9d95e42143 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -24,43 +24,43 @@ #define ASPEED_SOC_IOMEM_SIZE 0x00200000 =20 static const hwaddr aspeed_soc_ast2600_memmap[] =3D { - [ASPEED_SRAM] =3D 0x10000000, + [ASPEED_DEV_SRAM] =3D 0x10000000, /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ - [ASPEED_IOMEM] =3D 0x1E600000, - [ASPEED_PWM] =3D 0x1E610000, - [ASPEED_FMC] =3D 0x1E620000, - [ASPEED_SPI1] =3D 0x1E630000, - [ASPEED_SPI2] =3D 0x1E641000, - [ASPEED_EHCI1] =3D 0x1E6A1000, - [ASPEED_EHCI2] =3D 0x1E6A3000, - [ASPEED_MII1] =3D 0x1E650000, - [ASPEED_MII2] =3D 0x1E650008, - [ASPEED_MII3] =3D 0x1E650010, - [ASPEED_MII4] =3D 0x1E650018, - [ASPEED_ETH1] =3D 0x1E660000, - [ASPEED_ETH3] =3D 0x1E670000, - [ASPEED_ETH2] =3D 0x1E680000, - [ASPEED_ETH4] =3D 0x1E690000, - [ASPEED_VIC] =3D 0x1E6C0000, - [ASPEED_SDMC] =3D 0x1E6E0000, - [ASPEED_SCU] =3D 0x1E6E2000, - [ASPEED_XDMA] =3D 0x1E6E7000, - [ASPEED_ADC] =3D 0x1E6E9000, - [ASPEED_VIDEO] =3D 0x1E700000, - [ASPEED_SDHCI] =3D 0x1E740000, - [ASPEED_EMMC] =3D 0x1E750000, - [ASPEED_GPIO] =3D 0x1E780000, - [ASPEED_GPIO_1_8V] =3D 0x1E780800, - [ASPEED_RTC] =3D 0x1E781000, - [ASPEED_TIMER1] =3D 0x1E782000, - [ASPEED_WDT] =3D 0x1E785000, - [ASPEED_LPC] =3D 0x1E789000, - [ASPEED_IBT] =3D 0x1E789140, - [ASPEED_I2C] =3D 0x1E78A000, - [ASPEED_UART1] =3D 0x1E783000, - [ASPEED_UART5] =3D 0x1E784000, - [ASPEED_VUART] =3D 0x1E787000, - [ASPEED_SDRAM] =3D 0x80000000, + [ASPEED_DEV_IOMEM] =3D 0x1E600000, + [ASPEED_DEV_PWM] =3D 0x1E610000, + [ASPEED_DEV_FMC] =3D 0x1E620000, + [ASPEED_DEV_SPI1] =3D 0x1E630000, + [ASPEED_DEV_SPI2] =3D 0x1E641000, + [ASPEED_DEV_EHCI1] =3D 0x1E6A1000, + [ASPEED_DEV_EHCI2] =3D 0x1E6A3000, + [ASPEED_DEV_MII1] =3D 0x1E650000, + [ASPEED_DEV_MII2] =3D 0x1E650008, + [ASPEED_DEV_MII3] =3D 0x1E650010, + [ASPEED_DEV_MII4] =3D 0x1E650018, + [ASPEED_DEV_ETH1] =3D 0x1E660000, + [ASPEED_DEV_ETH3] =3D 0x1E670000, + [ASPEED_DEV_ETH2] =3D 0x1E680000, + [ASPEED_DEV_ETH4] =3D 0x1E690000, + [ASPEED_DEV_VIC] =3D 0x1E6C0000, + [ASPEED_DEV_SDMC] =3D 0x1E6E0000, + [ASPEED_DEV_SCU] =3D 0x1E6E2000, + [ASPEED_DEV_XDMA] =3D 0x1E6E7000, + [ASPEED_DEV_ADC] =3D 0x1E6E9000, + [ASPEED_DEV_VIDEO] =3D 0x1E700000, + [ASPEED_DEV_SDHCI] =3D 0x1E740000, + [ASPEED_DEV_EMMC] =3D 0x1E750000, + [ASPEED_DEV_GPIO] =3D 0x1E780000, + [ASPEED_DEV_GPIO_1_8V] =3D 0x1E780800, + [ASPEED_DEV_RTC] =3D 0x1E781000, + [ASPEED_DEV_TIMER1] =3D 0x1E782000, + [ASPEED_DEV_WDT] =3D 0x1E785000, + [ASPEED_DEV_LPC] =3D 0x1E789000, + [ASPEED_DEV_IBT] =3D 0x1E789140, + [ASPEED_DEV_I2C] =3D 0x1E78A000, + [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART5] =3D 0x1E784000, + [ASPEED_DEV_VUART] =3D 0x1E787000, + [ASPEED_DEV_SDRAM] =3D 0x80000000, }; =20 #define ASPEED_A7MPCORE_ADDR 0x40460000 @@ -69,41 +69,41 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2600_irqmap[] =3D { - [ASPEED_UART1] =3D 47, - [ASPEED_UART2] =3D 48, - [ASPEED_UART3] =3D 49, - [ASPEED_UART4] =3D 50, - [ASPEED_UART5] =3D 8, - [ASPEED_VUART] =3D 8, - [ASPEED_FMC] =3D 39, - [ASPEED_SDMC] =3D 0, - [ASPEED_SCU] =3D 12, - [ASPEED_ADC] =3D 78, - [ASPEED_XDMA] =3D 6, - [ASPEED_SDHCI] =3D 43, - [ASPEED_EHCI1] =3D 5, - [ASPEED_EHCI2] =3D 9, - [ASPEED_EMMC] =3D 15, - [ASPEED_GPIO] =3D 40, - [ASPEED_GPIO_1_8V] =3D 11, - [ASPEED_RTC] =3D 13, - [ASPEED_TIMER1] =3D 16, - [ASPEED_TIMER2] =3D 17, - [ASPEED_TIMER3] =3D 18, - [ASPEED_TIMER4] =3D 19, - [ASPEED_TIMER5] =3D 20, - [ASPEED_TIMER6] =3D 21, - [ASPEED_TIMER7] =3D 22, - [ASPEED_TIMER8] =3D 23, - [ASPEED_WDT] =3D 24, - [ASPEED_PWM] =3D 44, - [ASPEED_LPC] =3D 35, - [ASPEED_IBT] =3D 35, /* LPC */ - [ASPEED_I2C] =3D 110, /* 110 -> 125 */ - [ASPEED_ETH1] =3D 2, - [ASPEED_ETH2] =3D 3, - [ASPEED_ETH3] =3D 32, - [ASPEED_ETH4] =3D 33, + [ASPEED_DEV_UART1] =3D 47, + [ASPEED_DEV_UART2] =3D 48, + [ASPEED_DEV_UART3] =3D 49, + [ASPEED_DEV_UART4] =3D 50, + [ASPEED_DEV_UART5] =3D 8, + [ASPEED_DEV_VUART] =3D 8, + [ASPEED_DEV_FMC] =3D 39, + [ASPEED_DEV_SDMC] =3D 0, + [ASPEED_DEV_SCU] =3D 12, + [ASPEED_DEV_ADC] =3D 78, + [ASPEED_DEV_XDMA] =3D 6, + [ASPEED_DEV_SDHCI] =3D 43, + [ASPEED_DEV_EHCI1] =3D 5, + [ASPEED_DEV_EHCI2] =3D 9, + [ASPEED_DEV_EMMC] =3D 15, + [ASPEED_DEV_GPIO] =3D 40, + [ASPEED_DEV_GPIO_1_8V] =3D 11, + [ASPEED_DEV_RTC] =3D 13, + [ASPEED_DEV_TIMER1] =3D 16, + [ASPEED_DEV_TIMER2] =3D 17, + [ASPEED_DEV_TIMER3] =3D 18, + [ASPEED_DEV_TIMER4] =3D 19, + [ASPEED_DEV_TIMER5] =3D 20, + [ASPEED_DEV_TIMER6] =3D 21, + [ASPEED_DEV_TIMER7] =3D 22, + [ASPEED_DEV_TIMER8] =3D 23, + [ASPEED_DEV_WDT] =3D 24, + [ASPEED_DEV_PWM] =3D 44, + [ASPEED_DEV_LPC] =3D 35, + [ASPEED_DEV_IBT] =3D 35, /* LPC */ + [ASPEED_DEV_I2C] =3D 110, /* 110 -> 125 */ + [ASPEED_DEV_ETH1] =3D 2, + [ASPEED_DEV_ETH2] =3D 3, + [ASPEED_DEV_ETH3] =3D 32, + [ASPEED_DEV_ETH4] =3D 33, =20 }; =20 @@ -232,11 +232,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) qemu_irq irq; =20 /* IO space */ - create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOM= EM], ASPEED_SOC_IOMEM_SIZE); =20 /* Video engine stub */ - create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDE= O], 0x1000); =20 /* CPU */ @@ -295,21 +295,21 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) return; } memory_region_add_subregion(get_system_memory(), - sc->memmap[ASPEED_SRAM], &s->sram); + sc->memmap[ASPEED_DEV_SRAM], &s->sram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]= ); =20 /* RTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, - aspeed_soc_get_irq(s, ASPEED_RTC)); + aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), @@ -318,16 +318,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, - sc->memmap[ASPEED_TIMER1]); + sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); + qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { - qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, + qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_DEV_UART5); + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], = 2, uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); } =20 @@ -337,10 +337,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]= ); for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), - sc->irqmap[ASPEED_I2C] + i); + sc->irqmap[ASPEED_DEV_I2C] + i); /* * The AST2600 SoC has one IRQ per I2C bus. Skip the common * IRQ (AST2400 and AST2500) and connect all bussses. @@ -352,17 +352,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_SDRAM], errp)) { + sc->memmap[ASPEED_DEV_SDRAM], errp)) { return; } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]= ); sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_FMC)); + aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); =20 /* SPI */ for (i =3D 0; i < sc->spis_num; i++) { @@ -373,7 +373,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, - sc->memmap[ASPEED_SPI1 + i]); + sc->memmap[ASPEED_DEV_SPI1 + i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, s->spi[i].ctrl->flash_window_base); } @@ -384,16 +384,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, - sc->memmap[ASPEED_EHCI1 + i]); + sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); + aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } =20 /* SDMC - SDRAM Memory Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDM= C]); =20 /* Watch dog */ for (i =3D 0; i < sc->wdts_num; i++) { @@ -405,7 +405,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_WDT] + i * awc->offset); + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); } =20 /* Net */ @@ -416,9 +416,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - sc->memmap[ASPEED_ETH1 + i]); + sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); + aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); =20 object_property_set_link(OBJECT(&s->mii[i]), "nic", OBJECT(&s->ftgmac100[i]), &error_abort); @@ -427,7 +427,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) } =20 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, - sc->memmap[ASPEED_MII1 + i]); + sc->memmap[ASPEED_DEV_MII1 + i]); } =20 /* XDMA */ @@ -435,42 +435,42 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, - sc->memmap[ASPEED_XDMA]); + sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, - aspeed_soc_get_irq(s, ASPEED_XDMA)); + aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPI= O]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_GPIO)); + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, - sc->memmap[ASPEED_GPIO_1_8V]); + sc->memmap[ASPEED_DEV_GPIO_1_8V]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, - aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); =20 /* SDHCI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, - sc->memmap[ASPEED_SDHCI]); + sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_SDHCI)); + aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); =20 /* eMMC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMM= C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, - aspeed_soc_get_irq(s, ASPEED_EMMC)); + aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); } =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index a1a8684216..35be126db6 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -27,97 +27,97 @@ #define ASPEED_SOC_IOMEM_SIZE 0x00200000 =20 static const hwaddr aspeed_soc_ast2400_memmap[] =3D { - [ASPEED_IOMEM] =3D 0x1E600000, - [ASPEED_FMC] =3D 0x1E620000, - [ASPEED_SPI1] =3D 0x1E630000, - [ASPEED_EHCI1] =3D 0x1E6A1000, - [ASPEED_VIC] =3D 0x1E6C0000, - [ASPEED_SDMC] =3D 0x1E6E0000, - [ASPEED_SCU] =3D 0x1E6E2000, - [ASPEED_XDMA] =3D 0x1E6E7000, - [ASPEED_VIDEO] =3D 0x1E700000, - [ASPEED_ADC] =3D 0x1E6E9000, - [ASPEED_SRAM] =3D 0x1E720000, - [ASPEED_SDHCI] =3D 0x1E740000, - [ASPEED_GPIO] =3D 0x1E780000, - [ASPEED_RTC] =3D 0x1E781000, - [ASPEED_TIMER1] =3D 0x1E782000, - [ASPEED_WDT] =3D 0x1E785000, - [ASPEED_PWM] =3D 0x1E786000, - [ASPEED_LPC] =3D 0x1E789000, - [ASPEED_IBT] =3D 0x1E789140, - [ASPEED_I2C] =3D 0x1E78A000, - [ASPEED_ETH1] =3D 0x1E660000, - [ASPEED_ETH2] =3D 0x1E680000, - [ASPEED_UART1] =3D 0x1E783000, - [ASPEED_UART5] =3D 0x1E784000, - [ASPEED_VUART] =3D 0x1E787000, - [ASPEED_SDRAM] =3D 0x40000000, + [ASPEED_DEV_IOMEM] =3D 0x1E600000, + [ASPEED_DEV_FMC] =3D 0x1E620000, + [ASPEED_DEV_SPI1] =3D 0x1E630000, + [ASPEED_DEV_EHCI1] =3D 0x1E6A1000, + [ASPEED_DEV_VIC] =3D 0x1E6C0000, + [ASPEED_DEV_SDMC] =3D 0x1E6E0000, + [ASPEED_DEV_SCU] =3D 0x1E6E2000, + [ASPEED_DEV_XDMA] =3D 0x1E6E7000, + [ASPEED_DEV_VIDEO] =3D 0x1E700000, + [ASPEED_DEV_ADC] =3D 0x1E6E9000, + [ASPEED_DEV_SRAM] =3D 0x1E720000, + [ASPEED_DEV_SDHCI] =3D 0x1E740000, + [ASPEED_DEV_GPIO] =3D 0x1E780000, + [ASPEED_DEV_RTC] =3D 0x1E781000, + [ASPEED_DEV_TIMER1] =3D 0x1E782000, + [ASPEED_DEV_WDT] =3D 0x1E785000, + [ASPEED_DEV_PWM] =3D 0x1E786000, + [ASPEED_DEV_LPC] =3D 0x1E789000, + [ASPEED_DEV_IBT] =3D 0x1E789140, + [ASPEED_DEV_I2C] =3D 0x1E78A000, + [ASPEED_DEV_ETH1] =3D 0x1E660000, + [ASPEED_DEV_ETH2] =3D 0x1E680000, + [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART5] =3D 0x1E784000, + [ASPEED_DEV_VUART] =3D 0x1E787000, + [ASPEED_DEV_SDRAM] =3D 0x40000000, }; =20 static const hwaddr aspeed_soc_ast2500_memmap[] =3D { - [ASPEED_IOMEM] =3D 0x1E600000, - [ASPEED_FMC] =3D 0x1E620000, - [ASPEED_SPI1] =3D 0x1E630000, - [ASPEED_SPI2] =3D 0x1E631000, - [ASPEED_EHCI1] =3D 0x1E6A1000, - [ASPEED_EHCI2] =3D 0x1E6A3000, - [ASPEED_VIC] =3D 0x1E6C0000, - [ASPEED_SDMC] =3D 0x1E6E0000, - [ASPEED_SCU] =3D 0x1E6E2000, - [ASPEED_XDMA] =3D 0x1E6E7000, - [ASPEED_ADC] =3D 0x1E6E9000, - [ASPEED_VIDEO] =3D 0x1E700000, - [ASPEED_SRAM] =3D 0x1E720000, - [ASPEED_SDHCI] =3D 0x1E740000, - [ASPEED_GPIO] =3D 0x1E780000, - [ASPEED_RTC] =3D 0x1E781000, - [ASPEED_TIMER1] =3D 0x1E782000, - [ASPEED_WDT] =3D 0x1E785000, - [ASPEED_PWM] =3D 0x1E786000, - [ASPEED_LPC] =3D 0x1E789000, - [ASPEED_IBT] =3D 0x1E789140, - [ASPEED_I2C] =3D 0x1E78A000, - [ASPEED_ETH1] =3D 0x1E660000, - [ASPEED_ETH2] =3D 0x1E680000, - [ASPEED_UART1] =3D 0x1E783000, - [ASPEED_UART5] =3D 0x1E784000, - [ASPEED_VUART] =3D 0x1E787000, - [ASPEED_SDRAM] =3D 0x80000000, + [ASPEED_DEV_IOMEM] =3D 0x1E600000, + [ASPEED_DEV_FMC] =3D 0x1E620000, + [ASPEED_DEV_SPI1] =3D 0x1E630000, + [ASPEED_DEV_SPI2] =3D 0x1E631000, + [ASPEED_DEV_EHCI1] =3D 0x1E6A1000, + [ASPEED_DEV_EHCI2] =3D 0x1E6A3000, + [ASPEED_DEV_VIC] =3D 0x1E6C0000, + [ASPEED_DEV_SDMC] =3D 0x1E6E0000, + [ASPEED_DEV_SCU] =3D 0x1E6E2000, + [ASPEED_DEV_XDMA] =3D 0x1E6E7000, + [ASPEED_DEV_ADC] =3D 0x1E6E9000, + [ASPEED_DEV_VIDEO] =3D 0x1E700000, + [ASPEED_DEV_SRAM] =3D 0x1E720000, + [ASPEED_DEV_SDHCI] =3D 0x1E740000, + [ASPEED_DEV_GPIO] =3D 0x1E780000, + [ASPEED_DEV_RTC] =3D 0x1E781000, + [ASPEED_DEV_TIMER1] =3D 0x1E782000, + [ASPEED_DEV_WDT] =3D 0x1E785000, + [ASPEED_DEV_PWM] =3D 0x1E786000, + [ASPEED_DEV_LPC] =3D 0x1E789000, + [ASPEED_DEV_IBT] =3D 0x1E789140, + [ASPEED_DEV_I2C] =3D 0x1E78A000, + [ASPEED_DEV_ETH1] =3D 0x1E660000, + [ASPEED_DEV_ETH2] =3D 0x1E680000, + [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART5] =3D 0x1E784000, + [ASPEED_DEV_VUART] =3D 0x1E787000, + [ASPEED_DEV_SDRAM] =3D 0x80000000, }; =20 static const int aspeed_soc_ast2400_irqmap[] =3D { - [ASPEED_UART1] =3D 9, - [ASPEED_UART2] =3D 32, - [ASPEED_UART3] =3D 33, - [ASPEED_UART4] =3D 34, - [ASPEED_UART5] =3D 10, - [ASPEED_VUART] =3D 8, - [ASPEED_FMC] =3D 19, - [ASPEED_EHCI1] =3D 5, - [ASPEED_EHCI2] =3D 13, - [ASPEED_SDMC] =3D 0, - [ASPEED_SCU] =3D 21, - [ASPEED_ADC] =3D 31, - [ASPEED_GPIO] =3D 20, - [ASPEED_RTC] =3D 22, - [ASPEED_TIMER1] =3D 16, - [ASPEED_TIMER2] =3D 17, - [ASPEED_TIMER3] =3D 18, - [ASPEED_TIMER4] =3D 35, - [ASPEED_TIMER5] =3D 36, - [ASPEED_TIMER6] =3D 37, - [ASPEED_TIMER7] =3D 38, - [ASPEED_TIMER8] =3D 39, - [ASPEED_WDT] =3D 27, - [ASPEED_PWM] =3D 28, - [ASPEED_LPC] =3D 8, - [ASPEED_IBT] =3D 8, /* LPC */ - [ASPEED_I2C] =3D 12, - [ASPEED_ETH1] =3D 2, - [ASPEED_ETH2] =3D 3, - [ASPEED_XDMA] =3D 6, - [ASPEED_SDHCI] =3D 26, + [ASPEED_DEV_UART1] =3D 9, + [ASPEED_DEV_UART2] =3D 32, + [ASPEED_DEV_UART3] =3D 33, + [ASPEED_DEV_UART4] =3D 34, + [ASPEED_DEV_UART5] =3D 10, + [ASPEED_DEV_VUART] =3D 8, + [ASPEED_DEV_FMC] =3D 19, + [ASPEED_DEV_EHCI1] =3D 5, + [ASPEED_DEV_EHCI2] =3D 13, + [ASPEED_DEV_SDMC] =3D 0, + [ASPEED_DEV_SCU] =3D 21, + [ASPEED_DEV_ADC] =3D 31, + [ASPEED_DEV_GPIO] =3D 20, + [ASPEED_DEV_RTC] =3D 22, + [ASPEED_DEV_TIMER1] =3D 16, + [ASPEED_DEV_TIMER2] =3D 17, + [ASPEED_DEV_TIMER3] =3D 18, + [ASPEED_DEV_TIMER4] =3D 35, + [ASPEED_DEV_TIMER5] =3D 36, + [ASPEED_DEV_TIMER6] =3D 37, + [ASPEED_DEV_TIMER7] =3D 38, + [ASPEED_DEV_TIMER8] =3D 39, + [ASPEED_DEV_WDT] =3D 27, + [ASPEED_DEV_PWM] =3D 28, + [ASPEED_DEV_LPC] =3D 8, + [ASPEED_DEV_IBT] =3D 8, /* LPC */ + [ASPEED_DEV_I2C] =3D 12, + [ASPEED_DEV_ETH1] =3D 2, + [ASPEED_DEV_ETH2] =3D 3, + [ASPEED_DEV_XDMA] =3D 6, + [ASPEED_DEV_SDHCI] =3D 26, }; =20 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap @@ -221,11 +221,11 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) Error *err =3D NULL; =20 /* IO space */ - create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOM= EM], ASPEED_SOC_IOMEM_SIZE); =20 /* Video engine stub */ - create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDE= O], 0x1000); =20 /* CPU */ @@ -243,19 +243,19 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } memory_region_add_subregion(get_system_memory(), - sc->memmap[ASPEED_SRAM], &s->sram); + sc->memmap[ASPEED_DEV_SRAM], &s->sram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]= ); =20 /* VIC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, @@ -265,9 +265,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, - aspeed_soc_get_irq(s, ASPEED_RTC)); + aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), @@ -276,16 +276,16 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, - sc->memmap[ASPEED_TIMER1]); + sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); + qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 /* UART - attach an 8250 to the IO space as our UART5 */ if (serial_hd(0)) { - qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, + qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_DEV_UART5); + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], = 2, uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); } =20 @@ -295,25 +295,25 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]= ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, - aspeed_soc_get_irq(s, ASPEED_I2C)); + aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); =20 /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_SDRAM], errp)) { + sc->memmap[ASPEED_DEV_SDRAM], errp)) { return; } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]= ); sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, s->fmc.ctrl->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_FMC)); + aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); =20 /* SPI */ for (i =3D 0; i < sc->spis_num; i++) { @@ -322,7 +322,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, - sc->memmap[ASPEED_SPI1 + i]); + sc->memmap[ASPEED_DEV_SPI1 + i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, s->spi[i].ctrl->flash_window_base); } @@ -333,16 +333,16 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, - sc->memmap[ASPEED_EHCI1 + i]); + sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); + aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } =20 /* SDMC - SDRAM Memory Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDM= C]); =20 /* Watch dog */ for (i =3D 0; i < sc->wdts_num; i++) { @@ -354,7 +354,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_WDT] + i * awc->offset); + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); } =20 /* Net */ @@ -365,9 +365,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - sc->memmap[ASPEED_ETH1 + i]); + sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); + aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); } =20 /* XDMA */ @@ -375,26 +375,26 @@ static void aspeed_soc_realize(DeviceState *dev, Erro= r **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, - sc->memmap[ASPEED_XDMA]); + sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, - aspeed_soc_get_irq(s, ASPEED_XDMA)); + aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPI= O]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_GPIO)); + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); =20 /* SDHCI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, - sc->memmap[ASPEED_SDHCI]); + sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_SDHCI)); + aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); } static Property aspeed_soc_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, --=20 2.26.2