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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=f+bq5+bU5qJZgyq6pOlmgaDGL5Bj/lO10h+Sr2HJifNlLqLIWRY9WJoKPpTL3Or1Dd 94Xv0tcLB6XirpqoJQrx6kSoanptlvxfTsnxnn4lhRVHDM5fdUV8F5LAtN1JKGTdq3KY cJuLSB4Gn71/78StJpBkItgyAOW5+nNAfPUruv3O6nc2iIM6rX17zkbdLKbUqPfqzhwP +Foi8/KrXKlXoZMduPrPlDeXZnFAuusKSwt3OgKi8ampV61e9kQ7E2+Z47fT6knYfIDL R2mgcWmjFATe1rYSIb0MtQnXBItu3NcvyFFZRTjXTf+8ZofAoCkO4+6UDAtgqT0Xg9ag ERyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=kLxCq+wcZwVmndRKi8m5qRQx4qfSrDLtgQDX3I8dXdyOPKiN6ZGghMN3iRx0gadCiD gL61HrQCBdOin13RYcZMcIygKXTG9aocQsbjmHYCEb2Dq5A///dFT4wlfLQgPQLP9vEk 80EdfBvZ0WhN/xP3wa+BS2RsJcO9cIWBR68tVaYSsIqBN6nRYQs9F5ofxeu93m8qZdp8 iRqi88qp0s+fBoe8rRsKpkwmZcISqtZgt2l3eMOsuQ0jlKKn4t+rQKLO3Ui9i2M7D/cZ zkUd0/qQtI5WvlktjmUjXouxLkfOMGvq7Am3nKwghExDajPqRyvblVOk2m38u4gURQKH TPrw== X-Gm-Message-State: AOAM530PkoQTT0hW5FRVTrL4dnYUGoimHlupIoqc1qI3YqxKlX6WdXf3 0dTMsUzmmjYr5YHJJeL2glNnVMyUw2stxQ== X-Google-Smtp-Source: ABdhPJyYv56oX0DI78meVCbnQ61kaz52TP0P4a9oOcchr444/VGgffcjZGqmGQsAeEXB+O7WatvUoA== X-Received: by 2002:a17:902:8504:: with SMTP id bj4mr8926772plb.231.1598389276759; Tue, 25 Aug 2020 14:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 64/77] target/microblaze: Convert mbar to decodetree Date: Tue, 25 Aug 2020 13:59:37 -0700 Message-Id: <20200825205950.730499-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split this out of the normal branch instructions, as it requires special handling. End the TB only for an instruction barrier. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 81 ++++++++++++++++++---------------- 2 files changed, 45 insertions(+), 38 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 53da2b75aa..77b073be9e 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -124,6 +124,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 = @typea lwx 110010 ..... ..... ..... 1000 000 0000 @typea lwi 111010 ..... ..... ................ @typeb =20 +mbar 101110 imm:5 00010 0000 0000 0000 0100 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fc1c661368..a391e80fb9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1166,6 +1166,48 @@ static bool trans_brki(DisasContext *dc, arg_typeb_b= r *arg) return true; } =20 +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) +{ + int mbar_imm =3D arg->imm; + + /* + * Instruction access memory barrier. + * End the TB so that we recognize self-modified code immediately. + */ + if (mbar_imm & 1) { + dc->cpustate_changed =3D 1; + } + + /* Data access memory barrier. */ + if (mbar_imm & 2) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + + /* Sleep. */ + if (mbar_imm & 16) { + TCGv_i32 tmp_1; + + if (trap_userspace(dc, true)) { + /* Sleep is a privileged instruction. */ + return true; + } + + t_sync_flags(dc); + + tmp_1 =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp_1, cpu_env, + -offsetof(MicroBlazeCPU, env) + +offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + + gen_raise_exception(dc, EXCP_HLT); + } + return true; +} + + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1447,50 +1489,13 @@ static void dec_bcc(DisasContext *dc) =20 static void dec_br(DisasContext *dc) { - unsigned int dslot, link, abs, mbar; + unsigned int dslot, link, abs; uint32_t add_pc; =20 dslot =3D dc->ir & (1 << 20); abs =3D dc->ir & (1 << 19); link =3D dc->ir & (1 << 18); =20 - /* Memory barrier. */ - mbar =3D (dc->ir >> 16) & 31; - if (mbar =3D=3D 2 && dc->imm =3D=3D 4) { - uint16_t mbar_imm =3D dc->rd; - - /* Data access memory barrier. */ - if ((mbar_imm & 2) =3D=3D 0) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - } - - /* mbar IMM & 16 decodes to sleep. */ - if (mbar_imm & 16) { - TCGv_i32 tmp_1; - - if (trap_userspace(dc, true)) { - /* Sleep is a privileged instruction. */ - return; - } - - t_sync_flags(dc); - - tmp_1 =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp_1, cpu_env, - -offsetof(MicroBlazeCPU, env) - +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - - gen_raise_exception(dc, EXCP_HLT); - return; - } - /* Break the TB. */ - dc->cpustate_changed =3D 1; - return; - } - if (dslot && dec_setup_dslot(dc)) { return; } --=20 2.25.1