From nobody Tue Feb 10 13:34:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390544; cv=none; d=zohomail.com; s=zohoarc; b=YmJo+DP1ks/cRQ6lvTGoklKGNHk7UNbnKH+QAf2eQ+/rq3XzXBTkjkpP6OJ8u4UhcPP/5VtNSlVrcxT4kNYcQJuiJm+6sDHUmyeS1BSl8Aq+YqjHvkzlxXt8Y+lkxSd6Gc/PV66WT1uQkcn9tG1tAaGVqrUwbzsMZsZlKUxZ+rQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390544; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M605GjYj/TsAqS9LhAzYjh6MlBkWbkHJca8j+nbMmp4=; b=nKmDMpX5l2UqT1XquJrNnCnUzxos6tUlL5CtrneutVzmNtryxZ2/4ihu8XUBhWGaZWkgMBwnDr3/BBDTh/JjMZtoO3KYtD8CJvpYaKTqU9JV4J3bMPGtpyoyjfXeZvZf96iD7p9uv16U9aPlf36Hj5kG77scoJ8K8cJtuAfPlVU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390544218604.4916091778232; Tue, 25 Aug 2020 14:22:24 -0700 (PDT) Received: from localhost ([::1]:43524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgOc-0000v2-Sq for importer@patchew.org; Tue, 25 Aug 2020 17:22:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3Z-0007na-Al for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:37 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3U-0001pl-KF for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:36 -0400 Received: by mail-pg1-x541.google.com with SMTP id v15so7668439pgh.6 for ; Tue, 25 Aug 2020 14:00:31 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M605GjYj/TsAqS9LhAzYjh6MlBkWbkHJca8j+nbMmp4=; b=jcvqyZnThZ/3ASU91duPjcaQ7BdUAPmcwiKJovm/prHu5wf2MepgTAbmV6egLNARHE 8t29ZrUtBnhTNE4tdanV1o+IkBO55oPTUERBp/j1CjiPdiYzsNreLUH8UiMPKkQHyRh2 lSpyTxhdVA6fwVYS+SvrL5RY6h62/l9UzcLxO6FhOlcZkZEa1iNPCEsIzP94LD+mbu3i u8UEy5pKY8j4MaBfi64Hdzu14yBu6iHxGTQYa8lW5iWzG7PJVN0EguWNqrGDAOe8Vgv9 b6zw2UzodXn2BdanjCBOBSo97P7B6A8kzj7+BUbBf0mlpW5wWYPTShwjF01SpxdR3tEb d+LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M605GjYj/TsAqS9LhAzYjh6MlBkWbkHJca8j+nbMmp4=; b=a75wgPiUfXzi+2SpCDkVRcI3aBHuX+Yr+MjCXUw0JqJAoeWPuB1jnMnTv52A+wU9+F +Em/d+rzWM6RQfoLHRatlWnmK4Qgp9i8iBlIQ3YoN5I7TVTFhtrTDgjm4a0a+9LKiVYF NtLUeTp9zlW9MmfstD0CevzcyN4ayTQI1HqD1eheTvKCG1LEEx6lGYIxlXHDdcXithSJ MKupOeUQ2Z+xUTMmxLD+wJJapjIE0CUx0PEbOoZOIjHwIrb+Af/frySUhVMEEiBIzvIW Tl5q0XmvytUUabMeBujt6R/Ojr1YPGAVGomsF1RPhFmWuneKE08F43G8eY84zQvsG5Qw fo5Q== X-Gm-Message-State: AOAM5326DKWgyNS7Gre7yzfWj4T7p+LRh3k/1KFoCtgT38sinqiSB7BF enRkJAHcxp1doJziotBZ2fVQp0KWVhlCdA== X-Google-Smtp-Source: ABdhPJw/Moh5vxoSlhVdWC1DXqJPoH5MIWmlkNClwi8E39OayFE4i966A7kwPz+T6CMC8FgYVRMjnw== X-Received: by 2002:aa7:9552:: with SMTP id w18mr9374849pfq.150.1598389229530; Tue, 25 Aug 2020 14:00:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/77] target/microblaze: Convert to translator_loop Date: Tue, 25 Aug 2020 13:59:02 -0700 Message-Id: <20200825205950.730499-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Part two of conversion to the generic translator_loop. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++++++++++++++++++---------------- 1 file changed, 149 insertions(+), 140 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 45b1555f85..6a9710d76d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint3= 2_t ir) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { - CPUMBState *env =3D cs->env_ptr; - MicroBlazeCPU *cpu =3D env_archcpu(env); - uint32_t pc_start; - struct DisasContext ctx; - struct DisasContext *dc =3D &ctx; - uint32_t page_start, org_flags; - uint32_t npc; - int num_insns; + DisasContext *dc =3D container_of(dcb, DisasContext, base); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + int bound; =20 - pc_start =3D tb->pc; dc->cpu =3D cpu; - org_flags =3D dc->synced_flags =3D dc->tb_flags =3D tb->flags; - - dc->jmp =3D 0; + dc->synced_flags =3D dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); - if (dc->delayed_branch) { - dc->jmp =3D JMP_INDIRECT; - } - dc->base.pc_first =3D pc_start; - dc->base.pc_next =3D pc_start; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.tb =3D tb; =20 - if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", pc_start); + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); +} + +static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) +{ +} + +static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) +{ + tcg_gen_insn_start(dcb->pc_next); +} + +static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + gen_raise_exception_sync(dc, EXCP_DEBUG); + + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + dc->base.pc_next +=3D 4; + return true; +} + +static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + CPUMBState *env =3D cs->env_ptr; + + /* TODO: This should raise an exception, not terminate qemu. */ + if (dc->base.pc_next & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", + (uint32_t)dc->base.pc_next); } =20 - page_start =3D pc_start & TARGET_PAGE_MASK; - num_insns =3D 0; + dc->clear_imm =3D 1; + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + if (dc->clear_imm) { + dc->tb_flags &=3D ~IMM_FLAG; + } + dc->base.pc_next +=3D 4; =20 - gen_tb_start(tb); - do - { - tcg_gen_insn_start(dc->base.pc_next); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - gen_raise_exception_sync(dc, EXCP_DEBUG); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - break; + if (dc->delayed_branch && --dc->delayed_branch =3D=3D 0) { + if (dc->tb_flags & DRTI_FLAG) { + do_rti(dc); } - - /* Pretty disas. */ - LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); - - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); + if (dc->tb_flags & DRTB_FLAG) { + do_rtb(dc); } - - dc->clear_imm =3D 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) - dc->tb_flags &=3D ~IMM_FLAG; - dc->base.pc_next +=3D 4; - - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - if (dc->tb_flags & DRTI_FLAG) - do_rti(dc); - if (dc->tb_flags & DRTB_FLAG) - do_rtb(dc); - if (dc->tb_flags & DRTE_FLAG) - do_rte(dc); - /* Clear the delay slot flag. */ - dc->tb_flags &=3D ~D_FLAG; - /* If it is a direct jump, try direct chaining. */ - if (dc->jmp =3D=3D JMP_INDIRECT) { - TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); - dc->base.is_jmp =3D DISAS_JUMP; - } else if (dc->jmp =3D=3D JMP_DIRECT) { - t_sync_flags(dc); - gen_goto_tb(dc, 0, dc->jmp_pc); - } else if (dc->jmp =3D=3D JMP_DIRECT_CC) { - TCGLabel *l1 =3D gen_new_label(); - t_sync_flags(dc); - /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); - gen_goto_tb(dc, 0, dc->jmp_pc); - } - break; - } + if (dc->tb_flags & DRTE_FLAG) { + do_rte(dc); } - if (dc->base.singlestep_enabled) { - break; - } - } while (!dc->base.is_jmp && !dc->cpustate_changed - && !tcg_op_buf_full() - && !singlestep - && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) - && num_insns < max_insns); - - npc =3D dc->base.pc_next; - if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { - if (dc->tb_flags & D_FLAG) { - dc->base.is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); - sync_jmpstate(dc); - } else - npc =3D dc->jmp_pc; + /* Clear the delay slot flag. */ + dc->tb_flags &=3D ~D_FLAG; + dc->base.is_jmp =3D DISAS_JUMP; } =20 - /* Force an update if the per-tb cpu state has changed. */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT - && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { + /* Force an exit if the per-tb cpu state has changed. */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { dc->base.is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } - t_sync_flags(dc); +} + +static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + assert(!dc->abort_at_next_insn); =20 if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - /* nothing more to generate */ - } else if (unlikely(cs->singlestep_enabled)) { - TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); - - if (dc->base.is_jmp !=3D DISAS_JUMP) { - tcg_gen_movi_i32(cpu_pc, npc); - } - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - gen_goto_tb(dc, 1, npc); - break; - case DISAS_JUMP: - case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ - tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); - } + /* We have already exited the TB. */ + return; } - gen_tb_end(tb, num_insns); =20 - tb->size =3D dc->base.pc_next - pc_start; - tb->icount =3D num_insns; + t_sync_flags(dc); + if (dc->tb_flags & D_FLAG) { + sync_jmpstate(dc); + dc->jmp =3D JMP_NOJMP; + } =20 + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + assert(dc->jmp =3D=3D JMP_NOJMP); + gen_goto_tb(dc, 0, dc->base.pc_next); + return; + + case DISAS_UPDATE: + assert(dc->jmp =3D=3D JMP_NOJMP); + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; + + case DISAS_JUMP: + switch (dc->jmp) { + case JMP_INDIRECT: + { + TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + } + return; + + case JMP_DIRECT_CC: + { + TCGLabel *l1 =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + gen_goto_tb(dc, 1, dc->base.pc_next); + gen_set_label(l1); + } + /* fall through */ + + case JMP_DIRECT: + gen_goto_tb(dc, 0, dc->jmp_pc); + return; + } + /* fall through */ + + default: + g_assert_not_reached(); + } +} + +static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) +{ #ifdef DEBUG_DISAS #if !SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - FILE *logfile =3D qemu_log_lock(); - qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); - qemu_log_unlock(logfile); - } + qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); + log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif #endif - assert(!dc->abort_at_next_insn); +} + +static const TranslatorOps mb_tr_ops =3D { + .init_disas_context =3D mb_tr_init_disas_context, + .tb_start =3D mb_tr_tb_start, + .insn_start =3D mb_tr_insn_start, + .breakpoint_check =3D mb_tr_breakpoint_check, + .translate_insn =3D mb_tr_translate_insn, + .tb_stop =3D mb_tr_tb_stop, + .disas_log =3D mb_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) +{ + DisasContext dc; + translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.25.1