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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2WmsQs1dYriEEFTKVUq6JHveLUFEQ0EEc9cZlXDrRq8=; b=AZrtnXIvt95MnL+SGFF2mFyi7y/3QiSRmo7M5RREpvC7eM1q+MnG96rBCssXY2ArTa 9rMn/xKOe2em9aRbmtGIwoXM/62SqYqsGlvqeEVQzYBAd3q9iHU3mn27uFZNrN1ZW+mU /v+09EbKs/YrXdpQLHeLbvUWfC0U58Sv/zg9rt6Nq9bkIw/QMPGoLZ74yyGXHBlSHfqW pC2C/oIHomGidzl8iiGKFg72NiwZBnWlq+3I6nyH60cWQ25UFqgMspYcEWgEt1XUVXkz 6zoGiQOiVDPjLlVQMSudp8R9lylP3zVbjZFmNEbVSYXa2IcSNSNyTkLYHPEQLtN+PkYP wtuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2WmsQs1dYriEEFTKVUq6JHveLUFEQ0EEc9cZlXDrRq8=; b=r6S2oo6Z1FUUbd8RTePQ+4OdsuxlfhH4fcTn9bGTzej8V6vuczaKhuzfyIv/KIT3G3 JQNxwbbLNI6cBj5x0Kqj/tPAcM/1H5m5fcpsORIoSa241PprvtvqCcRleqAKOmElHeWq DhXBu+0h50GBoxYkXcQt8nn4W9HFNg40+DHNserGjZvXSexJqqy6lbPnVAZf5EozlIDs 0yczwjRXe/ZURIUL8VcVcyJatGOytog/okSmzE5CyMjjgXxVdcnS9n50EHbzE+Is6YS2 w0YVwBf6YYn7qVfG7wzwleNcTUOEJoqXbx1FtBEn4gHVXYnu/hIDtoWrXtkhZg7pPg3I RJ5Q== X-Gm-Message-State: AOAM532Fy703yzT9zdkzJMQsOfHKqbHlarxiLwI+PsJEfq+nu4/8sPqw qiy54iffbBo1BOXFnAvXirvqYge97MMFoA== X-Google-Smtp-Source: ABdhPJxGs5OSlHnoKPCPMNrEFiw0lYhVJwxs3ZQEeAbqp7Q42/W41X9bmQsl8vM8zgM3118cD0vSeQ== X-Received: by 2002:a17:90a:de10:: with SMTP id m16mr3095422pjv.34.1598389193949; Tue, 25 Aug 2020 13:59:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/77] tests/tcg: Add microblaze to arches filter Date: Tue, 25 Aug 2020 13:58:34 -0700 Message-Id: <20200825205950.730499-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. 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Iglesias --- tests/tcg/configure.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 7d714f902a..598a50cd4f 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -94,7 +94,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=3Dxtensa ;; - alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv6= 4|s390x|sh4|sparc64) arches=3D$target ;; *) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389568; cv=none; d=zohomail.com; s=zohoarc; b=nTKpQ5aPep+kZyHmNeEdRtcpfCmgwGwEr9V4eEpZ1cIpEc8E6Z82WpMFjCbSBwT3vb6L+tBAT8DQYxsZ8DmxEyA0hnmWw7ETlByaBOZQ/C46U3Dj9w3WUtpa4Iycws84bTUXmbuthPP7cPzYfbTuudituZsVmhSakAEJp/JDEOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389568; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VbBY1yItMeIkPbGFrNMfYpfJv2H3xsn/XCS3gcTz2VE=; b=L9dAvnMEXD5q7IOvJP9WviENEMG/AoNNB+UxSNFkEUP45U08S+MzXj5msj81PX2IEmDpgsTQlc53G9FQeoLF+VaGeQx8tEgdYWBKq5B5I8OxmeM2QMFSvLnE6ZTbSSdStQaSYaGsYsv33OBAxYpdIfsX6WzskHOXrExcG8TqcBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389568114619.1068743196821; Tue, 25 Aug 2020 14:06:08 -0700 (PDT) Received: from localhost ([::1]:33178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg8s-00078U-Nh for importer@patchew.org; Tue, 25 Aug 2020 17:06:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg2w-0006rJ-NH for qemu-devel@nongnu.org; Tue, 25 Aug 2020 16:59:58 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:38466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg2v-0001c0-3I for qemu-devel@nongnu.org; Tue, 25 Aug 2020 16:59:58 -0400 Received: by mail-pj1-x1042.google.com with SMTP id ls14so121208pjb.3 for ; Tue, 25 Aug 2020 13:59:56 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VbBY1yItMeIkPbGFrNMfYpfJv2H3xsn/XCS3gcTz2VE=; b=N78+NB1PhP9V0tYk48fl7Mg3+sokZAFY8wivDWgDC0Lrz1vXqrVdV+5r0Eyp3ry37G SUTlqfcwpFC8HmWej7OlcuImek2vapqA5GvnlK6d0a5IodAlRLmTjJrj8QaCDvlvLK21 dSQESHTmhh3qXbxhoKPjTouLSXaHOaB1Dy9IVBDuonx7qd54O0TuXoD7rLmv+G5jYlqe aTDHciyYkSLAV1dVXcksYxO5xvqSM2Po5/Wtr7rGSFlpvhVKDZ9vMiinOHxJZDT0hlzc ZEQBhBTRHouvg6M9oht0GuB3c7E81CLu49MXEv+6ZdT+ugnEmer0YN6u5/se2WR7dkTf LsWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VbBY1yItMeIkPbGFrNMfYpfJv2H3xsn/XCS3gcTz2VE=; b=NL0IoVR2uTkvHvUUQd+F8m140VTgyWpfW48tAFfuZoJutO9aVLhDQbmKDw2QF+cntR lSRpDCzL63P5XKeXHPTmZhCFFJQ53pxP1X5v606T6mV4/Bb/yaCxj3ahORCJqjEkeaqm gPDfM/T95jeTEp0lVrIwgg4m40Q26UpK/E6VAh8fLxlXWnCrKhYCKEqiNZSw5cSWY3uP CJ59MC/D5vSFDSCcSGODiQnc1UrAx++7QJdEzCUcGnTh/Nk6y686Bmr2J7hf9+j6D63K t9M/jKa4ga74JGruzwWS9wL9eqmuuMGuzvuHDWLWbTlMkH4oGSiBbrl9tS71oeLRkG6m wYOA== X-Gm-Message-State: AOAM530kZaqMQ3MQmB2CGFSzlrTjq91y+9iqxwny5E4Vo3eGFP23GTEh 5LH+iD4iuDb+/l9mZQ3TQZvAleqdJQbSpA== X-Google-Smtp-Source: ABdhPJxVPpjcOiCGG9a4G4SfB4CX3Kj4946E+Lw1aEp+hto46yePuvQPiJXW6HP2Diw/rUFOHKJ5gg== X-Received: by 2002:a17:90a:d510:: with SMTP id t16mr3290035pju.210.1598389195444; Tue, 25 Aug 2020 13:59:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO Date: Tue, 25 Aug 2020 13:58:35 -0700 Message-Id: <20200825205950.730499-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is optional in ISO C, and not all cpus provide it. Cc: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- tests/tcg/multiarch/float_convs.c | 2 ++ tests/tcg/multiarch/float_madds.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_= convs.c index 47e24b8b16..e9be75c2d5 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -30,7 +30,9 @@ float_mapping round_flags[] =3D { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; =20 static void print_input(float input) diff --git a/tests/tcg/multiarch/float_madds.c b/tests/tcg/multiarch/float_= madds.c index eceb4ae38b..e422608ccd 100644 --- a/tests/tcg/multiarch/float_madds.c +++ b/tests/tcg/multiarch/float_madds.c @@ -29,7 +29,9 @@ float_mapping round_flags[] =3D { #ifdef FE_DOWNWARD { FE_DOWNWARD, "downwards" }, #endif +#ifdef FE_TOWARDZERO { FE_TOWARDZERO, "to zero" } +#endif }; =20 =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389318; cv=none; d=zohomail.com; s=zohoarc; b=ZKluedTTpp51xLgh/5h6rizcWznlORfmQq1eP5Dk4cen0Z2tXmcfVKeFjrSHSr+nE9GmlFzsY/aXGo8LwTRSnyr6l8hBYR8GLi9bBPTLEy+kzpueZ37oA/mV8bzvP5a1DiyU4vDgGnBj3ny/Q7kLMvJkLq3JnoVSPDzN/FicdeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389318; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rxIBmswNh0tIGuyehJwJsuO5I+nId1kc+WGKDH86wIY=; b=Hb+S/i9j78KpdIbdYrMFzr8Lgz0CgPSx+17koRgRMsbmkD+lc4QlzBJtIBeMX66j9nNCirTRb8PltUC4PuqP1d9qrcwuBIxzqynmD5TFZixA9SBuD0NIibcKKkpZfWYaC5W1vVDK3av4lL8svf4r2gMLHkmr00yGOp5Bq8aM36w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389318900843.3804185246972; Tue, 25 Aug 2020 14:01:58 -0700 (PDT) Received: from localhost ([::1]:45218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg4r-0000ME-IL for importer@patchew.org; Tue, 25 Aug 2020 17:01:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg2x-0006su-SQ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 16:59:59 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:32848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg2w-0001cL-A5 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 16:59:59 -0400 Received: by mail-pf1-x444.google.com with SMTP id u20so8300628pfn.0 for ; Tue, 25 Aug 2020 13:59:57 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rxIBmswNh0tIGuyehJwJsuO5I+nId1kc+WGKDH86wIY=; b=LOtU6s9lu5shExjw41c6rKHbfdwBkDJ/k+j+0RQIcHhLeYVUoXPF5sIdGkhQoIc/CS 699txRbQ5YelkbCWPLH9owdGI/EyjIV+tTyqJ4n5b2VsG4W89LkB2EVd3cJnK1IoqVLP LRhBldZAdnh+QRk6oPkDpJAAYiAjrlkNGr+txgNijgHurdtdiHW7vOzXvhvyMP6UeRjW vgHAHxxtdBCvX3bLMuwVLU8s+r8VcNjohcx2opMf1ettKy+ltx1jXVe4LBO7Ty5JT9xI wr0YcU/t261FWKZumjvinaHTHUJQog4swpZ8JQ0CIPoIh/zRwPNdVvoApkz9kvoIhrpS utqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rxIBmswNh0tIGuyehJwJsuO5I+nId1kc+WGKDH86wIY=; b=XVD+46/OUdyXexX/Mn53c/JxhQs4PtgM9qKIV/3uMmB8FTggUJyQtWukBbflXooioc bNNXRwjxRsa0UzzrRUxJtoE+xOmZQXg8rWEWPg0SqK1BZ+jGE7zVZOMAy0zSSagbt/Wt wcJXGb1bDddfnksLbYqEIkBwotdV+18ZIjkSi9BjV9nG1LdC9rFa8Od9ERShZHap6gp4 SJyANWcrxXoHSYsER89Jijp0ZUO2uuFi4Oc9Ziogcn9R6Fn1BZbFvJMETlwaj5aZFZVn egFEBYHznE0qi5hWDB1baSOWtFeMBvvvecHgtGMDmdqoFQDmXve51eoEOMVd5PdyryWQ jA6A== X-Gm-Message-State: AOAM533AZBUB3x2hpz/TOyzztck/sp/Y1CWIvhFaXhINcG0q09VjHqnU OmS124e4CEQFnIQSJGwT4COIOfhLIcyyYg== X-Google-Smtp-Source: ABdhPJwpTvAafnclmRaeqBNR2IFwVR6V9a4ijA5W4FX4iKVV8ZMT+rGQ/MTdmYrVSrAzzcI7jq9Xbw== X-Received: by 2002:a62:1d05:: with SMTP id d5mr5501965pfd.63.1598389196565; Tue, 25 Aug 2020 13:59:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/77] tests/tcg: Do not require FE_* exception bits Date: Tue, 25 Aug 2020 13:58:36 -0700 Message-Id: <20200825205950.730499-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Define anything that is missing as 0, so that flags & FE_FOO is false for any missing FOO. Cc: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- tests/tcg/multiarch/float_helpers.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/tcg/multiarch/float_helpers.h b/tests/tcg/multiarch/floa= t_helpers.h index 6337bc66c1..309f3f4bf1 100644 --- a/tests/tcg/multiarch/float_helpers.h +++ b/tests/tcg/multiarch/float_helpers.h @@ -8,6 +8,23 @@ =20 #include =20 +/* Some hosts do not have support for all of these; not required by ISO C.= */ +#ifndef FE_OVERFLOW +#define FE_OVERFLOW 0 +#endif +#ifndef FE_UNDERFLOW +#define FE_UNDERFLOW 0 +#endif +#ifndef FE_DIVBYZERO +#define FE_DIVBYZERO 0 +#endif +#ifndef FE_INEXACT +#define FE_INEXACT 0 +#endif +#ifndef FE_INVALID +#define FE_INVALID 0 +#endif + /* Number of constants in each table */ int get_num_f16(void); int get_num_f32(void); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389440; cv=none; d=zohomail.com; s=zohoarc; b=dLWqFgCgAqpVuaG9+wLPUiQvh5vLEFlzT+SFgmWGWBALOssIMiqhyR6mUTGtKj2kTVdJOsLf83JaAy7u4B1WSZ42um452HxNknKIJYQ8KQ4Dj7H2yZeNk6ZnXP/vA5XrGW0bwyhFtOfDRKHcr8fWBrOY63izaglgrEPt/dtQi+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389440; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=nQL4y5kmPCkgxOXdZ8PrSMjdSSy1kB8fvgFUEMn3o+iwkUZz6gUqKKXlBf/Bpaz6sH4SiLzM87P/o/JPSiGHkrf+NyopmtSFQdZNMVduYCrg2nHT7xNf2wcUGNyUyEjCiN6tcOZ5Caqa3YQq7El45jD0wAOpquJAbLiaXNhGRE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389440354534.3145286468539; Tue, 25 Aug 2020 14:04:00 -0700 (PDT) Received: from localhost ([::1]:53698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg6p-0003uV-0l for importer@patchew.org; Tue, 25 Aug 2020 17:03:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg2z-0006vI-Q2 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:01 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:39046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg2x-0001cb-NS for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:01 -0400 Received: by mail-pj1-x1043.google.com with SMTP id j13so118705pjd.4 for ; Tue, 25 Aug 2020 13:59:59 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=J9K799MQUJG8gJFsWlmvUn/p7lg5eagJFY+rlKjGdkmdPDx5sV6qSvZ8onlvQbs2aI FohWbPjvbwsp5mULvYai/SMy4GH2gOeZaJX0x8d0x5829N3Ps6ObkhQXAhCKrldjOk4R gQXFhWSB0vFoJHPvbJV+urCocd9nh9GcavmG7iyO77Y9OxUfwWCyEYCMBF2SLlvc5ZQA WvS6muzuBHHqywNjAFgtUZCUGk5sZT8WKEFg/LoWez+a/uYC36P6dodL5iGkGXzzqwnd v5U+NBuTPoeNQYaEZzB1TllVoCVkH7KhIIsbJr7pkR/dvZG7HR5+zpYi0cgxvzoRr12j ga5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6qPmiblB+ZyNN9MP1YkeatmcIUSnXTMdD0ACsae5YvQ=; b=nk/PwpZNuOCZUpVAfzS9A2UKAqhZhV8cX5CATnOT6j3zmuSZbOAURe7+NHPrrHU4EI XWSd8wXwQKNVzJ8VY+HCPg5KtOB0Cc1wiDeB09VTkDng0daV6IoInZkgObEauZy36QYg +l2ociCxORK27fgA3eEeW4DRovONfhO1UYItSSRjCasDfz4ecK3Bbt3pyb4Z0o0+UAxI I+67pxJGOLnzLyGHWyPIPlTkeLWluhFRc+CnB+rrG7WJgymI1ZC264ow/fJmzpmWApxK kHDGTJA+9ZLrLVcw2s8dAwyQ+MXzWxRR7wI9uRPms0/PZUFTFTE0KiFXRDcoyC7wtn8w 1a6A== X-Gm-Message-State: AOAM532+ffXkRjaJKoYzROvJ/EE8kuBa6rl/c9iS6W5r9ZAVwfsvGJLX CRprEMdLtiiBelZBE/zmGPNDc4EK2dWQtQ== X-Google-Smtp-Source: ABdhPJyKyOZbDBqCsyO8yEnRlgiP9zigUCQrn8YdBYEVFnxbuUKPRl9JUQIC7gUGCcoSZPy3R/RhKw== X-Received: by 2002:a17:90a:1117:: with SMTP id d23mr3065772pja.33.1598389197690; Tue, 25 Aug 2020 13:59:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/77] target/microblaze: Tidy gdbstub Date: Tue, 25 Aug 2020 13:58:37 -0700 Message-Id: <20200825205950.730499-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Signed-off-by: Richard Henderson --- target/microblaze/gdbstub.c | 193 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 92 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 73e8973597..e65ec051a5 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -21,58 +21,80 @@ #include "cpu.h" #include "exec/gdbstub.h" =20 +/* + * GDB expects SREGs in the following order: + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. + * + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't + * map them to anything and return a value of 0 instead. + */ + +enum { + GDB_PC =3D 32 + 0, + GDB_MSR =3D 32 + 1, + GDB_EAR =3D 32 + 2, + GDB_ESR =3D 32 + 3, + GDB_FSR =3D 32 + 4, + GDB_BTR =3D 32 + 5, + GDB_PVR0 =3D 32 + 6, + GDB_PVR11 =3D 32 + 17, + GDB_EDR =3D 32 + 18, + GDB_SLR =3D 32 + 25, + GDB_SHR =3D 32 + 26, +}; + int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUClass *cc =3D CPU_GET_CLASS(cs); CPUMBState *env =3D &cpu->env; - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLB= HI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything and return a value of 0 instead. - */ - static const uint8_t sreg_map[6] =3D { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; + uint32_t val; =20 - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { - return gdb_get_reg32(mem_buf, env->regs[n]); - } else { - n -=3D 32; - switch (n) { - case 0 ... 5: - return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); - /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -=3D 6; - return gdb_get_reg32(mem_buf, env->pvr.regs[n]); - case 18: - return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); - /* Other SRegs aren't modeled, so report a value of 0 */ - case 19 ... 24: - return gdb_get_reg32(mem_buf, 0); - case 25: - return gdb_get_reg32(mem_buf, env->slr); - case 26: - return gdb_get_reg32(mem_buf, env->shr); - default: - return 0; - } + if (n > cc->gdb_num_core_regs) { + return 0; } + + switch (n) { + case 1 ... 31: + val =3D env->regs[n]; + break; + case GDB_PC: + val =3D env->sregs[SR_PC]; + break; + case GDB_MSR: + val =3D env->sregs[SR_MSR]; + break; + case GDB_EAR: + val =3D env->sregs[SR_EAR]; + break; + case GDB_ESR: + val =3D env->sregs[SR_ESR]; + break; + case GDB_FSR: + val =3D env->sregs[SR_FSR]; + break; + case GDB_BTR: + val =3D env->sregs[SR_BTR]; + break; + case GDB_PVR0 ... GDB_PVR11: + /* PVR12 is intentionally skipped */ + val =3D env->pvr.regs[n - GDB_PVR0]; + break; + case GDB_EDR: + val =3D env->sregs[SR_EDR]; + break; + case GDB_SLR: + val =3D env->slr; + break; + case GDB_SHR: + val =3D env->shr; + break; + default: + /* Other SRegs aren't modeled, so report a value of 0 */ + val =3D 0; + break; + } + return gdb_get_reg32(mem_buf, val); } =20 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) CPUMBState *env =3D &cpu->env; uint32_t tmp; =20 - /* - * GDB expects SREGs in the following order: - * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLB= HI. - * They aren't stored in this order, so make a map. - * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't - * map them to anything. - */ - static const uint8_t sreg_map[6] =3D { - SR_PC, - SR_MSR, - SR_EAR, - SR_ESR, - SR_FSR, - SR_BTR - }; - if (n > cc->gdb_num_core_regs) { return 0; } =20 tmp =3D ldl_p(mem_buf); =20 - /* - * GDB expects registers to be reported in this order: - * R0-R31 - * PC-BTR - * PVR0-PVR11 - * EDR-TLBHI - * SLR-SHR - */ - if (n < 32) { + switch (n) { + case 1 ... 31: env->regs[n] =3D tmp; - } else { - n -=3D 32; - switch (n) { - case 0 ... 5: - env->sregs[sreg_map[n]] =3D tmp; - break; + break; + case GDB_PC: + env->sregs[SR_PC] =3D tmp; + break; + case GDB_MSR: + env->sregs[SR_MSR] =3D tmp; + break; + case GDB_EAR: + env->sregs[SR_EAR] =3D tmp; + break; + case GDB_ESR: + env->sregs[SR_ESR] =3D tmp; + break; + case GDB_FSR: + env->sregs[SR_FSR] =3D tmp; + break; + case GDB_BTR: + env->sregs[SR_BTR] =3D tmp; + break; + case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - case 6 ... 17: - n -=3D 6; - env->pvr.regs[n] =3D tmp; - break; - /* Only EDR is modeled in these indeces, so ignore the rest */ - case 18: - env->sregs[SR_EDR] =3D tmp; - break; - case 25: - env->slr =3D tmp; - break; - case 26: - env->shr =3D tmp; - break; - } + env->pvr.regs[n - GDB_PVR0] =3D tmp; + break; + case GDB_EDR: + env->sregs[SR_EDR] =3D tmp; + break; + case GDB_SLR: + env->slr =3D tmp; + break; + case GDB_SHR: + env->shr =3D tmp; + break; } return 4; } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389324; cv=none; d=zohomail.com; s=zohoarc; b=EEucf3Z7PZVmX2TSrIzvt9gClHTKZCZpYodcwhDGDVJtjviRBkvg3R/S7zVOSQvmL6nqVWjLWamjRTjgSz61ldzzK6LjfM4SdODsKsUmyj/3DJJ9KF/d3tmdOWf9Vsr7C1WbesZEkvCoQRuc8ceJYcosGlBhit6BdJPoEH/EsT0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389324; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4OXLnCdYVi2j43Kppbpt72ljKyfNbleLew6fTqAwaaE=; b=TfGRD+nO6zuj7hLyVnH0GGGZP5+1p/LNPRLIBYIlJX/MraG3+irS+wumrBvjAmpXMj4iYRvy0Cufpn9sBlaE5/VMOWoJwrpL6OQc/wdFoMJeXaQgmvscYPlSJ+G8m1of3fpYpWW5M8QFpG4qu4bpSMMzGXV6b4qLQX1gvVQp/Hk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389324445532.0942747337806; Tue, 25 Aug 2020 14:02:04 -0700 (PDT) Received: from localhost ([::1]:45726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg4x-0000ar-1P for importer@patchew.org; Tue, 25 Aug 2020 17:02:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg31-0006xk-Pl for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:03 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:54321) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg2y-0001cq-T3 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:03 -0400 Received: by mail-pj1-x1043.google.com with SMTP id mt12so118841pjb.4 for ; Tue, 25 Aug 2020 14:00:00 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 ++- linux-user/microblaze/cpu_loop.c | 12 +++++------ linux-user/microblaze/signal.c | 8 ++++---- target/microblaze/cpu.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 34 ++++++++++++++++---------------- target/microblaze/mmu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 10 +++++++--- 9 files changed, 42 insertions(+), 37 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a31134b65c..d1f91bb318 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,6 +236,7 @@ struct CPUMBState { =20 uint32_t imm; uint32_t regs[32]; + uint64_t pc; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -351,7 +352,7 @@ typedef MicroBlazeCPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { - *pc =3D env->sregs[SR_PC]; + *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 3e0a7f730b..3c693086f4 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -51,7 +51,7 @@ void cpu_loop(CPUMBState *env) case EXCP_BREAK: /* Return address is 4 bytes after the call. */ env->regs[14] +=3D 4; - env->sregs[SR_PC] =3D env->regs[14]; + env->pc =3D env->regs[14]; ret =3D do_syscall(env,=20 env->regs[12],=20 env->regs[5],=20 @@ -63,7 +63,7 @@ void cpu_loop(CPUMBState *env) 0, 0); if (ret =3D=3D -TARGET_ERESTARTSYS) { /* Wind back to before the syscall. */ - env->sregs[SR_PC] -=3D 4; + env->pc -=3D 4; } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { env->regs[3] =3D ret; } @@ -73,13 +73,13 @@ void cpu_loop(CPUMBState *env) * not a userspace-usable register, as the kernel may clobber = it * at any point.) */ - env->regs[14] =3D env->sregs[SR_PC]; + env->regs[14] =3D env->pc; break; case EXCP_HW_EXCP: - env->regs[17] =3D env->sregs[SR_PC] + 4; + env->regs[17] =3D env->pc + 4; if (env->iflags & D_FLAG) { env->sregs[SR_ESR] |=3D 1 << 12; - env->sregs[SR_PC] -=3D 4; + env->pc -=3D 4; /* FIXME: if branch was immed, replay the imm as well. */ } =20 @@ -165,5 +165,5 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) env->regs[29] =3D regs->r29; env->regs[30] =3D regs->r30; env->regs[31] =3D regs->r31; - env->sregs[SR_PC] =3D regs->pc; + env->pc =3D regs->pc; } diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 80950c2181..b4eeef4673 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -87,7 +87,7 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPUMBState *env) __put_user(env->regs[29], &sc->regs.r29); __put_user(env->regs[30], &sc->regs.r30); __put_user(env->regs[31], &sc->regs.r31); - __put_user(env->sregs[SR_PC], &sc->regs.pc); + __put_user(env->pc, &sc->regs.pc); } =20 static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *e= nv) @@ -124,7 +124,7 @@ static void restore_sigcontext(struct target_sigcontext= *sc, CPUMBState *env) __get_user(env->regs[29], &sc->regs.r29); __get_user(env->regs[30], &sc->regs.r30); __get_user(env->regs[31], &sc->regs.r31); - __get_user(env->sregs[SR_PC], &sc->regs.pc); + __get_user(env->pc, &sc->regs.pc); } =20 static abi_ulong get_sigframe(struct target_sigaction *ka, @@ -188,7 +188,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->regs[7] =3D frame_addr +=3D offsetof(typeof(*frame), uc); =20 /* Offset of 4 to handle microblaze rtid r14, 0 */ - env->sregs[SR_PC] =3D (unsigned long)ka->_sa_handler; + env->pc =3D (unsigned long)ka->_sa_handler; =20 unlock_user_struct(frame, frame_addr, 1); return; @@ -228,7 +228,7 @@ long do_sigreturn(CPUMBState *env) restore_sigcontext(&frame->uc.tuc_mcontext, env); /* We got here through a sigreturn syscall, our path back is via an rtb insn so setup r14 for that. */ - env->regs[14] =3D env->sregs[SR_PC]; + env->regs[14] =3D env->pc; =20 unlock_user_struct(frame, frame_addr, 0); return -TARGET_QEMU_ESIGRETURN; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 51e5c85b10..bde9992535 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -79,7 +79,7 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 - cpu->env.sregs[SR_PC] =3D value; + cpu->env.pc =3D value; } =20 static bool mb_cpu_has_work(CPUState *cs) @@ -117,7 +117,7 @@ static void mb_cpu_reset(DeviceState *dev) /* Disable stack protector. */ env->shr =3D ~0; =20 - env->sregs[SR_PC] =3D cpu->cfg.base_vectors; + env->pc =3D cpu->cfg.base_vectors; =20 #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e65ec051a5..9ea31f8d2f 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -59,7 +59,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->regs[n]; break; case GDB_PC: - val =3D env->sregs[SR_PC]; + val =3D env->pc; break; case GDB_MSR: val =3D env->sregs[SR_MSR]; @@ -115,7 +115,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->regs[n] =3D tmp; break; case GDB_PC: - env->sregs[SR_PC] =3D tmp; + env->pc =3D tmp; break; case GDB_MSR: env->sregs[SR_MSR] =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ab2ceeb055..5c392deea4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -35,7 +35,7 @@ void mb_cpu_do_interrupt(CPUState *cs) =20 cs->exception_index =3D -1; env->res_addr =3D RES_ADDR_NONE; - env->regs[14] =3D env->sregs[SR_PC]; + env->regs[14] =3D env->pc; } =20 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs) return; } =20 - env->regs[17] =3D env->sregs[SR_PC] + 4; + env->regs[17] =3D env->pc + 4; env->sregs[SR_ESR] &=3D ~(1 << 12); =20 /* Exception breaks branch + dslot sequence? */ @@ -145,15 +145,15 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " "esr=3D%" PRIx64 " iflags=3D%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], + env->pc, env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] =3D cpu->cfg.base_vectors + 0x20; + env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 case EXCP_MMU: - env->regs[17] =3D env->sregs[SR_PC]; + env->regs[17] =3D env->pc; =20 env->sregs[SR_ESR] &=3D ~(1 << 12); /* Exception breaks branch + dslot sequence? */ @@ -169,7 +169,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "bimm exception at pc=3D%" PRIx64 " " "iflags=3D%x\n", - env->sregs[SR_PC], env->iflags); + env->pc, env->iflags); env->regs[17] -=3D 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } @@ -188,10 +188,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=3D%" PRIx64 " ear=3D%" PRIx64 "= " "iflags=3D%x\n", - env->sregs[SR_PC], env->sregs[SR_EAR], env->ifla= gs); + env->pc, env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] =3D cpu->cfg.base_vectors + 0x20; + env->pc =3D cpu->cfg.base_vectors + 0x20; break; =20 case EXCP_IRQ: @@ -209,14 +209,14 @@ void mb_cpu_do_interrupt(CPUState *cs) { const char *sym; =20 - sym =3D lookup_symbol(env->sregs[SR_PC]); + sym =3D lookup_symbol(env->pc); if (sym && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { =20 qemu_log( "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x sym= =3D%s\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->if= lags, + env->pc, env->sregs[SR_MSR], t, env->iflags, sym); =20 log_cpu_state(cs, 0); @@ -226,14 +226,14 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%" PRIx64 " msr=3D%" PRIx64 " = %x " "iflags=3D%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->if= lags); + env->pc, env->sregs[SR_MSR], t, env->iflags); =20 env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM \ | MSR_UM | MSR_IE); env->sregs[SR_MSR] |=3D t; =20 - env->regs[14] =3D env->sregs[SR_PC]; - env->sregs[SR_PC] =3D cpu->cfg.base_vectors + 0x10; + env->regs[14] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; =20 @@ -245,17 +245,17 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=3D%" PRIx64 " msr=3D%" PRIx64 " %x " "iflags=3D%x\n", - env->sregs[SR_PC], env->sregs[SR_MSR], t, env->ifl= ags); + env->pc, env->sregs[SR_MSR], t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |=3D t; env->sregs[SR_MSR] |=3D MSR_BIP; if (cs->exception_index =3D=3D EXCP_HW_BREAK) { - env->regs[16] =3D env->sregs[SR_PC]; + env->regs[16] =3D env->pc; env->sregs[SR_MSR] |=3D MSR_BIP; - env->sregs[SR_PC] =3D cpu->cfg.base_vectors + 0x18; + env->pc =3D cpu->cfg.base_vectors + 0x18; } else - env->sregs[SR_PC] =3D env->btarget; + env->pc =3D env->btarget; break; default: cpu_abort(cs, "unhandled exception type=3D%d\n", diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 6763421ba2..3f403b567b 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -251,7 +251,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=3D%" PRIx64 "\n", - i, env->sregs[SR_PC]); + i, env->pc); env->mmu.tids[i] =3D env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f3b17a95b3..2deef32740 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,7 +75,7 @@ void helper_debug(CPUMBState *env) { int i; =20 - qemu_log("PC=3D%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("PC=3D%" PRIx64 "\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a96cb21d96..9f6815cc1f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1805,7 +1805,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) } =20 qemu_fprintf(f, "IN: PC=3D%" PRIx64 " %s\n", - env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); + env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", @@ -1868,7 +1868,11 @@ void mb_tcg_init(void) offsetof(CPUMBState, regs[i]), regnames[i]); } - for (i =3D 0; i < ARRAY_SIZE(cpu_SR); i++) { + + cpu_SR[SR_PC] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + + for (i =3D 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); @@ -1878,5 +1882,5 @@ void mb_tcg_init(void) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, target_ulong *data) { - env->sregs[SR_PC] =3D data[0]; + env->pc =3D data[0]; } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.13.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 13:59:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FtEPL/E9lzDT+6PJrqbAO+r8K2BAzAB3u+X3MwdzqPI=; b=zgfJ8FPhE5Cmw1qKAE/xbui7J9BVJXpzpEQD8Pm2albhra/oaGRqO5TdNoCOmM9QWd 85XMqNu0ImP912jw3JkQhOCNeykeguXFkexr7hWuskKHaMayKGb+IEcWR+H0R/pjglkm tThYFC6LQRrR5qRpnr4I+/CxdBY6aegVwA/jHIwxV3YnAXD/5djsGu1L2QYD3sXcX4Ib M510Bm3hxbi0dvpO0XTz5zywxJ8G3XnGbPi7jKDAHobhE3wZi7nB9FM6UQqWYklgZK9k cNMsHNaQDMH+/MseiI6GozznsxG3nUZtnBic6p0OzgXdJLXJedOb5MmhnCHeOEt3ytbl Aqzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FtEPL/E9lzDT+6PJrqbAO+r8K2BAzAB3u+X3MwdzqPI=; b=e70YVNrGSdXii5k3SK9AbDhYVMnd7CqKjFfxcnYiE86UZh7mmLRlYcr5poT+3Bm/hE PEmTwWvSi1cA0IOzR0U8+HnU06n9Goy9rsmg88ke37AwYfokXKmlFv6alY8uN31w2oMf sBP8eF7+ymYyit0CbB+D7lEDmaEfIwSMNmofKktEpmGwIONO2yRIsfB7No5rLHIPGL/y 6aCRceqP60wuft5wp35X+kiRdXmr0fAuyepxMaYTHvDr1gWMyY3+AuQzewNqxFpnDeG4 /Fr3Ekq8GZwd5b7NrbLHgBwAmy7HFOcskR3ZtSJYoVsOPF40qNB1hR5yYfcGWJdPt/9p YTLA== X-Gm-Message-State: AOAM5308tm1belP+BjJ+BD2z288qQr0FGPzEaiVI8kvH7TJSizkCuUEU aEIj1fFnIqYaT1rNXLlUEJ74BdncF9XDHg== X-Google-Smtp-Source: ABdhPJy3jDaqYQ4VXSx1kE4AdY+nFP5LtY09MmNqaGAj3dKg8HtHHol+TD4i/TgGHWXs3r8Rs63Shw== X-Received: by 2002:a63:de4d:: with SMTP id y13mr8266109pgi.247.1598389200357; Tue, 25 Aug 2020 14:00:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/77] target/microblaze: Split out MSR from env->sregs Date: Tue, 25 Aug 2020 13:58:39 -0700 Message-Id: <20200825205950.730499-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 7 ++--- target/microblaze/cpu.c | 4 +-- target/microblaze/gdbstub.c | 4 +-- target/microblaze/helper.c | 49 +++++++++++++++++------------------ target/microblaze/op_helper.c | 22 ++++++++-------- target/microblaze/translate.c | 14 +++++----- 6 files changed, 51 insertions(+), 49 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d1f91bb318..36de61d9f9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,6 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint64_t pc; + uint64_t msr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env= , target_ulong *pc, *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->iflags & IFLAGS_TB_MASK) | - (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); + (env->msr & (MSR_UM | MSR_VM | MSR_EE)); } =20 #if !defined(CONFIG_USER_ONLY) @@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool= ifetch) MicroBlazeCPU *cpu =3D env_archcpu(env); =20 /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } =20 - if (env->sregs[SR_MSR] & MSR_UM) { + if (env->msr & MSR_UM) { return MMU_USER_IDX; } return MMU_KERNEL_IDX; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bde9992535..0eac068570 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) =20 #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] =3D MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->msr =3D MSR_EE | MSR_IE | MSR_VM | MSR_UM; #else - env->sregs[SR_MSR] =3D 0; + env->msr =3D 0; mmu_init(&env->mmu); env->mmu.c_mmu =3D 3; env->mmu.c_mmu_tlb_access =3D 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9ea31f8d2f..e4c4936a7a 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->pc; break; case GDB_MSR: - val =3D env->sregs[SR_MSR]; + val =3D env->msr; break; case GDB_EAR: val =3D env->sregs[SR_EAR]; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->pc =3D tmp; break; case GDB_MSR: - env->sregs[SR_MSR] =3D tmp; + env->msr =3D tmp; break; case GDB_EAR: env->sregs[SR_EAR] =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5c392deea4..a18314540f 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ +/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr =3D RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 /* Disable the MMU. */ - t =3D (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |=3D t; + t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |=3D t; /* Exception in progress. */ - env->sregs[SR_MSR] |=3D MSR_EIP; + env->msr |=3D MSR_EIP; =20 qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " @@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 /* Disable the MMU. */ - t =3D (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; - env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |=3D t; + t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; + env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |=3D t; /* Exception in progress. */ - env->sregs[SR_MSR] |=3D MSR_EIP; + env->msr |=3D MSR_EIP; =20 qemu_log_mask(CPU_LOG_INT, "exception at pc=3D%" PRIx64 " ear=3D%" PRIx64 "= " @@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; =20 case EXCP_IRQ: - assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))); - assert(env->sregs[SR_MSR] & MSR_IE); + assert(!(env->msr & (MSR_EIP | MSR_BIP))); + assert(env->msr & MSR_IE); assert(!(env->iflags & D_FLAG)); =20 - t =3D (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; =20 #if 0 #include "disas/disas.h" @@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs) =20 qemu_log( "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x sym= =3D%s\n", - env->pc, env->sregs[SR_MSR], t, env->iflags, + env->pc, env->msr, t, env->iflags, sym); =20 log_cpu_state(cs, 0); @@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%" PRIx64 " msr=3D%" PRIx64 " = %x " "iflags=3D%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); =20 - env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM \ - | MSR_UM | MSR_IE); - env->sregs[SR_MSR] |=3D t; + env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + env->msr |=3D t; =20 env->regs[14] =3D env->pc; env->pc =3D cpu->cfg.base_vectors + 0x10; @@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t =3D (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1; + t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=3D%" PRIx64 " msr=3D%" PRIx64 " %x " "iflags=3D%x\n", - env->pc, env->sregs[SR_MSR], t, env->iflags); + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->sregs[SR_MSR] |=3D t; - env->sregs[SR_MSR] |=3D MSR_BIP; + env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + env->msr |=3D t; + env->msr |=3D MSR_BIP; if (cs->exception_index =3D=3D EXCP_HW_BREAK) { env->regs[16] =3D env->pc; - env->sregs[SR_MSR] |=3D MSR_BIP; + env->msr |=3D MSR_BIP; env->pc =3D cpu->cfg.base_vectors + 0x18; } else env->pc =3D env->btarget; @@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) CPUMBState *env =3D &cpu->env; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) + && (env->msr & MSR_IE) + && !(env->msr & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { cs->exception_index =3D EXCP_IRQ; mb_cpu_do_interrupt(cs); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2deef32740..3668382d36 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,14 +78,14 @@ void helper_debug(CPUMBState *env) qemu_log("PC=3D%" PRIx64 "\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%s) eip= =3D%d ie=3D%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i =3D 0; i < 32; i++) { qemu_log("r%2.2d=3D%8.8x ", i, env->regs[i]); if ((i + 1) % 4 =3D=3D 0) @@ -135,15 +135,15 @@ static inline int div_prepare(CPUMBState *env, uint32= _t a, uint32_t b) MicroBlazeCPU *cpu =3D env_archcpu(env); =20 if (b =3D=3D 0) { - env->sregs[SR_MSR] |=3D MSR_DZ; + env->msr |=3D MSR_DZ; =20 - if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] =3D ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; } - env->sregs[SR_MSR] &=3D ~MSR_DZ; + env->msr &=3D ~MSR_DZ; return 1; } =20 @@ -192,7 +192,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) } if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) - && (env->sregs[SR_MSR] & MSR_EE)) { + && (env->msr & MSR_EE)) { raise_fpu_exception(env); } } @@ -437,7 +437,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, if (mask =3D=3D 3) { env->sregs[SR_ESR] |=3D 1 << 11; } - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } helper_raise_exception(env, EXCP_HW_EXCP); @@ -484,7 +484,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr phy= saddr, vaddr addr, env =3D &cpu->env; =20 cpu_restore_state(cs, retaddr, true); - if (!(env->sregs[SR_MSR] & MSR_EE)) { + if (!(env->msr & MSR_EE)) { return; } =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f6815cc1f..9f2dcd82cd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,16 +1809,16 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", - env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR= ], + env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " "eip=3D%d ie=3D%d\n", env->btaken, env->btarget, - (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (bool)(env->sregs[SR_MSR] & MSR_EIP), - (bool)(env->sregs[SR_MSR] & MSR_IE)); + (env->msr & MSR_UM) ? "user" : "kernel", + (env->msr & MSR_UMS) ? "user" : "kernel", + (bool)(env->msr & MSR_EIP), + (bool)(env->msr & MSR_IE)); for (i =3D 0; i < 12; i++) { qemu_fprintf(f, "rpvr%2.2d=3D%8.8x ", i, env->pvr.regs[i]); if ((i + 1) % 4 =3D=3D 0) { @@ -1871,8 +1871,10 @@ void mb_tcg_init(void) =20 cpu_SR[SR_PC] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + cpu_SR[SR_MSR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); =20 - for (i =3D 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389578; cv=none; d=zohomail.com; s=zohoarc; b=Y+mrXTi2elF9XEsTdZTqBOmXrBHY2CE2XIOpEepG+qRbRlCJ+mMdiBH2lxOFl6GBMWxukZTntODWZVU1teRdnm+lHF6HkPPaIj80Nhgxh5oKGWVY3O09yp1KN3s+1JQsgwOz7IJpkoH8VMXZr6lvAjdpbfpvYq8zR928ke4NQYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389578; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3AKOFIW3VCEZ6h4ggmUpiB5wdoa5LhPs+jftJ9b2SfM=; b=kkt/coxxEpJCckBG/CzHRUrJT6yPTmVn7FHkP4Ps6D0zf+FYcLD05B0/EyxctAKgU2y037UolC9m/8ToP1RFu/0nUd8/1nHHlXDmn3h+kdUknZE6rGTrOmHk9cWd5M4d+3rs9ZFyPDUvfeFi1p8cGUTbDjmK76meFoF86+Tq52Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389578706941.070134918798; Tue, 25 Aug 2020 14:06:18 -0700 (PDT) Received: from localhost ([::1]:33848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg93-0007Td-EY for importer@patchew.org; Tue, 25 Aug 2020 17:06:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg33-00070P-JX for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:05 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:36366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg31-0001d8-Au for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:05 -0400 Received: by mail-pf1-x444.google.com with SMTP id m8so8305016pfh.3 for ; Tue, 25 Aug 2020 14:00:02 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3AKOFIW3VCEZ6h4ggmUpiB5wdoa5LhPs+jftJ9b2SfM=; b=IaanKXrCmMh3H59/7HKhL+NTg2x+i1oQ/SdB8jMjmQ7pDB0alzia1+N5Pjcfjd/g/Z PIk4wwS1s4/STGg6A+aroQ1+WyF4469MKp/711grmjB8Lv3CjwYcWXOuXhdZ5l7BKMB/ TYlaQiE9cRoYLSggK+ZORZkYfG9p+r7iuc7MPJ9HoVogaO3cQT4muSxYdkb2civ5Af1Z Dw9MlkI3c9ew/OzZb8Iur0i8vQ3eJ6AH8Uo8x9OTV1DRrrqrqe1XiJEEQ1NrqjEorMIl PztLWKHhLRszKeA+sqJGRNNKmSXCYH35SRXID22wjhe8k4tkyyREAN7YBIp9aEgMm4lt o57g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3AKOFIW3VCEZ6h4ggmUpiB5wdoa5LhPs+jftJ9b2SfM=; b=dQYWWRCcDcL5fM/YzFmtsk5lDgat4v8voDJ2rSVIFS6PPYKkByz1JeOxbNiVP7XJCp eNOCFNuRmaysnRBYTc2HngGb6w643AvmliR4bjBRivdhbBR3aXGl3DLVLoiLGjLfg4b+ Mi+YMmLOlV4HlOYEm1OhyABmIhpU/p5n+eyZOBQZU3cBNhUmyrKdcMGz4E/fQ6nLCBWr OV/SbqttdxGc+7nhg+Nm5usvRFkX8iWxQYo8mtzNzxwwXhGAyeZfoPDTctXn/d5z8TmC 017V2b6qLiN9B2Q06lB/YkAva70S7n9v7OUMe4h+WnitbEgLyFFKxeQAxG9rsDdiSRM7 pk0A== X-Gm-Message-State: AOAM5301NNfxYZjA9XGII4RrarUZRZG2kvvjOcXu36sUMDszNmrBVvHj 5imzylXjb1Hf8Q1rAe8ikEHmkI86JujxDg== X-Google-Smtp-Source: ABdhPJxy71saGP8dnmh78ZXRtiQWs/WrK3AmA5qqqytpYq/iBa+Q4XpyxgOucSCML4gFLbeDAvyn9Q== X-Received: by 2002:a62:8f51:: with SMTP id n78mr9374812pfd.74.1598389201475; Tue, 25 Aug 2020 14:00:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/77] target/microblaze: Split out EAR from env->sregs Date: Tue, 25 Aug 2020 13:58:40 -0700 Message-Id: <20200825205950.730499-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 6 +++--- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 36de61d9f9..c9035b410e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -238,6 +238,7 @@ struct CPUMBState { uint32_t regs[32]; uint64_t pc; uint64_t msr; + uint64_t ear; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e4c4936a7a..e33a613efe 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->msr; break; case GDB_EAR: - val =3D env->sregs[SR_EAR]; + val =3D env->ear; break; case GDB_ESR: val =3D env->sregs[SR_ESR]; @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->msr =3D tmp; break; case GDB_EAR: - env->sregs[SR_EAR] =3D tmp; + env->ear =3D tmp; break; case GDB_ESR: env->sregs[SR_ESR] =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a18314540f..afe9634781 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int siz= e, qemu_log_mask(CPU_LOG_MMU, "mmu=3D%d miss v=3D%" VADDR_PRIx "\n", mmu_idx, address); =20 - env->sregs[SR_EAR] =3D address; + env->ear =3D address; switch (lu.err) { case ERR_PROT: env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " "esr=3D%" PRIx64 " iflags=3D%x\n", - env->pc, env->sregs[SR_EAR], + env->pc, env->ear, env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=3D%" PRIx64 " ear=3D%" PRIx64 "= " "iflags=3D%x\n", - env->pc, env->sregs[SR_EAR], env->iflags); + env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); env->pc =3D cpu->cfg.base_vectors + 0x20; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 3668382d36..5bacd29663 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=3D%" PRIx64 "\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%s) eip= =3D%d ie=3D%d\n", env->btaken, env->btarget, @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr, "unaligned access addr=3D" TARGET_FMT_lx " mask=3D%x, wr=3D%d dr=3Dr%d\n", addr, mask, wr, dr); - env->sregs[SR_EAR] =3D addr; + env->ear =3D addr; env->sregs[SR_ESR] =3D ESR_EC_UNALIGNED_DATA | (wr << 10) \ | (dr & 31) << 5; if (mask =3D=3D 3) { @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong add= r) qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); - env->sregs[SR_EAR] =3D addr; + env->ear =3D addr; env->sregs[SR_ESR] =3D ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr phy= saddr, vaddr addr, return; } =20 - env->sregs[SR_EAR] =3D addr; + env->ear =3D addr; if (access_type =3D=3D MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] =3D ESR_EC_INSN_BUS; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9f2dcd82cd..62747b02f3 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], + env->msr, env->sregs[SR_ESR], env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " @@ -1873,8 +1873,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_SR[SR_MSR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_SR[SR_EAR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); =20 - for (i =3D SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389328; cv=none; d=zohomail.com; s=zohoarc; b=VZw6e6E6ZAm4XdL9j4y/ESByIobdtYHvUMnxv3W12ngJgmWY/Z2eYZ4QJC3WXFwdMW/obg8C3ewG9oQk8axoBlTz8nur+/dpOe/VUa4L3ady0FJsXxtMBVhbvNjYyHrGHgUGZrKrjkA1o/fl2SJg73Rr/+9cEJshH9zNukcIl7U= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 6 +++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 18 +++++++++--------- target/microblaze/op_helper.c | 17 ++++++++--------- target/microblaze/translate.c | 6 ++++-- 6 files changed, 27 insertions(+), 25 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c9035b410e..7d94af43ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,6 +239,7 @@ struct CPUMBState { uint64_t pc; uint64_t msr; uint64_t ear; + uint64_t esr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 3c693086f4..c10e3e0261 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env) case EXCP_HW_EXCP: env->regs[17] =3D env->pc + 4; if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |=3D 1 << 12; + env->esr |=3D 1 << 12; env->pc -=3D 4; /* FIXME: if branch was immed, replay the imm as well. */ } =20 env->iflags &=3D ~(IMM_FLAG | D_FLAG); =20 - switch (env->sregs[SR_ESR] & 31) { + switch (env->esr & 31) { case ESR_EC_DIVZERO: info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; @@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env) break; default: fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "= \n", - env->sregs[SR_ESR] & ESR_EC_MASK); + env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); break; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index e33a613efe..05e22f233d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->ear; break; case GDB_ESR: - val =3D env->sregs[SR_ESR]; + val =3D env->esr; break; case GDB_FSR: val =3D env->sregs[SR_FSR]; @@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->ear =3D tmp; break; case GDB_ESR: - env->sregs[SR_ESR] =3D tmp; + env->esr =3D tmp; break; case GDB_FSR: env->sregs[SR_FSR] =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634781..ea290be780 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, env->ear =3D address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; + env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; + env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 env->regs[17] =3D env->pc + 4; - env->sregs[SR_ESR] &=3D ~(1 << 12); + env->esr &=3D ~(1 << 12); =20 /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |=3D 1 << 12 ; + env->esr |=3D 1 << 12 ; env->sregs[SR_BTR] =3D env->btarget; } =20 @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " "esr=3D%" PRIx64 " iflags=3D%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); env->pc =3D cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] =3D env->pc; =20 - env->sregs[SR_ESR] &=3D ~(1 << 12); + env->esr &=3D ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=3D%d\n", env->bim= m)); - env->sregs[SR_ESR] |=3D 1 << 12 ; + env->esr |=3D 1 << 12 ; env->sregs[SR_BTR] =3D env->btarget; =20 /* Reexecute the branch. */ diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29663..f01cf9be64 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=3D%" PRIx64 "\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%s) eip= =3D%d ie=3D%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t= a, uint32_t b) env->msr |=3D MSR_DZ; =20 if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] =3D ESR_EC_DIVZERO; + env->esr =3D ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint3= 2_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] =3D ESR_EC_FPU; + env->esr =3D ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } =20 @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong add= r, " mask=3D%x, wr=3D%d dr=3Dr%d\n", addr, mask, wr, dr); env->ear =3D addr; - env->sregs[SR_ESR] =3D ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr =3D ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) <<= 5; if (mask =3D=3D 3) { - env->sregs[SR_ESR] |=3D 1 << 11; + env->esr |=3D 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong add= r) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear =3D addr; - env->sregs[SR_ESR] =3D ESR_EC_STACKPROT; + env->esr =3D ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, env->ear =3D addr; if (access_type =3D=3D MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] =3D ESR_EC_INSN_BUS; + env->esr =3D ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] =3D ESR_EC_DATA_BUS; + env->esr =3D ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 62747b02f3..411c7b6e49 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->sregs[SR_FSR], env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " @@ -1875,8 +1875,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_SR[SR_EAR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); + cpu_SR[SR_ESR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); =20 - for (i =3D SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389617; cv=none; d=zohomail.com; s=zohoarc; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v5cOPITpAORhIDF2PS7d5r/AWbCGGzSRkZP2Jde8Lx4=; b=pdYgUZe6lsB1pe/3gIVvPQOv5GC3Mqs9Pbpakba3p5aq/sFfxKlTowoIhVu5ZU2Dne rJeM0a2a7oZ5d5HI1lLYoMkbV3tYeAwoqF+/nA133px+lk/i59ApSc4kKUlRHh3sU0fB LBUucSGSRRW508uAh4vlrTkGYXXPrD0hIjO18vm3Vgd0lFz03Fd6BjdGZzmhZMk5AION 5gJasLRTIKp59Y116jgacGKEsik+HFt+e/oN/CMRSq4ppPElhauEYm4Z3IABZ2Z2eMbD YEJOVN+Srbp0C2DcjhqH2e9TqqQkFZbq2sR1gqWlAKU6cFxcclUShdIgnMyjlSwJhEh7 f5VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v5cOPITpAORhIDF2PS7d5r/AWbCGGzSRkZP2Jde8Lx4=; b=J2zQ+ix7/d8Q5bSmGjFehTFKJnjcMGMUaYf/NkYh9KlRZEfhnfNRWmBQKbkZe88/Tm RctcRa7nvkEnu/9lsPYJxIG+bX3nclv16PurKKzeDp1Paq6zofJiwapFUcSb7ai7fexN aIufzBzZ1t0YDzS3MAMRKqz8DakHEaxhO2sLVUtD+m5x9rgT8uwt6Wg6VELGlDog9T73 xR6TRbnGnx/DaXXncnwmfp5RtW/lTlsTFJHmNpu6q/FfBamglbvJtA0Gra3+FXi3LaoO 6F5+yeWBeA9THIqe+dvh+LSo4QAFc/3dgfepTerS5kOBxspUAPn0P/wQnrVMl155zx75 havg== X-Gm-Message-State: AOAM530/lZ9mJ7bDzov4hrC8AjT3PtnSA5hEQ98YdJLGIpf2nKUQbdSH ZG34JmOwx4I0TJZcwIH8GgngcZGBgMmvGQ== X-Google-Smtp-Source: ABdhPJwRp771g8bxWS9TE6h7ALsy/aBl8i8l5h6BKMIqAEBRq9XcrFqcn2qVGKvu1z9uFAaNm/uofg== X-Received: by 2002:a62:7acb:: with SMTP id v194mr9400232pfc.302.1598389203993; Tue, 25 Aug 2020 14:00:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/77] target/microblaze: Split out FSR from env->sregs Date: Tue, 25 Aug 2020 13:58:42 -0700 Message-Id: <20200825205950.730499-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + linux-user/microblaze/cpu_loop.c | 4 ++-- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/op_helper.c | 8 ++++---- target/microblaze/translate.c | 6 ++++-- 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7d94af43ed..bcafef99b0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,6 +240,7 @@ struct CPUMBState { uint64_t msr; uint64_t ear; uint64_t esr; + uint64_t fsr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index c10e3e0261..da5e98b784 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo =3D TARGET_SIGFPE; info.si_errno =3D 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code =3D TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code =3D TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr =3D 0; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 05e22f233d..2634ce49fc 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->esr; break; case GDB_FSR: - val =3D env->sregs[SR_FSR]; + val =3D env->fsr; break; case GDB_BTR: val =3D env->sregs[SR_BTR]; @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->esr =3D tmp; break; case GDB_FSR: - env->sregs[SR_FSR] =3D tmp; + env->fsr =3D tmp; break; case GDB_BTR: env->sregs[SR_BTR] =3D tmp; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f01cf9be64..ae57d45536 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int fla= gs) int raise =3D 0; =20 if (flags & float_flag_invalid) { - env->sregs[SR_FSR] |=3D FSR_IO; + env->fsr |=3D FSR_IO; raise =3D 1; } if (flags & float_flag_divbyzero) { - env->sregs[SR_FSR] |=3D FSR_DZ; + env->fsr |=3D FSR_DZ; raise =3D 1; } if (flags & float_flag_overflow) { - env->sregs[SR_FSR] |=3D FSR_OF; + env->fsr |=3D FSR_OF; raise =3D 1; } if (flags & float_flag_underflow) { - env->sregs[SR_FSR] |=3D FSR_UF; + env->fsr |=3D FSR_UF; raise =3D 1; } if (raise diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 411c7b6e49..c58c49ea8f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->sregs[SR_FSR], + env->debug, env->imm, env->iflags, env->fsr, env->sregs[SR_BTR]); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " "eip=3D%d ie=3D%d\n", @@ -1877,8 +1877,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_SR[SR_ESR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + cpu_SR[SR_FSR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); =20 - for (i =3D SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389701; cv=none; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uVRyTVQxo8OjLoh4LZ/et66lNRgcRHaSjjoCMlpw+SQ=; b=yE1UsFN4anihXN9PFOKhd1TyAM1LP/xfDZHy+g85G6vlKvTxgzxLG5AfU27URAMfF2 MbqNkkBtHNmLr6hnT9t2wqHvYq1cWDD/qe6rCnfSXvuyZ+HC5JOcrnluTXIl/TO7La4R tJGrEeJqEC4eygNcVwauWNl7o3Y2fbjebDCxX/Qdli8Sc0SEcrfX03XXXpB1Len+ybyE tADj2HW9rc9sZwFyll3lyrvKbMdfkf6CGkVMeKCgnHG+AU9/b4LaFpqDSHNJMyznVvmz IvA7SQdS+7YIngbkiXvYeFO9SQW3PURgxUlyInPE1y1KTdSgsMlw2gR1Kwib31OQxb/P +0dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uVRyTVQxo8OjLoh4LZ/et66lNRgcRHaSjjoCMlpw+SQ=; b=omlKj6cdAcEE6cpTZxcITctnF9OWRhRik+r9kr6WTQAm7YNJAtoc0ul6g+mszi3zxG OH1vivvYfVw8hIDzN7pTKNabxdMHwMkZP8vpaiSvM4ni1kAy+/YeOh5tuLnPsmSYyO6L pJFjhZuq4meaQH8o9Eju/4+4qUM+h2Y/jlC4P0ag/1dws0S8f0d49aWLGVCQS27PA1BY GnfrReN7UBQNb4cl9T4Wq8fcYGFWvOMUbULmw20CKGUMQCwpO/IX2RSHJV993TzEPk6n /3Y4CkaQ/D8qpfW/GVcCN90oDtEdTGiKwNzUINNOQEGNAtvGqnsuce+RiefRbTINgIVL k5Zw== X-Gm-Message-State: AOAM530RHP7/fS64jbArhD9kzWBtvBt2hKrDeC1brsOU7DBEm9SR7OyQ LTPABv4+g4vMVzW9I9Bv/kaY7napcgwF9A== X-Google-Smtp-Source: ABdhPJwPeikTZDLVPCgs3H8y5ZKc7bTJXcSdlui+09RJI1tZA3HIVm4rED7TqtZzBxhU9QJSaT1EUA== X-Received: by 2002:a62:82c3:: with SMTP id w186mr8018070pfd.287.1598389205254; Tue, 25 Aug 2020 14:00:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/77] target/microblaze: Split out BTR from env->sregs Date: Tue, 25 Aug 2020 13:58:43 -0700 Message-Id: <20200825205950.730499-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/gdbstub.c | 4 ++-- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 6 ++++-- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index bcafef99b0..deddb47abb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,6 +241,7 @@ struct CPUMBState { uint64_t ear; uint64_t esr; uint64_t fsr; + uint64_t btr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 2634ce49fc..cde8c169bf 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->fsr; break; case GDB_BTR: - val =3D env->sregs[SR_BTR]; + val =3D env->btr; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->fsr =3D tmp; break; case GDB_BTR: - env->sregs[SR_BTR] =3D tmp; + env->btr =3D tmp; break; case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ea290be780..b240dc76f6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { env->esr |=3D 1 << 12 ; - env->sregs[SR_BTR] =3D env->btarget; + env->btr =3D env->btarget; } =20 /* Disable the MMU. */ @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=3D%d\n", env->bim= m)); env->esr |=3D 1 << 12 ; - env->sregs[SR_BTR] =3D env->btarget; + env->btr =3D env->btarget; =20 /* Reexecute the branch. */ env->regs[17] -=3D 4; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c58c49ea8f..469e1f103a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, - env->sregs[SR_BTR]); + env->btr); qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " "eip=3D%d ie=3D%d\n", env->btaken, env->btarget, @@ -1879,8 +1879,10 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_SR[SR_FSR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); + cpu_SR[SR_BTR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); =20 - for (i =3D SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { + for (i =3D SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, sregs[i]), special_regnames[i]); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389858; cv=none; d=zohomail.com; s=zohoarc; b=XLb+8CXjK0KdQ7iFuEertKQJhJy3MNXMIB2t8kM3utZNCGElR9bCDY75nKYRyAJ7zxzo1klmNeB5jEQabQ2tZfd41uIIyJBPVTfnB/tSjWbUB/3MKub3KicHRGxtL3jc3LYhIM5nhrjXviJ7IdqnfzZXu4X/igNF2V6Fd/wziG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389858; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kxuKPEsnkZdfVwCBdweXYlcCCLoCz5+CGJqBlv/VqWk=; b=gKMf0JrIbKunssk9FWPeNQlRB3DSsAYAXS69b4vgoP8yDXF3Vi1fokRfVcEF23zZ5eiba5+oItHScXUK38q7FwncMsvNGtjtoWAy6rRY5trHQDkcbFIigto5OzycFD+Xfw+vc3ay2cErMRIfsEIEEGAoKtb1KWBeSDb9bHe39tE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389858446848.5014657445544; Tue, 25 Aug 2020 14:10:58 -0700 (PDT) Received: from localhost ([::1]:50794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgDY-0005xd-3M for importer@patchew.org; Tue, 25 Aug 2020 17:10:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg38-00079f-88 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:10 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41473) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg36-0001fs-85 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:09 -0400 Received: by mail-pf1-x441.google.com with SMTP id t9so4126129pfq.8 for ; Tue, 25 Aug 2020 14:00:07 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++++++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translate.c | 16 +++------------- 4 files changed, 12 insertions(+), 19 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index deddb47abb..610ddfb719 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint64_t esr; uint64_t fsr; uint64_t btr; - uint64_t sregs[14]; + uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fe9dfe795d..bbfb665321 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1032,9 +1032,12 @@ static void elf_core_copy_regs(target_elf_gregset_t = *regs, const CPUMBState *env (*regs)[pos++] =3D tswapreg(env->regs[i]); } =20 - for (i =3D 0; i < 6; i++) { - (*regs)[pos++] =3D tswapreg(env->sregs[i]); - } + (*regs)[pos++] =3D tswapreg(env->pc); + (*regs)[pos++] =3D tswapreg(env->msr); + (*regs)[pos++] =3D 0; + (*regs)[pos++] =3D tswapreg(env->ear); + (*regs)[pos++] =3D 0; + (*regs)[pos++] =3D tswapreg(env->esr); } =20 #endif /* TARGET_MICROBLAZE */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index cde8c169bf..9cba9d2215 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->pvr.regs[n - GDB_PVR0]; break; case GDB_EDR: - val =3D env->sregs[SR_EDR]; + val =3D env->edr; break; case GDB_SLR: val =3D env->slr; @@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->pvr.regs[n - GDB_PVR0] =3D tmp; break; case GDB_EDR: - env->sregs[SR_EDR] =3D tmp; + env->edr =3D tmp; break; case GDB_SLR: env->slr =3D tmp; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 469e1f103a..7d307e6b48 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -103,12 +103,6 @@ static const char *regnames[] =3D "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; =20 -static const char *special_regnames[] =3D -{ - "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", - "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) =20 /* Registers that aren't modeled are reported as 0 */ qemu_fprintf(f, "redr=3D%" PRIx64 " rpid=3D0 rzpr=3D0 rtlbx=3D0 rtlbsx= =3D0 " - "rtlblo=3D0 rtlbhi=3D0\n", env->sregs[SR_EDR]); + "rtlblo=3D0 rtlbhi=3D0\n", env->edr); qemu_fprintf(f, "slr=3D%x shr=3D%x\n", env->slr, env->shr); for (i =3D 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=3D%8.8x ", i, env->regs[i]); @@ -1881,12 +1875,8 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_SR[SR_BTR] =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - - for (i =3D SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMBState, sregs[i]), - special_regnames[i]); - } + cpu_SR[SR_EDR] =3D + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } =20 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mWZxIEkP4nZuOtJzfgZGg0mAj4EW15ubIN08DOn/YHw=; b=RC6zNY84l5SEbDULSwoVTK/rpCSSMntFEwn/7wJhAlDStBlc/K8rTF6HqceQ0Sr1fF oXniV059a4UXS65ZkQHxhhJImZ71dXWmSIYR2Rrnd9DYheyj89cCV31zKBuXzaj5hGhk EqRgv4+yf/IHmJzXPLUFxw+e74b9SWvAZre9wz2SN+GzCtimYA64gKhjhHSLb0gkqt4G WR141VUEAqxzkFoBUWDwpHEYim/Z/s7rUWNUI2VJ91UpUcpW0ZWIYFxdiEp+NdfO5uHU lSeHRCaNA51UzL5+pR8xLc980mw1ItY5c2qGJ940tXCpIknhJNTowNNG4qjkXzy23Zbt 1M7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mWZxIEkP4nZuOtJzfgZGg0mAj4EW15ubIN08DOn/YHw=; b=T8gEQ1zGjuiWKwf8ZEBFzgIQX3s799oL5rslNJ1ZIPX+wxsKfEl7X/dTknetVHLDuu XjGK2IrTBVHftcQpcgAxI2D7uQ1aqnNZtffd0gjd2ZNVePn3s9CrhJdPJQ9Sdw1JmuN+ clb5o3q/TRwZJOxV199oqwr0qQw7XfGafl3f6r+w+TmBEg0TbKbWNgfblznilNN0Vx5+ I6udYKuuOlYwxLI7FDvotsN41N6uF8AfxdRi/JGUlQydYqFA4myf2fiLXFecOPMes8h/ CsT0QJl5zVrIu6eNhJkmDpapjVBmLpMukaADkjGgoozgBsD/EoBCZ/jpB5YHtRf8qwvB 0eCw== X-Gm-Message-State: AOAM531tf6rAPXy1EHIKGaU6ETan0rXa/eLZ40iJ72da/kaa/AvXSWLf SJjnsp4qUsK6iJzZWy9FjMcf+IzPdJO0Fw== X-Google-Smtp-Source: ABdhPJzK3pjjKYnLw+WGibuE3m3MfG3qR5dvPeo9pyOUkgZQ87i9UB3X438AO4CXYrs9JHWE61h5ug== X-Received: by 2002:a17:90b:40cb:: with SMTP id hj11mr3224573pjb.67.1598389207825; Tue, 25 Aug 2020 14:00:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/77] target/microblaze: Split the cpu_SR array Date: Tue, 25 Aug 2020 13:58:45 -0700 Message-Id: <20200825205950.730499-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Similar to splitting the sregs array, this will allow further fixes and cleanups. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 106 +++++++++++++++++++++------------- 1 file changed, 65 insertions(+), 41 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d307e6b48..19d7b8abfd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,13 @@ =20 static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_SR[14]; +static TCGv_i64 cpu_pc; +static TCGv_i64 cpu_msr; +static TCGv_i64 cpu_ear; +static TCGv_i64 cpu_esr; +static TCGv_i64 cpu_fsr; +static TCGv_i64 cpu_btr; +static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i64 env_btarget; @@ -117,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *= dc, uint32_t index) TCGv_i32 tmp =3D tcg_const_i32(index); =20 t_sync_flags(dc); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp =3D DISAS_UPDATE; @@ -136,17 +142,17 @@ static void gen_goto_tb(DisasContext *dc, int n, targ= et_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i64(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } =20 static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); tcg_gen_shri_i32(d, d, 31); } =20 @@ -159,8 +165,8 @@ static void write_carry(DisasContext *dc, TCGv_i32 v) TCGv_i64 t0 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); - tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); + tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); tcg_temp_free_i64(t0); } =20 @@ -180,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -196,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; =20 if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); + tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -431,7 +437,7 @@ static void dec_xor(DisasContext *dc) =20 static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(d, cpu_msr); } =20 static inline void msr_write(DisasContext *dc, TCGv_i32 v) @@ -443,8 +449,8 @@ static inline void msr_write(DisasContext *dc, TCGv_i32= v) /* PVR bit is not writable. */ tcg_gen_extu_i32_i64(t, v); tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); + tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); + tcg_gen_or_i64(cpu_msr, cpu_msr, t); tcg_temp_free_i64(t); } =20 @@ -503,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); dc->is_jmp =3D DISAS_UPDATE; return; } @@ -535,15 +541,25 @@ static void dec_msr(DisasContext *dc) if (to) { LOG_DIS("m%ss sr%x r%d imm=3D%x\n", to ? "t" : "f", sr, dc->ra, dc= ->imm); switch (sr) { - case 0: + case SR_PC: break; - case 1: + case SR_MSR: msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: + tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + break; case SR_ESR: + tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); + tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + break; + case SR_BTR: + tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + break; + case SR_EDR: + tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -561,22 +577,30 @@ static void dec_msr(DisasContext *dc) LOG_DIS("m%ss r%d sr%x imm=3D%x\n", to ? "t" : "f", dc->rd, sr, dc= ->imm); =20 switch (sr) { - case 0: + case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); break; - case 1: + case SR_MSR: msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); - break; + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); } + break; case SR_ESR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + break; case SR_FSR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + break; case SR_BTR: + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -749,7 +773,7 @@ static void dec_bit(DisasContext *dc) t0 =3D tcg_temp_new_i32(); =20 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t0, cpu_msr); tcg_gen_andi_i32(t0, t0, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { @@ -995,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); =20 tcg_temp_free_i32(t0); @@ -1115,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1169,7 +1193,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 = pc_true, TCGv_i64 pc_false) TCGv_i64 tmp_zero =3D tcg_const_i64(0); =20 tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC], + tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tmp_btaken, tmp_zero, pc_true, pc_false); =20 @@ -1253,7 +1277,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); + tcg_gen_movi_i64(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1309,7 +1333,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1327,7 +1351,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1346,7 +1370,7 @@ static inline void do_rte(DisasContext *dc) t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); =20 - tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); + tcg_gen_extrl_i64_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1401,7 +1425,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu !=3D 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); + tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu =3D=3D 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1652,7 +1676,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) =20 #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); + tcg_gen_movi_i64(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1730,7 +1754,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); sync_jmpstate(dc); } else npc =3D dc->jmp_pc; @@ -1740,7 +1764,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) if (dc->is_jmp =3D=3D DISAS_NEXT && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { dc->is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } t_sync_flags(dc); =20 @@ -1748,7 +1772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); =20 if (dc->is_jmp !=3D DISAS_JUMP) { - tcg_gen_movi_i64(cpu_SR[SR_PC], npc); + tcg_gen_movi_i64(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1863,19 +1887,19 @@ void mb_tcg_init(void) regnames[i]); } =20 - cpu_SR[SR_PC] =3D + cpu_pc =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_SR[SR_MSR] =3D + cpu_msr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_SR[SR_EAR] =3D + cpu_ear =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); - cpu_SR[SR_ESR] =3D + cpu_esr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_SR[SR_FSR] =3D + cpu_fsr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); - cpu_SR[SR_BTR] =3D + cpu_btr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - cpu_SR[SR_EDR] =3D + cpu_edr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389769; cv=none; d=zohomail.com; s=zohoarc; b=UFwLMOMUK8WiBEOay0Jc2XmuqFJnUtDgvAqX4asJ35w5DcGAaPU0j/Wr4yQMVuuL7SDYANBDHHpcRGy9X/ij+tcODbU3UmQV97aPp9fqmAdRmP5NYGWcvd+xkoBcn1m92u5d8UISVyPvYDtqMm4qwT2BDSqazMeN2NQ+W9IpbW4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389769; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rsRB0RZxqoK3N2gzIw0qX54Gonb1t6EonRXZar2I/Yw=; b=b9ACd7Nwr9oe5GpSiwx0xSbtkAqdl2lloBBcuniXR8ZW38V5vF4dyKifslfCaSiw/O78PdTxh+f7L3G7Y6HxFQVsjn0FEtsq/YHQOpKWraZ8DjQzQX8Mxh7iA8QAvbro9JxB5im/VvSVVWmekZgslVnYFtdPMXFdtwXUYWXQm7o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389769813749.8871243855978; Tue, 25 Aug 2020 14:09:29 -0700 (PDT) Received: from localhost ([::1]:45762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgC6-0003u2-F3 for importer@patchew.org; Tue, 25 Aug 2020 17:09:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3C-0007Hn-4w for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:14 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:41466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg39-0001gM-7Y for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:13 -0400 Received: by mail-pg1-x52f.google.com with SMTP id w186so5570209pgb.8 for ; Tue, 25 Aug 2020 14:00:10 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/helper.c | 16 +++---- target/microblaze/mmu.c | 4 +- target/microblaze/op_helper.c | 4 +- target/microblaze/translate.c | 78 ++++++++++++++--------------------- 5 files changed, 43 insertions(+), 63 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 610ddfb719..f4c3c09b09 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,12 +231,12 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t debug; uint32_t btaken; - uint64_t btarget; + uint32_t btarget; uint32_t bimm; =20 uint32_t imm; uint32_t regs[32]; - uint64_t pc; + uint32_t pc; uint64_t msr; uint64_t ear; uint64_t esr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b240dc76f6..b95617a81a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -143,7 +143,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |=3D MSR_EIP; =20 qemu_log_mask(CPU_LOG_INT, - "hw exception at pc=3D%" PRIx64 " ear=3D%" PRIx6= 4 " " + "hw exception at pc=3D%x ear=3D%" PRIx64 " " "esr=3D%" PRIx64 " iflags=3D%x\n", env->pc, env->ear, env->esr, env->iflags); @@ -167,8 +167,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* was the branch immprefixed?. */ if (env->bimm) { qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=3D%" PRIx64 " " - "iflags=3D%x\n", + "bimm exception at pc=3D%x iflags=3D%x\n= ", env->pc, env->iflags); env->regs[17] -=3D 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); @@ -186,8 +185,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->msr |=3D MSR_EIP; =20 qemu_log_mask(CPU_LOG_INT, - "exception at pc=3D%" PRIx64 " ear=3D%" PRIx64 "= " - "iflags=3D%x\n", + "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", env->pc, env->ear, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &=3D ~(IMM_FLAG | D_FLAG); @@ -224,8 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=3D%" PRIx64 " msr=3D%" PRIx64 " = %x " - "iflags=3D%x\n", + "interrupt at pc=3D%x msr=3D%" PRIx64 " %x iflags= =3D%x\n", env->pc, env->msr, t, env->iflags); =20 env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -242,9 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=3D%" PRIx64 " msr=3D%" PRIx64 " %x " - "iflags=3D%x\n", - env->pc, env->msr, t, env->iflags); + "break at pc=3D%x msr=3D%" PRIx64 " %x iflags=3D= %x\n", + env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->msr |=3D t; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 3f403b567b..6e583d78d9 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -250,8 +250,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) if (rn =3D=3D MMU_R_TLBHI) { if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) qemu_log_mask(LOG_GUEST_ERROR, - "invalidating index %x at pc=3D%" PRIx64 "\n", - i, env->pc); + "invalidating index %x at pc=3D%x\n", + i, env->pc); env->mmu.tids[i] =3D env->mmu.regs[MMU_R_PID] & 0xff; mmu_flush_idx(env, i); } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index ae57d45536..fdf706a723 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -75,12 +75,12 @@ void helper_debug(CPUMBState *env) { int i; =20 - qemu_log("PC=3D%" PRIx64 "\n", env->pc); + qemu_log("PC=3D%08x\n", env->pc); qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); - qemu_log("btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%s) eip= =3D%d ie=3D%d\n", + qemu_log("btaken=3D%d btarget=3D%x mode=3D%s(saved=3D%s) eip=3D%d ie= =3D%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 19d7b8abfd..72783c1d8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -55,7 +55,7 @@ =20 static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; -static TCGv_i64 cpu_pc; +static TCGv_i32 cpu_pc; static TCGv_i64 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; @@ -64,7 +64,7 @@ static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; -static TCGv_i64 env_btarget; +static TCGv_i32 cpu_btarget; static TCGv_i32 env_iflags; static TCGv env_res_addr; static TCGv_i32 env_res_val; @@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *= dc, uint32_t index) TCGv_i32 tmp =3D tcg_const_i32(index); =20 t_sync_flags(dc); - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp =3D DISAS_UPDATE; @@ -142,10 +142,10 @@ static void gen_goto_tb(DisasContext *dc, int n, targ= et_ulong dest) { if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); } else { - tcg_gen_movi_i64(cpu_pc, dest); + tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -509,7 +509,7 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); dc->is_jmp =3D DISAS_UPDATE; return; } @@ -850,7 +850,7 @@ static inline void sync_jmpstate(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); } dc->jmp =3D JMP_INDIRECT; - tcg_gen_movi_i64(env_btarget, dc->jmp_pc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } } =20 @@ -1019,7 +1019,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); =20 tcg_temp_free_i32(t0); @@ -1139,7 +1139,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1187,18 +1187,15 @@ static inline void eval_cc(DisasContext *dc, unsign= ed int cc, } } =20 -static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_= false) +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_= false) { - TCGv_i64 tmp_btaken =3D tcg_temp_new_i64(); - TCGv_i64 tmp_zero =3D tcg_const_i64(0); + TCGv_i32 zero =3D tcg_const_i32(0); =20 - tcg_gen_extu_i32_i64(tmp_btaken, env_btaken); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, - tmp_btaken, tmp_zero, + tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, + env_btaken, zero, pc_true, pc_false); =20 - tcg_temp_free_i64(tmp_btaken); - tcg_temp_free_i64(tmp_zero); + tcg_temp_free_i32(zero); } =20 static void dec_setup_dslot(DisasContext *dc) @@ -1229,14 +1226,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset =3D (int32_t)((int16_t)dc->imm); /* sign-extend. */ =20 - tcg_gen_movi_i64(env_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); dc->jmp =3D JMP_DIRECT_CC; dc->jmp_pc =3D dc->pc + offset; } else { dc->jmp =3D JMP_INDIRECT; - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); } @@ -1277,7 +1272,7 @@ static void dec_br(DisasContext *dc) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i64(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); gen_helper_raise_exception(cpu_env, tmp_hlt); tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); @@ -1303,7 +1298,7 @@ static void dec_br(DisasContext *dc) dc->jmp =3D JMP_INDIRECT; if (abs) { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); + tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && (dc->imm =3D=3D 8 || dc->imm= =3D=3D 0x18)) t_gen_raise_exception(dc, EXCP_BREAK); @@ -1321,9 +1316,7 @@ static void dec_br(DisasContext *dc) dc->jmp_pc =3D dc->pc + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(env_btaken, 1); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } } @@ -1387,7 +1380,6 @@ static inline void do_rte(DisasContext *dc) static void dec_rts(DisasContext *dc) { unsigned int b_bit, i_bit, e_bit; - TCGv_i64 tmp64; =20 i_bit =3D dc->ir & (1 << 21); b_bit =3D dc->ir & (1 << 22); @@ -1413,13 +1405,7 @@ static void dec_rts(DisasContext *dc) =20 dc->jmp =3D JMP_INDIRECT; tcg_gen_movi_i32(env_btaken, 1); - - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc))); - tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]); - tcg_gen_add_i64(env_btarget, env_btarget, tmp64); - tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX); - tcg_temp_free_i64(tmp64); + tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } =20 static int dec_check_fpuv2(DisasContext *dc) @@ -1676,7 +1662,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) =20 #if SIM_COMPAT if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i64(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_debug(); } #endif @@ -1718,10 +1704,9 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb, int max_insns) dc->tb_flags &=3D ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp =3D=3D JMP_INDIRECT) { - TCGv_i64 tmp_pc =3D tcg_const_i64(dc->pc); - eval_cond_jmp(dc, env_btarget, tmp_pc); - tcg_temp_free_i64(tmp_pc); - + TCGv_i32 tmp_pc =3D tcg_const_i32(dc->pc); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); dc->is_jmp =3D DISAS_JUMP; } else if (dc->jmp =3D=3D JMP_DIRECT) { t_sync_flags(dc); @@ -1754,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { dc->is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else npc =3D dc->jmp_pc; @@ -1764,7 +1749,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) if (dc->is_jmp =3D=3D DISAS_NEXT && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { dc->is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); =20 @@ -1772,7 +1757,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); =20 if (dc->is_jmp !=3D DISAS_JUMP) { - tcg_gen_movi_i64(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -1822,7 +1807,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) return; } =20 - qemu_fprintf(f, "IN: PC=3D%" PRIx64 " %s\n", + qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " @@ -1830,8 +1815,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved=3D%= s) " - "eip=3D%d ie=3D%d\n", + qemu_fprintf(f, "btaken=3D%d btarget=3D%x mode=3D%s(saved=3D%s) eip=3D= %d ie=3D%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", @@ -1869,7 +1853,7 @@ void mb_tcg_init(void) env_imm =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); - env_btarget =3D tcg_global_mem_new_i64(cpu_env, + cpu_btarget =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); env_btaken =3D tcg_global_mem_new_i32(cpu_env, @@ -1888,7 +1872,7 @@ void mb_tcg_init(void) } =20 cpu_pc =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear =3D --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389850; cv=none; d=zohomail.com; s=zohoarc; b=mFzgi/r6QVsaCjjysdzb1LQYt3Q6hq0EylydFtWNjgJKkhnOGbhO+B3XcQTSxsR4dhuxTjEGmTg4SCXwRNsOxatSKrxJD56phbimZtemidpAGao77qkHAD23R6e+AqEPCwJ/69R8SbCDY08n9+zLlqbB0zQbBswufr3d2i05awI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389850; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vLvNC5AlBnMMj5Xypoodm2v5NfVH1pHkbk/5dT3fkns=; b=fTKu3Lfm6rywS0ofDYSzKDwRq+D9AsmPo/IRH0MiV+60ttNtZsqrzqwueMotEZmbOQ1TW5b1Xs/aXafmkgJDeUUpgx+CJ1ghNq43jshzuSIP/zIn1RXDiOrhc6HZUhk2Wz2dgfrObYGKBa8QJQTAKHLZJBIuTWBF89vAuQ5mQLM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389850804563.4988697586161; Tue, 25 Aug 2020 14:10:50 -0700 (PDT) Received: from localhost ([::1]:50072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgDR-0005fu-DF for importer@patchew.org; Tue, 25 Aug 2020 17:10:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3C-0007JL-PA for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:14 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:35852) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg39-0001gV-W1 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:14 -0400 Received: by mail-pg1-x541.google.com with SMTP id p37so7680704pgl.3 for ; Tue, 25 Aug 2020 14:00:11 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vLvNC5AlBnMMj5Xypoodm2v5NfVH1pHkbk/5dT3fkns=; b=ecipNhGoBKQ02TFbaj93oCSwUtgmXchdRW+KyRkuqHGEhP+HYSHLrpYoGYpZ8bPWor AaNzAQG+dRa0p3LHKkpzWB7v9GoPRHImvr2F1GlvhIzYS3v9BrnhXnl/dOfuLtU6IJfZ 8BbVdX8OC7PMr0sY1ujrCLu9mrAeNbyobQOldhc0t6u97fx8JgHfWeMzPoWmCBeCF6M1 PRBbc+pZ8HGGaWFcX2Lyid/u+sccwbUCuMVYSUHZwI5ZfAD6cch41X3LOpYXlpL8Tu/w gCpyELHhW725yNXvk9gTWzxVa8gqZMKUcDcZf0Ya9rozm+5INRX1gUByKj7I3NsTZIdV YgUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vLvNC5AlBnMMj5Xypoodm2v5NfVH1pHkbk/5dT3fkns=; b=M7BYj1J9B1kX6N1mb7kAatcaCIWbnQuInwvh/QlF1GU36bP/WZbND/zb3hp0h1k/Kw XH4h5U20GvsPgMQfGki5Mbrk7SuHBwLmFAzlAVlN0NmrlXzqgsVu6QRAiYMM5eESimxb hHXGxjaaD0FmiPMgEYmWaOcv8FHSs3Squiir2EOxPbtM7xqx52HmkJeCZ7BLLd4CRcJ7 q+DmgWDxo7CP5vlMWU/jHhFYe3Lkg+fXj3VS6fhLI85eQ01l1T83fPdKDXy25jOQQIXS xtF2Lz0jXdEQMytAgOvL/SeAnE47C//9HR+WNuCS+3KwTlbsG2PJTg4xAougmjvUTCK/ U/mA== X-Gm-Message-State: AOAM531FTe52uZhDL1Jb0DzRCACuyezN58L+8BGqJmZB2+HcuJRLFrCa dBWiijSTncmLYbafh4Bk1M7aCQ9S0xVGNw== X-Google-Smtp-Source: ABdhPJyuCs2jI9ABs6i8r57lAA98cs5p3ASNH/VqixxhhVuyMa/5AHf9/V9iLUOSD305SyPFAdeR1A== X-Received: by 2002:a17:902:9888:: with SMTP id s8mr9203826plp.111.1598389210032; Tue, 25 Aug 2020 14:00:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/77] target/microblaze: Fix width of MSR Date: Tue, 25 Aug 2020 13:58:47 -0700 Message-Id: <20200825205950.730499-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 38 ++++++++++++----------------------- 4 files changed, 17 insertions(+), 29 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f4c3c09b09..019e5dfa26 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,7 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint64_t msr; + uint32_t msr; uint64_t ear; uint64_t esr; uint64_t fsr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b95617a81a..af79091fd2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=3D%x msr=3D%" PRIx64 " %x iflags= =3D%x\n", + "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x\n", env->pc, env->msr, t, env->iflags); =20 env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); @@ -239,7 +239,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & D_FLAG)); t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, - "break at pc=3D%x msr=3D%" PRIx64 " %x iflags=3D= %x\n", + "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", env->pc, env->msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fdf706a723..a7f6cb71f1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; =20 qemu_log("PC=3D%08x\n", env->pc); - qemu_log("rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx64 " " + qemu_log("rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 72783c1d8a..0e71e7ed01 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,7 +56,7 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; -static TCGv_i64 cpu_msr; +static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i64 cpu_esr; static TCGv_i64 cpu_fsr; @@ -152,8 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) =20 static void read_carry(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); - tcg_gen_shri_i32(d, d, 31); + tcg_gen_shri_i32(d, cpu_msr, 31); } =20 /* @@ -162,12 +161,9 @@ static void read_carry(DisasContext *dc, TCGv_i32 d) */ static void write_carry(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t0, v); /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1); - tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1); - tcg_temp_free_i64(t0); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); + tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); } =20 static void write_carryi(DisasContext *dc, bool carry) @@ -437,21 +433,14 @@ static void dec_xor(DisasContext *dc) =20 static inline void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_extrl_i64_i32(d, cpu_msr); + tcg_gen_mov_i32(d, cpu_msr); } =20 static inline void msr_write(DisasContext *dc, TCGv_i32 v) { - TCGv_i64 t; - - t =3D tcg_temp_new_i64(); dc->cpustate_changed =3D 1; - /* PVR bit is not writable. */ - tcg_gen_extu_i32_i64(t, v); - tcg_gen_andi_i64(t, t, ~MSR_PVR); - tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR); - tcg_gen_or_i64(cpu_msr, cpu_msr, t); - tcg_temp_free_i64(t); + /* PVR bit is not writable, and is never set. */ + tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); } =20 static void dec_msr(DisasContext *dc) @@ -773,8 +762,7 @@ static void dec_bit(DisasContext *dc) t0 =3D tcg_temp_new_i32(); =20 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_extrl_i64_i32(t0, cpu_msr); - tcg_gen_andi_i32(t0, t0, MSR_CC); + tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1326,7 +1314,7 @@ static inline void do_rti(DisasContext *dc) TCGv_i32 t0, t1; t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_ori_i32(t1, t1, MSR_IE); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1344,7 +1332,7 @@ static inline void do_rtb(DisasContext *dc) TCGv_i32 t0, t1; t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_andi_i32(t1, t1, ~MSR_BIP); tcg_gen_shri_i32(t0, t1, 1); tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); @@ -1363,7 +1351,7 @@ static inline void do_rte(DisasContext *dc) t0 =3D tcg_temp_new_i32(); t1 =3D tcg_temp_new_i32(); =20 - tcg_gen_extrl_i64_i32(t1, cpu_msr); + tcg_gen_mov_i32(t1, cpu_msr); tcg_gen_ori_i32(t1, t1, MSR_EE); tcg_gen_andi_i32(t1, t1, ~MSR_EIP); tcg_gen_shri_i32(t0, t1, 1); @@ -1809,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) =20 qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=3D%" PRIx64 " resr=3D%" PRIx64 " rear=3D%" PRIx6= 4 " " + qemu_fprintf(f, "rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1874,7 +1862,7 @@ void mb_tcg_init(void) cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); cpu_ear =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389908; cv=none; d=zohomail.com; s=zohoarc; b=D7KJeLd3Y4+bgoqcwiu/WmqX+6Auscv+9a/BVXCLiLAxYm0KZaLfBypDQf9FFStm6YRE6gFQcACsVLUzHTzn9YVyNqiPztlLdPFGCMO7EUGcbG30R0/aL5qQguTMI0AyQF1dD56XrnSS8h0Xujt+zkpOOCq8jbZXNE9+dg6zieA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389908; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+nsIkr2WvIp6my21gJ25pABEfOsk+UM0/dRmzACDNzE=; b=K6wHwI9OOKLE2O4HOnH6UdJUAi8ehWCjGroGwu7CDdLLiM80Dg4mtSAedJSVB0zezC VgRH2So8yKIA21R7VzN7VNzk2yCmpYW+21HXK/RPY9JTfojWnGvrQn78n+aKA+kolhiU 48DOa1Gpj75m6mDJ9+gPIjmwhpfmxuOlGgsScq2WuexrtlCRRxyXNC71AvEjriSH0/ZA zwxZ8/ecrgowB1INkNGrhsLotmulDYhIFUsMKubCh8eDOYLeDfQdiNLzMMUIR3RQkg0b VvPRR//MJsWeLxA2N2YBfo1yTCGTyUKISIBehA1l7dzGrsINpCuCFcBtg+86TeGdIXLL He5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+nsIkr2WvIp6my21gJ25pABEfOsk+UM0/dRmzACDNzE=; b=uUMBvdGl7DW1fQ7vbezoewnGPq23VDJIYuPiquk+X86ExJmxx1AYPrTbPsDn1S2cyg TOpleWgjj8bLJwBwzRMpHddShjSArGeLjzWpJXhFWbniYajCKvZtyV6h4pwOeH5m7IWW epGiO/UoGoJpUV7KrhjXfP1eIGd30q4kBFbK325f+SAV2hFrOJ1mNxQpYB07dpe8Plsx B/VbfBTa1OFiE+uVnjIClHFGiRfJAu4wGCw8iQs2wNdpwnVRztSzLMMt8ohnxKf7gQvN Dr74vfHBqeWe5d30PnFHlBnKwXsHmYcVAAigNajAJtOCaM/1OmWW7cMSiMLUKxmHWDlz wB3w== X-Gm-Message-State: AOAM533KFc3Hbhz8C30T2c3Kke1NUdA3ChYlU6IKkoAkJ6Yf7SHk/x+d KLQcNhT0GZZDkqS3CgB0d+tMkFcUYyOJKw== X-Google-Smtp-Source: ABdhPJw9r3wzV6gkJU3+haj+A8gqGg8cApnEOwF7JXWuo9uCrPyhg29T9OeiFeSPc0T5piGhjqE84A== X-Received: by 2002:a05:6a00:14d0:: with SMTP id w16mr9327023pfu.39.1598389211180; Tue, 25 Aug 2020 14:00:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/77] target/microblaze: Fix width of ESR Date: Tue, 25 Aug 2020 13:58:48 -0700 Message-Id: <20200825205950.730499-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 16 ++++++++-------- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 019e5dfa26..aaac0c9a6c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -239,7 +239,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; uint64_t ear; - uint64_t esr; + uint32_t esr; uint64_t fsr; uint64_t btr; uint64_t edr; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "= \n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) =20 qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%x ear=3D%" PRIx64 " " - "esr=3D%" PRIx64 " iflags=3D%x\n", + "esr=3D%x iflags=3D%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a7f6cb71f1..dc2bec0c99 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env) int i; =20 qemu_log("PC=3D%08x\n", env->pc); - qemu_log("rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " + qemu_log("rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " "debug[%x] imm=3D%x iflags=3D%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0e71e7ed01..f63aae6de9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,7 +58,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; -static TCGv_i64 cpu_esr; +static TCGv_i32 cpu_esr; static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; @@ -182,7 +182,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP); + tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond; @@ -198,7 +198,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; =20 if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN); + tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return cond_user; @@ -539,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); break; case SR_ESR: - tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]); + tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); @@ -580,7 +580,7 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); @@ -1399,7 +1399,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu !=3D 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU); + tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } return (dc->cpu->cfg.use_fpu =3D=3D 2) ? PVR2_USE_FPU2_MASK : 0; @@ -1797,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) =20 qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=3D%x resr=3D%" PRIx64 " rear=3D%" PRIx64 " " + qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, @@ -1866,7 +1866,7 @@ void mb_tcg_init(void) cpu_ear =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr"); + tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); cpu_fsr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr =3D --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389976; cv=none; d=zohomail.com; s=zohoarc; b=fB1uL08Kvi7snuGvANNmjKbxYZKnP6+9icYdjTYFUcjJNyDY5qM5tq2wj5+5EA6KkpfetYYWbabQ50NtouR+6KBUKDSy3VNE0RRTl7Oid7h8ffHkdAMI2uHWEQ8Ww2Rxn+3X8I/sTQeAOiPM9OVPeOFCexC8TX6eZU1bk9RzrHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389976; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rMh4Sqcir06bVXs74gHMdeUNg4a+HHCVID7KGWDrg3A=; b=g1odbfqa0+q9nGJx4EOMNU0ydqt+dor2x/OjpfsUqnfHm9qK0igIWuPQCrZTp7/p3eDYIp56n++gVCJCHs6XF2Vw5rf4z84OqhlBZEc6bwBd8SsAj7xwhdBbUA3XlO0/Z4fKoYb8ivbKF+Xx8TXOYD4r4YTZ4wx4ZM4agu5Qif8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389976693340.89440259427295; Tue, 25 Aug 2020 14:12:56 -0700 (PDT) Received: from localhost ([::1]:59150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgFT-0000yA-9y for importer@patchew.org; Tue, 25 Aug 2020 17:12:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3F-0007OW-6c for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:17 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:33107) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3C-0001gw-OZ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:16 -0400 Received: by mail-pg1-x543.google.com with SMTP id o13so7688800pgf.0 for ; Tue, 25 Aug 2020 14:00:14 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rMh4Sqcir06bVXs74gHMdeUNg4a+HHCVID7KGWDrg3A=; b=pLeGcz39VQ2b4YB7GhbRNmfrp8ZshjAHxpsJAi3TKvDx5mX+YuHdarLDS9gIsv/sxi 3fJYgbkzWbQYgfaRtPCcm1+taontYWQY3lp3Ciw2/N9GPWu51+JaVLVOqso9GqAMvpaT IsgNHN61Oh9WOBGhN3Oqfkod9DDsLACn7u4p//HC6B59Cw+UvFEGue8B5rxLZFVjbtDc UhUBWHlFc8Aose560U9udDL94QTStqVVWUoMp92xUxykDHZvWAnt1MK3Tu1KuW6l7IfG ErcVlTqE2QwZpwnCMuzLxLjxGxOOvNc3QdK7l2QwZ1rsLKehkV9ak1WKQRwJlpMQ5mH5 x4lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rMh4Sqcir06bVXs74gHMdeUNg4a+HHCVID7KGWDrg3A=; b=LWHKvs0W96QUu3a9qK2VGAUt+/tnPNH4pN8TzR3msaCpTXe7h29yREuPcIcbYJ9fzN zNVB/h4S7P/mSKgm1R2hp5krQcf9d2iWgidU0uF7RPDJlbkUaKiSHwp36t60Z+XymIK8 66L2+x2xOjtPUupd+8q2l6ncFeG7P3PQSTJO4miYMo4Q90XSNVzt4zOIboqsVbCYAC3y ZwFXs7ep99kf8k83PBuTkyjoQwm/XAqQdKu9M9TUpmbjawX2vDaP5MYRgQISloD1QaF6 lwiqNrnv4mLpyhHEreh5ylnXFu+8BHILDngiVEpQkbRDcpSb8NO6CLyEjJ6fXghhZfG/ vqFg== X-Gm-Message-State: AOAM531mbRgCMrf8Ld1NlgvsdtxVp0uZfy3D31ytFHGKFcVuGs9aIac9 05CBou7N0tZL7+hZF4Z0RtrzqWv7yXbscg== X-Google-Smtp-Source: ABdhPJwQfSmOTc87ZFy2jjnDiDsKnD6jMgFr5+ddYoRPEWZNN3gXdlXodjX5PITbaiq1zqGkfYHyrw== X-Received: by 2002:aa7:96c8:: with SMTP id h8mr6386665pfq.108.1598389212946; Tue, 25 Aug 2020 14:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/77] target/microblaze: Fix width of FSR Date: Tue, 25 Aug 2020 13:58:49 -0700 Message-Id: <20200825205950.730499-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index aaac0c9a6c..34177f9b28 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -240,7 +240,7 @@ struct CPUMBState { uint32_t msr; uint64_t ear; uint32_t esr; - uint64_t fsr; + uint32_t fsr; uint64_t btr; uint64_t edr; float_status fp_status; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f63aae6de9..3fc2feda3d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_fsr; static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; @@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); break; case SR_FSR: - tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); @@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc) tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); break; case SR_FSR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); @@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " - "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " + "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%x " "rbtr=3D%" PRIx64 "\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, @@ -1867,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_fsr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_btr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr =3D --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390036; cv=none; d=zohomail.com; s=zohoarc; b=C9135GXeOLSoj1HdD+7hrSqpX7GlsDdDV2I2BoFatDjjU/KyP1l3d3tNQkj58MK+QwL3ccfXUNBLWhdToBRUt4y408q51XOS1fpD1f+EAnqSn/Ve10Q78s36Micm+iw8lGW/7wdWFeAo/X9rXNvYvFb8EFyDs5fssAZWuPkOjs0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390036; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=IIdGPIUKyx+haK+nXvW2lBcmJaDOrDq+B8kEwTezP2zKRqAMh2QWxruWX6He7r4Tq9uX7UyvVL3+AqCKUofXS96/dgTg0hvBWVr+Fj6QqFUNWwN7idffavk2dmtUJ7m3QK8Qfs+fGu4i5aJuqatCEr+rY1ZpPKkm24oGOff5Keg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390036269439.35779498478587; Tue, 25 Aug 2020 14:13:56 -0700 (PDT) Received: from localhost ([::1]:34380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgGR-0002Lz-1r for importer@patchew.org; Tue, 25 Aug 2020 17:13:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3G-0007Rd-N6 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:18 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:39048) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3D-0001hE-Mq for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:18 -0400 Received: by mail-pj1-x1043.google.com with SMTP id j13so119248pjd.4 for ; Tue, 25 Aug 2020 14:00:15 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=JoxIZUUZWi/kyFj8rG/GieKFHcSqVpadpupd+vXYjFjgJ7oD9HzJq9O4A6sVbmikwU K9IfJ/E6Q5bjZM22hHkOTVBggJfkJufWLaGGKa1OVSmxmnZrXdx7rV3Ug0pV1RDIZiUG TRm5Xqgy4+A77PZkh5EzFlyvs3DCWf/41iMyS3E61GJYtJYAmt6DNTMVAy97YC+BY7qP haXHAuuuS4N1qGTlmT9SpN4w4t/DfkG0zigGXZrxKsT5nYBy5w3wNyDZIYreRzvOLW6N /DE4S4gF81G1gcmDTfNwIBNsSQunE/LsePwT8wPT3LDIjrN7NGvuG6PikdrChiSRuABo SEjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AF5wUNj1rfWDk74W8hKW9/y1FLbHGsX9t+9rRKYsDAE=; b=m4+NBinIrgDtlUzJhJ38+IrBxdYu1cJ+aShjvxWroiay+IGHEZ/xFGysApwS5NlWb4 1/IBOsUtR2P1hooupgUoZQIILGgB7IDirxQzjQ4EQ91tfdpDE+CEhL8O8tEjVtbZn0lx OVSF51yQ8BQxFr2hDWH6pccg298wAhyS89mTuX2kZDcRNG7QYnXz9D4w0IrPxYYwmtVE 6tJtDynuMB9G0jY5c/RdvG8a7wKxfpvONQKgDlIyUWuBDYFYjjaWVCHXyaj/FJrEYOGB igWHuqsulPY3OHSYX1pdkJx6gRvkKLwo+i5FyrBWz0S4ml07ttqHsz5nVKxjKPO5vvIP PPjg== X-Gm-Message-State: AOAM532hhHWJFvCc6EA9YpwjUyiaOgsR2FVQNoq1dafw2euBLmhYrkBe 3cwDHx4fMSlaoyKyuH7RkdM5kB/BIRTWyw== X-Google-Smtp-Source: ABdhPJx5NJSADve+SF/vMsZcz0coY3c4ey5dkWOsibQinB76dvBEhX9rPzi3gX33pkqPg8YAenNPag== X-Received: by 2002:a17:90a:fd82:: with SMTP id cx2mr3098541pjb.20.1598389213985; Tue, 25 Aug 2020 14:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/77] target/microblaze: Fix width of BTR Date: Tue, 25 Aug 2020 13:58:50 -0700 Message-Id: <20200825205950.730499-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9b28..72f068a5fd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3fc2feda3d..a2bba0fe61 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_btr; static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); @@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); @@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " - "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%x " - "rbtr=3D%" PRIx64 "\n", + "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%x rbtr=3D%x\n", env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags, env->fsr, env->btr); @@ -1868,8 +1868,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_btr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); cpu_edr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390107; cv=none; d=zohomail.com; s=zohoarc; b=ZBOnlXUtIbtM5DvWFdkjD/RhCfKPYPYadFCspsn0W9QET9FPd+L1XqF3OXajunjA6mg/sp7m2jZ6JcD8OwPMR0BKGj1cQaE8qY6SvFRlAvD+GO6Au9jMKoKBexhsZZJp7KlF7wZjqaUz5OpmpGkqFWYeJlLOdBukNRvf/co6akE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390107; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=B46Gga+JGf7OqhbIR/RTdTVS4uxMqi++a/joaWq/SkmF0TrO0Y9da8SdOv9JqlC6Z8PKKVzcTv8pq2u6srKr2Ja39IoCAul6wBOd6rYf4aCzmbCnMGsSqNfJjikMfcAgYO15lXVRgOp2mt1ZKlIS9cDICgia74CoDXzKAARfSbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390107570394.95941540914396; Tue, 25 Aug 2020 14:15:07 -0700 (PDT) Received: from localhost ([::1]:39198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgHa-0004HM-AZ for importer@patchew.org; Tue, 25 Aug 2020 17:15:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3H-0007Sh-5P for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:19 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:53401) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3E-0001hZ-SS for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:18 -0400 Received: by mail-pj1-x1044.google.com with SMTP id nv17so121915pjb.3 for ; Tue, 25 Aug 2020 14:00:16 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=QCFFwNNodSFcQsaP163bMmLe8rGKMi/YtW2jQIx8KfyesacWpCMp2g/90lF/URT5Yg JYFY6bOdUWSWZxWWElEtexGgxuodmct9tXh89NFWAblhU8Yz6B0tV8lzEpG656E7KwaG wuM17xlWH58h2s2wHlohZQ9ZuArGSj7bqAGCO8JXGIN5HdYjxs4iruVzMvPMLN6UNhmc HGhymZSzs0wlDaDAfrt/JZjrbLxVAOA5v3peWoISUGojIfnm6uzQ2btbdCUoXeRMjotr rHPWBYziOQ23s79afH4EM/8qW6EjoDPShYKpaPbvGT/8C5oDJJ8JvA81iYTQbtbSnFsM mt6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZaIdcAkOSjEufmU2G8vkTG/fvmG7Z2otY+gyeoJlJtY=; b=iT9PCMT+KeB+LeMdtIvkC7IZynDqpzCwSH3XmfSUlJ/pwOd+7uoweqPLa+ueCttuP0 Ux6HpZNNpdrBXL7xavLsTOKOS/zFzss0v9HhPQuIiVnzGTpgzMIJ/96q3owu6gOXjd9h 6nEvakz9yOryyC7qJMpts5PwoWwQCEgiOigSPPiUzfmg+shL2c+w/Vyxa12Jfk5fSfnD WHWjRJntUKmo+28VkWVfLdhubGIaL8UF6KA2XvQRsXmbQHFQ/PhVFebZZUE9UYEtz/dU MUk64hCxtCtCiC8I4ilC1Idb26jCfIwmJGP1O8MZBmfga6fcaOIH6/FbEZYeOwdOZoib Cing== X-Gm-Message-State: AOAM532NVw3dTsroB4t/9QwRm8uPsnS/YlGyFt5FgitHbdk0UokCQ00W F1EjrYNCxLfN5f1JDq+vmdx7JFb9UXktXQ== X-Google-Smtp-Source: ABdhPJwUXv3iyhh9K5h9YxDx2yTlUJ2zQf5j/yInEWN90XJahDIrsYvdIFwzU741weSdCxmroEpgFg== X-Received: by 2002:a17:90a:ead1:: with SMTP id ev17mr3093171pjb.147.1598389215137; Tue, 25 Aug 2020 14:00:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 18/77] target/microblaze: Fix width of EDR Date: Tue, 25 Aug 2020 13:58:51 -0700 Message-Id: <20200825205950.730499-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 11 +++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 72f068a5fd..b88acba12b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t esr; uint32_t fsr; uint32_t btr; - uint64_t edr; + uint32_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a2bba0fe61..a862ac4055 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; -static TCGv_i64 cpu_edr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -548,7 +547,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], @@ -591,7 +591,8 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, edr)); break; case 0x800: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1818,7 +1819,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) } =20 /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=3D%" PRIx64 " rpid=3D0 rzpr=3D0 rtlbx=3D0 rtlbsx= =3D0 " + qemu_fprintf(f, "redr=3D%x rpid=3D0 rzpr=3D0 rtlbx=3D0 rtlbsx=3D0 " "rtlblo=3D0 rtlbhi=3D0\n", env->edr); qemu_fprintf(f, "slr=3D%x shr=3D%x\n", env->slr, env->shr); for (i =3D 0; i < 32; i++) { @@ -1868,8 +1869,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); - cpu_edr =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } =20 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389967; cv=none; d=zohomail.com; s=zohoarc; b=fOVDeLFciM3Ytj6z9jcfn4iJHCxdL6x7pIEpzkkWHPDPrMBJ9f7a86zzyjW+SuFW75jC9K+D70F4ZHQWm5n1bF19IC4g/JC9UctrJnVIqXTiDL0alHu5eKiuvp002NoOU2y8iNDq3u7wllVXIpwBxFTgpXS9Y20En3dTFL2hQJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389967; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HaAnpocjYbBqDikM80fgZOEo5h0cDqsU8in/f2nqeSk=; b=Ut1eVEoFHm96BmOx9JwXqvVll7ggBSO/ciuB6xYLNDdJx7+DCY/IkBPulVGI/8yonESHE9Y4Rm7FsgUGFvTWqgAUHSypZaN0NYwROpjy/GUOOMX+p8DBj9L3UCnFdGrL/F9LnpFP+qz0Q61kLfFViYdrg2zNY40WGZeZioNocZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389967213678.6617366297088; Tue, 25 Aug 2020 14:12:47 -0700 (PDT) Received: from localhost ([::1]:58542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgFJ-0000jP-K9 for importer@patchew.org; Tue, 25 Aug 2020 17:12:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3I-0007VH-F4 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:20 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:36389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3G-0001hs-Fo for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:20 -0400 Received: by mail-pj1-x1042.google.com with SMTP id q1so127248pjd.1 for ; Tue, 25 Aug 2020 14:00:17 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HaAnpocjYbBqDikM80fgZOEo5h0cDqsU8in/f2nqeSk=; b=k9kjF86s31Ab6Xxn5y1ioVUgfUNO5Z9DQhb3bZ6qS/8aB+TXe5RxE228zFX0joYqry jCpmGE/9BGjfUK8/lMe6cbl6DSHt7tW7Ba/y+7Whcnc8X9kQQJtIwwb9N+5whq94TFp1 9okqSRW8nDo8nwAxwMfj/Y3n2RDxQ+E/6wkeA7hvsAAzcqf8uoXKFLCc6bSI06gX722u mO43Pe+X5aVDiGA8a9oc1212zKtcNTE7Ihfg0v9yAtJhn+Ajt+3FFa3Kos0xoE8gwtNU b7sDdPATD63oLz5ONAvHmqYvZa16II4x50z10FVjg0NxDIpAxe90jXM8twXtIqUu5J0f gXzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HaAnpocjYbBqDikM80fgZOEo5h0cDqsU8in/f2nqeSk=; b=c+fvWZ2c8jAb+hbxtQpc7MgCoCXIB7FCO1LWZDYrTKLqM/uZCLOGRvicgA+N2n08cV 6w2FUjjnJpLoGgL+Z30pNj55EkydPElfqm/NSxpr5liBA9LPIVY8InX1ZzntmAHtFc8o 4Q2dlK+wIn2HJWDFj26hnwDZeVsG6yaeFzC8sZpuDOJwoLzecxuTk2ulUlZsGF6iTlRb V4s42l11XA5r1IMILo1H32Fb+0YKUIYgPzgYu+/lOFkSec0CUA/M3uqZhGO7sfkTq8bF EDReEnf5Ldl0P6Tc0gqnhrftwj71Z2T/hwzCsLLyFZ2hEhCM2yQWU8v4wdiCS/LA/C3M Izhg== X-Gm-Message-State: AOAM5303uNH6CQZKEc9XKcvRAjASYSogvf3Ay3vA8m6dpNxPV6VIA0Tl kyhnfh5z8vJs8le0m62hTk8qD4y+2EeIEg== X-Google-Smtp-Source: ABdhPJwXOwt3xJDrUSYFVwhpnGaIl117Xi+uhbnoeT/eJDn6/bomr/cF6n2Ylq9J5d2Qv9jy0spGfA== X-Received: by 2002:a17:90b:1895:: with SMTP id mn21mr3146401pjb.173.1598389216498; Tue, 25 Aug 2020 14:00:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/77] target/microblaze: Remove cpu_ear Date: Tue, 25 Aug 2020 13:58:52 -0700 Message-Id: <20200825205950.730499-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a862ac4055..f5ca25cead 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i64 cpu_ear; static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; @@ -533,7 +532,12 @@ static void dec_msr(DisasContext *dc) msr_write(dc, cpu_R[dc->ra]); break; case SR_EAR: - tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); + { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)= ); + tcg_temp_free_i64(t64); + } break; case SR_ESR: tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); @@ -573,10 +577,15 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); + { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)= ); + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); + } else { + tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); + } + tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1865,8 +1874,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_ear =3D - tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); cpu_esr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390094; cv=none; d=zohomail.com; s=zohoarc; b=W0qAZmooNBWmbid+tCXWT3S3FQYH7GD2YBJQOtPb6M2bSXyQm7oE9UjgEIjJmmxVCnBlLqstdEEpOjVU+pCVhwF8hMnvG2OtnpbsTK7YjPU7R41xG4/lTYE2SlGvLG0bHe2gdxv+so2WWbb7x0anEyT44JaZU0DbdNZ5gmAUadY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390094; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z4AmITk5w2LQx1h3BHbpZiArbCayMAaSAdvlTGNWCzo=; b=dyE2biAGYa7YfEj+f7VHzDG6F3d2a+dDG4wLjdTQkRuVF4p67+dEUzY36+i8j1lRADjNCdohk1uDfOaBwNb3Yb1Lvc+fGbDjZR2HFcsblYUdGUi0TT1IjIQLpmLfEqQe9VeJNCYP5wTb14Oojv84wStCO5BLOZM78fgpGAdH1P0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390094327395.781102094945; Tue, 25 Aug 2020 14:14:54 -0700 (PDT) Received: from localhost ([::1]:38688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgHN-00045C-2r for importer@patchew.org; Tue, 25 Aug 2020 17:14:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3J-0007Y2-PS for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:21 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42051) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3H-0001i6-Gi for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:21 -0400 Received: by mail-pg1-x543.google.com with SMTP id g1so3877669pgm.9 for ; Tue, 25 Aug 2020 14:00:18 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z4AmITk5w2LQx1h3BHbpZiArbCayMAaSAdvlTGNWCzo=; b=yNqdK3Wk3d6p9u/Kck72abkbV6JvNTxoax6CiVyS7o9qRdRbDATlM826k3bs0LUwh5 /SYUwKXovfc8xFnrvuzq/9V/aPIX3QyE+3W1T46Ux6BE6INv2A3cx9QXYheFzTkGGENg VOcjAgVcc1YnQeg9Eq3sXzkcCkf5NNpnAsmQlSaW/1w/mR59qnsGgRWpJblh8xAHm64Y +hITm0sJRv42MwMG00mae32LrTtbkl8xZBj3PNA52//dTFbUD5INrLwmSO69bKeeMJbj tUKb6h18x5GPazHnc1NLHEsF2ojTH8fRvAkMY4zfFj2vHflLigo0iNpK6bqjoAFlUoil tnsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z4AmITk5w2LQx1h3BHbpZiArbCayMAaSAdvlTGNWCzo=; b=D3uQ8fTeh9NG8gvmRrMPeJ32HpbRHkjoIKxbWcRbD45Rym4cZ40wLLJEVV3cnA+uo6 /uIZcA9NTQtl6PkPL0XLnf6gU+zMfu+Wtg/fCyeG6YQSxWyuGgKCER4qBje9YsKPn+ZW i/uz8EsbByA+eWTXySsS8FuDoHaoDs/m0/N22YAzliVAcPWfdDmjbWfk43Iymp2SqQX4 ErJbxtj9OHoBVob+wA4CG3vHcDlDeYCAdD9v7ndCYNJVILPSeNMhZG2MDOMGgOLOAzUf 5vm9Xh11BOz0jWmNqzIrn2OFUGuzXxwCl+6jt8gX/VtIT92Sw3reg/jg42qrZh9Vdu94 2u7Q== X-Gm-Message-State: AOAM533YELu2Ks/y49qMMC1iOrkY/vLNqWjY2OgTnOaMzB80A4S3OCZN rMD5pLuYIAiKOpNnk+oM4GNKmk2fKbbh6g== X-Google-Smtp-Source: ABdhPJyu6iY/48roUr3V09LM5aYGVyuw+2ujTQY5XphbbbFkpuxHsFWgVvYS+4ZOu9sD2vsIR4NAIg== X-Received: by 2002:aa7:84d4:: with SMTP id x20mr9055319pfn.96.1598389217721; Tue, 25 Aug 2020 14:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/77] target/microblaze: Tidy raising of exceptions Date: Tue, 25 Aug 2020 13:58:53 -0700 Message-Id: <20200825205950.730499-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f5ca25cead..9a00a78b8a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -57,7 +57,6 @@ static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 cpu_esr; static TCGv_i32 env_imm; static TCGv_i32 env_btaken; static TCGv_i32 cpu_btarget; @@ -114,17 +113,31 @@ static inline void t_sync_flags(DisasContext *dc) } } =20 -static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) +static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp =3D tcg_const_i32(index); =20 - t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->is_jmp =3D DISAS_UPDATE; } =20 +static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) +{ + t_sync_flags(dc); + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_raise_exception(dc, index); +} + +static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) +{ + TCGv_i32 tmp =3D tcg_const_i32(esr_ec); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); + tcg_temp_free_i32(tmp); + + gen_raise_exception_sync(dc, EXCP_HW_EXCP); +} + static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -178,8 +191,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) && dc->cpu->cfg.illegal_opcode_exception) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } return cond; } @@ -194,8 +206,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; =20 if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; } @@ -540,7 +551,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); + tcg_gen_st_i32(cpu_R[dc->ra], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_st_i32(cpu_R[dc->ra], @@ -589,7 +601,8 @@ static void dec_msr(DisasContext *dc) } break; case SR_ESR: - tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); + tcg_gen_ld_i32(cpu_R[dc->rd], + cpu_env, offsetof(CPUMBState, esr)); break; case SR_FSR: tcg_gen_ld_i32(cpu_R[dc->rd], @@ -1258,8 +1271,7 @@ static void dec_br(DisasContext *dc) =20 /* mbar IMM & 16 decodes to sleep. */ if (mbar_imm & 16) { - TCGv_i32 tmp_hlt =3D tcg_const_i32(EXCP_HLT); - TCGv_i32 tmp_1 =3D tcg_const_i32(1); + TCGv_i32 tmp_1; =20 LOG_DIS("sleep\n"); =20 @@ -1269,13 +1281,16 @@ static void dec_br(DisasContext *dc) } =20 t_sync_flags(dc); + + tmp_1 =3D tcg_const_i32(1); tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - gen_helper_raise_exception(cpu_env, tmp_hlt); - tcg_temp_free_i32(tmp_hlt); tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + + gen_raise_exception(dc, EXCP_HLT); return; } /* Break the TB. */ @@ -1300,14 +1315,15 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(env_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && (dc->imm =3D=3D 8 || dc->imm= =3D=3D 0x18)) - t_gen_raise_exception(dc, EXCP_BREAK); + if (!(dc->tb_flags & IMM_FLAG) && + (dc->imm =3D=3D 8 || dc->imm =3D=3D 0x18)) { + gen_raise_exception_sync(dc, EXCP_BREAK); + } if (dc->imm =3D=3D 0) { if (trap_userspace(dc, true)) { return; } - - t_gen_raise_exception(dc, EXCP_DEBUG); + gen_raise_exception_sync(dc, EXCP_DEBUG); } } } else { @@ -1411,8 +1427,7 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { if ((dc->cpu->cfg.use_fpu !=3D 2) && (dc->tb_flags & MSR_EE_FLAG)) { - tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); - t_gen_raise_exception(dc, EXCP_HW_EXCP); + gen_raise_hw_excp(dc, ESR_EC_FPU); } return (dc->cpu->cfg.use_fpu =3D=3D 2) ? PVR2_USE_FPU2_MASK : 0; } @@ -1668,8 +1683,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) #endif =20 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - t_gen_raise_exception(dc, EXCP_DEBUG); - dc->is_jmp =3D DISAS_UPDATE; + gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1874,8 +1888,6 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); cpu_msr =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); - cpu_esr =3D - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); } =20 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390218; cv=none; d=zohomail.com; s=zohoarc; b=fNEVcdnsuN2/QmWRtZ2TpuDap+u5ZBuxWxzJXfRgfd4ANJFY3wznSvc0ipU0mEmmJplfiDN/SE/WjWJi8AOXHPOTpDlLFkN172KYh/1TmM44DTcc6iu8U1QHItat0NpsLsTVUAIFS81M10bXzmbs04vXpXVIm58KSS+tImV1Djw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390218; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=45kd/bFobWQBgRWzCCV4KKe4PH1pZqfnSM8e41v0zaE=; b=DauJfWo6TQ//k0087EOx6qPx7uGyR9rLjjdRLVztPc4qLZS11WRUF6WhO1youco0f+7tdEh79e9FsGNjwvBcqYylYyOPpReWtTjtKStHUykyy0+JuO2Cca4tuUipfx4448tH7u+R6w4CRWk5OsY4+IrTSkR0Q3IznR5kSKu5GWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390218356825.785923581583; Tue, 25 Aug 2020 14:16:58 -0700 (PDT) Received: from localhost ([::1]:46966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgJN-0007TW-2n for importer@patchew.org; Tue, 25 Aug 2020 17:16:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3K-0007aY-Sj for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:22 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:33115) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3J-0001iM-0r for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:22 -0400 Received: by mail-pf1-x430.google.com with SMTP id u20so8301534pfn.0 for ; Tue, 25 Aug 2020 14:00:20 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This will allow tcg to remove any dead code that might follow an exception. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 2f8bdea22b..820711366d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,4 +1,4 @@ -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390158; cv=none; d=zohomail.com; s=zohoarc; b=k6LTmjyCyXLDol+HBE0Foueeva+xX0ZgOpBvw4qV4C2aHiWjfqRfCEQYoq4i76t2U3PYUQLCxEWTAK78M6t4MCHtP464rrtAizMEvYYjvY7pfw4KGLL9niEiub9Ft3B6mzJRV51W2J29g8BHf86AYIEtYedlIC9Ty5E6A/UzFOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390158; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=RmHHxl2j0wNlQTD8F8Zp14DvISVCtuMFEwwpekVCsAhaPYh/7iET8nzR6wHAyN622AIgpCEwdPmS8QFs5Aw8r6LchyXeEEE1fbdvaLO+QQTPBGYa2huB3ETQy08z8v7V4Th45A9xc7onOKCqAr2bXbx3EifVx4lZo/RgVV+1QY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390158976864.362209788931; Tue, 25 Aug 2020 14:15:58 -0700 (PDT) Received: from localhost ([::1]:42728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgIP-0005n2-M8 for importer@patchew.org; Tue, 25 Aug 2020 17:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3O-0007cB-Qv for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:26 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:54324) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3K-0001iW-It for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:25 -0400 Received: by mail-pj1-x1041.google.com with SMTP id mt12so119517pjb.4 for ; Tue, 25 Aug 2020 14:00:21 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=vobbvPS8Lr8CuEEcFozCZKfdB0nFRULGiyoAIkT2Ccu0Ca3mOrZ8F9XzOfTa6hFxNN +uqkHKb4BKBk9ebjE0opYYWH3NrMRLN0XEAF22dURu8xC8fR2JLgMvpfp/dkm7wJcisq +jiI1qVXxyKPWRPYqWSr6Rzi6O/hyK/VHSwWYMD4pP7qYOo9m8O9uiy3Vf8lpxgSqV2O kXynAbDB9dTaY9Bf+BUMec+FPeEx1sTMqnQeYjY672I6fiDRg0kv7Ai75XBSY0GgFFnm JoqKc2dqecsLhdLarCrHMkKC3b3zdYSpqvqdVnO2NiN0r8IfPXtDrB5SYg1upuIiFGrO wIEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lL2TV9fvxAuHwerQiahLV44CD3Djc67HSq2e2+fPjhU=; b=YqgMFpIFiLDlszHAZfv4GOejKiNoZZDVASjxIkjI6BKO6/AZwM1aJ4Zzo3aB2JNoQ4 oD4QNsEO0lZgsCXIwXcfPuyymj61OEMsitVrCj3DWRBsPMhHljw989eIfPPYjWDmZ+fX rw9fqc3HMotw4Aq/7Kc6/kXQ3WffK1z+Ql877ngwNZKLJ4HVsMDTf5oS+w/1jfNo2SE9 L4JNNqhKmGEtXsuHDrit8vd7yCWCS9yGohx/K9lmIhXplxqj1wQQGYNWqFMuiEQ1rPQp 093gs9v2UUBCyimL+e0KirQxn1f+4smyo6Ze8JucYUIu6BATdPZsU8lj3i+HPdt5SB3n 2NTg== X-Gm-Message-State: AOAM532yH7tmJ+Yo5ShhgxTxn4mmm5rLS3wP2KHQRsX0K2BJFXmZFibK EJ0Lr22y4wQfrJc5OhbLAJM1trp+OryeAw== X-Google-Smtp-Source: ABdhPJxLwHZKodMPz4KsyvNNxODqt7+U8jKrCxlOze4y/mVT02JeAYIItC2wxXirotz7JIhV3LuZ9A== X-Received: by 2002:a17:90a:d34b:: with SMTP id i11mr3104435pjx.125.1598389220666; Tue, 25 Aug 2020 14:00:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/77] target/microblaze: Remove helper_debug and env->debug Date: Tue, 25 Aug 2020 13:58:55 -0700 Message-Id: <20200825205950.730499-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is not used, and seems redundant with -d cpu. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 1 - target/microblaze/helper.h | 1 - target/microblaze/op_helper.c | 23 ----------------------- target/microblaze/translate.c | 16 ++-------------- 4 files changed, 2 insertions(+), 39 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b88acba12b..7708c9a3d3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -229,7 +229,6 @@ typedef struct CPUMBState CPUMBState; #define STREAM_NONBLOCK (1 << 4) =20 struct CPUMBState { - uint32_t debug; uint32_t btaken; uint32_t btarget; uint32_t bimm; diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 820711366d..9309142f8d 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index dc2bec0c99..d79202c3f8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -71,29 +71,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t in= dex) cpu_loop_exit(cs); } =20 -void helper_debug(CPUMBState *env) -{ - int i; - - qemu_log("PC=3D%08x\n", env->pc); - qemu_log("rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " - "debug[%x] imm=3D%x iflags=3D%x\n", - env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags); - qemu_log("btaken=3D%d btarget=3D%x mode=3D%s(saved=3D%s) eip=3D%d ie= =3D%d\n", - env->btaken, env->btarget, - (env->msr & MSR_UM) ? "user" : "kernel", - (env->msr & MSR_UMS) ? "user" : "kernel", - (bool)(env->msr & MSR_EIP), - (bool)(env->msr & MSR_IE)); - for (i =3D 0; i < 32; i++) { - qemu_log("r%2.2d=3D%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 =3D=3D 0) - qemu_log("\n"); - } - qemu_log("\n\n"); -} - static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) { uint32_t cout =3D 0; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9a00a78b8a..ecfa6b86a4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 -static TCGv_i32 env_debug; static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; @@ -1675,13 +1674,6 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb, int max_insns) tcg_gen_insn_start(dc->pc); num_insns++; =20 -#if SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_debug(); - } -#endif - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in @@ -1824,10 +1816,9 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " - "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%x rbtr=3D%x\n", + "imm=3D%x iflags=3D%x fsr=3D%x rbtr=3D%x\n", env->msr, env->esr, env->ear, - env->debug, env->imm, env->iflags, env->fsr, - env->btr); + env->imm, env->iflags, env->fsr, env->btr); qemu_fprintf(f, "btaken=3D%d btarget=3D%x mode=3D%s(saved=3D%s) eip=3D= %d ie=3D%d\n", env->btaken, env->btarget, (env->msr & MSR_UM) ? "user" : "kernel", @@ -1857,9 +1848,6 @@ void mb_tcg_init(void) { int i; =20 - env_debug =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, debug), - "debug0"); env_iflags =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390272; cv=none; d=zohomail.com; s=zohoarc; b=f2HErAa6zciCSpN8Pz/dgQkqw5fM/YbZdmcOXHZ/Vik9jeFPsAAN+1X1+hgH3dPayfDgV6YC5d9sUmYAd4Ud+uy2/9EuEROl0SxMkIunIA4CSEeRdB2vyiBBOeToG9ZTg2dpKM3ZSSv7R9+plyTydUnbFiyeF5sOy2z2x1MsOvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390272; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xvkn3g2mPXtRTX9S6LWMZSG9zfZ6Smrj8vu/NEKgNeA=; b=GDlAyxMelzIQZ2Usz/G046Pgx1nuEB3D2smzSmwz64gEf0YzGOuQFOW7EtnVO8aCqd0G3uBJMYGkF9e39qQEF3zlieVtzuI/MD4QyJRtM8+zfKqCcs7rr4RwersZ5z/sn4pchjo2aVgekMp3bUatcIFB50QrpLMM41t60etKio8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390272257492.27648207364075; Tue, 25 Aug 2020 14:17:52 -0700 (PDT) Received: from localhost ([::1]:51034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgKE-0000gN-Te for importer@patchew.org; Tue, 25 Aug 2020 17:17:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3O-0007cK-Tr for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:26 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:40286) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3L-0001j0-Qa for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:26 -0400 Received: by mail-pf1-x444.google.com with SMTP id k18so8289548pfp.7 for ; Tue, 25 Aug 2020 14:00:23 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xvkn3g2mPXtRTX9S6LWMZSG9zfZ6Smrj8vu/NEKgNeA=; b=U07UN401s5r1Gj1l4xopewFTPFsRvbi9caHmUFnrm3JzK9Zch3+F+nBlciPlsN2m7a hyt5KgLSlNKhx/uCoc2miczrq+C1q/DFx4OKPL39QpUHsy5SZnxfelS0ZrC64F5i4nPB BXn4jAjj1tddigM9FMAO5IEJrgJDxcQOxd+I4ijnxdpQoJFaNuy8H5y/lfRANISRYWoK P21rrjBSgKI9EwZUPgySTR0Ob9XZ2T7xL5aKzzPXLDWlaHKvMuclWKVtTsKzlfbYrfHE pC6+P4ge41WSuWPcWurnv72F8ifZAz6bIsdD77nijxGhKfWoRhcDph2VO87Z8VKTX1YT 7C2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xvkn3g2mPXtRTX9S6LWMZSG9zfZ6Smrj8vu/NEKgNeA=; b=kmU67Pm3B3hNxsMvsYt4ubXU9cUGQM9ISucqFZyUe0j9d+uFfYnEjlDL2mMrSGW6Cn gzCJJhTiusCVJYMDA7z0gg7wosXGJtngjnMM3czIDYwGnq1HT8K+jwwG1aLPzvF5SiXQ BVFS4FmrwSInMZZJTHiCdEKuN9DvOo0n85JBCemO8Fj90IDxEhLnZYPvvHDDwy9rQEX/ cSeqzvhpSh+uSxE7pTRexkD7zUrxaHRT1dA1QWgOlvQqNLa1nnQETooyelhWOCAptmjr pVtH9GX7BARo8MWgEpVUrv4rDkuPTUGft+S2EkpaYwWPT5SNW4ykZ/x8loAJ1JEeH20/ yCOQ== X-Gm-Message-State: AOAM532qqMZ/0bR7/gVdXiMAa1AJKDbkWmTXz6I2uSqysT5+JcKj832s z0S9lNFGCCiNbN7tKTCPjWF+BBKej5zAkQ== X-Google-Smtp-Source: ABdhPJzMTFpCAxGT03BtR1BSQpS98vLvhuSwowONo7Tt7XgMgLmLCcIzZLN7kp0R0QYJbsSgbSyaqw== X-Received: by 2002:a17:902:b28b:: with SMTP id u11mr469785plr.117.1598389222114; Tue, 25 Aug 2020 14:00:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/77] target/microblaze: Rename env_* tcg variables to cpu_* Date: Tue, 25 Aug 2020 13:58:56 -0700 Message-Id: <20200825205950.730499-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ecfa6b86a4..9aa63ddcc5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,12 +56,12 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; -static TCGv_i32 env_imm; -static TCGv_i32 env_btaken; +static TCGv_i32 cpu_imm; +static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; -static TCGv_i32 env_iflags; -static TCGv env_res_addr; -static TCGv_i32 env_res_val; +static TCGv_i32 cpu_iflags; +static TCGv cpu_res_addr; +static TCGv_i32 cpu_res_val; =20 #include "exec/gen-icount.h" =20 @@ -107,7 +107,7 @@ static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ if (dc->tb_flags !=3D dc->synced_flags) { - tcg_gen_movi_i32(env_iflags, dc->tb_flags); + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); dc->synced_flags =3D dc->tb_flags; } } @@ -222,10 +222,10 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(env_imm, env_imm, dc->imm); + tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); else - tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); - return &env_imm; + tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + return &cpu_imm; } else return &cpu_R[dc->rb]; } @@ -859,7 +859,7 @@ static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { if (dc->jmp =3D=3D JMP_DIRECT) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); } dc->jmp =3D JMP_INDIRECT; tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); @@ -869,7 +869,7 @@ static inline void sync_jmpstate(DisasContext *dc) static void dec_imm(DisasContext *dc) { LOG_DIS("imm %x\n", dc->imm << 16); - tcg_gen_movi_i32(env_imm, (dc->imm << 16)); + tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |=3D IMM_FLAG; dc->clear_imm =3D 0; } @@ -1040,8 +1040,8 @@ static void dec_load(DisasContext *dc) } =20 if (ex) { - tcg_gen_mov_tl(env_res_addr, addr); - tcg_gen_mov_i32(env_res_val, v); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_gen_mov_i32(cpu_res_val, v); } if (dc->rd) { tcg_gen_mov_i32(cpu_R[dc->rd], v); @@ -1103,7 +1103,7 @@ static void dec_store(DisasContext *dc) =20 write_carryi(dc, 1); swx_skip =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); =20 /* * Compare the value loaded at lwx with current contents of @@ -1111,11 +1111,11 @@ static void dec_store(DisasContext *dc) */ tval =3D tcg_temp_new_i32(); =20 - tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val, + tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, cpu_R[dc->rd], mem_index, mop); =20 - tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); write_carryi(dc, 0); tcg_temp_free_i32(tval); } @@ -1204,7 +1204,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 = pc_true, TCGv_i32 pc_false) TCGv_i32 zero =3D tcg_const_i32(0); =20 tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - env_btaken, zero, + cpu_btaken, zero, pc_true, pc_false); =20 tcg_temp_free_i32(zero); @@ -1245,7 +1245,7 @@ static void dec_bcc(DisasContext *dc) dc->jmp =3D JMP_INDIRECT; tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } - eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); + eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } =20 static void dec_br(DisasContext *dc) @@ -1311,7 +1311,7 @@ static void dec_br(DisasContext *dc) =20 dc->jmp =3D JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); if (link && !dslot) { if (!(dc->tb_flags & IMM_FLAG) && @@ -1330,7 +1330,7 @@ static void dec_br(DisasContext *dc) dc->jmp =3D JMP_DIRECT; dc->jmp_pc =3D dc->pc + (int32_t)((int16_t)dc->imm); } else { - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); } } @@ -1419,7 +1419,7 @@ static void dec_rts(DisasContext *dc) LOG_DIS("rts ir=3D%x\n", dc->ir); =20 dc->jmp =3D JMP_INDIRECT; - tcg_gen_movi_i32(env_btaken, 1); + tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } =20 @@ -1722,7 +1722,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) TCGLabel *l1 =3D gen_new_label(); t_sync_flags(dc); /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1848,22 +1848,22 @@ void mb_tcg_init(void) { int i; =20 - env_iflags =3D tcg_global_mem_new_i32(cpu_env, + cpu_iflags =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, iflags), "iflags"); - env_imm =3D tcg_global_mem_new_i32(cpu_env, + cpu_imm =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, imm), "imm"); cpu_btarget =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btarget), "btarget"); - env_btaken =3D tcg_global_mem_new_i32(cpu_env, + cpu_btaken =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, btaken), "btaken"); - env_res_addr =3D tcg_global_mem_new(cpu_env, + cpu_res_addr =3D tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); - env_res_val =3D tcg_global_mem_new_i32(cpu_env, + cpu_res_val =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, res_val), "res_val"); for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390329; cv=none; d=zohomail.com; s=zohoarc; b=Abfc9T/Ck1RqBE6cJ9Sy7YOM0YECeAyqeBtv4vn65S8o4xI0j+1O/Q3o7eM/uE9m7hRjI6rqjqhNfuDPa1sJoNHrZs86uja7wk5EYgbj9nf5Kw6vsBRNv3cv6ncN6XSqYhIJtf/rFMGWBWQsKw/c5fijqAMY6QIWiEjG9S0a+Dk= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 62 +++++++++++++++-------------------- 1 file changed, 27 insertions(+), 35 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9aa63ddcc5..e709884f2d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -95,14 +95,6 @@ typedef struct DisasContext { int singlestep_enabled; } DisasContext; =20 -static const char *regnames[] =3D -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1846,36 +1838,36 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) =20 void mb_tcg_init(void) { - int i; +#define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } +#define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X } =20 - cpu_iflags =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, iflags), - "iflags"); - cpu_imm =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, imm), - "imm"); - cpu_btarget =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btarget), - "btarget"); - cpu_btaken =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, btaken), - "btaken"); - cpu_res_addr =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMBState, res_addr), - "res_addr"); - cpu_res_val =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, res_val), - "res_val"); - for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUMBState, regs[i]), - regnames[i]); + static const struct { + TCGv_i32 *var; int ofs; char name[8]; + } i32s[] =3D { + R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), + R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), + R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), + + SP(pc), + SP(msr), + SP(imm), + SP(iflags), + SP(btaken), + SP(btarget), + SP(res_val), + }; + +#undef R +#undef SP + + for (int i =3D 0; i < ARRAY_SIZE(i32s); ++i) { + *i32s[i].var =3D + tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); } =20 - cpu_pc =3D - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); - cpu_msr =3D - tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); + cpu_res_addr =3D + tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_a= ddr"); } =20 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390499; cv=none; d=zohomail.com; s=zohoarc; b=IXZ+mNcpJihd5XkaH0ya6W7x+Cbk+3Chf1H+SkX0fs/5MpVzN4g6qSml6KGq4T9YdpfQ94Kr+QYHnIj9Q9EpaCmWB1cZXMVMOaDTDrfiVNK80/iDjtkOY/9WD2XX3psCPD7J8NzEgspN3eEVCSWOzb6hmOdRQ3Z5/mxRwGx+cEs= ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=cUS6GIKGx21wYOKJbrs7aR8rRqGzGceLtDLQyfMEprC0ONmpz4GgbAxDZOtyza7z5x UDQXaFBa4na9WG1aAomhPT+KnkQMZYmEFYChMLt/GrClhgDWvQ6vt2T2dlvVsBXo0xWE DtQ/C3AP/D5hxSD7hqZl4/nMCWFmvBj1prAg0pYn//Nhh6wySLGuJ7DcqjDhhaK9w3LU U3n+1FGRZp8sFKcxBK+InFHliLB031EWeOokq1NB2TjxbcljAhY4kZgTVYoUNMYDOeKz enaMVFfWANhMSmBWm/vTUI7xtRQErq0eWhQwv5vQxLRAy0G4cV/RMyWN7PG52jSVKNH6 p1Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tvav2yDgl091Kla7AxGkIifdrAi1yowT9YLtoH5uMlM=; b=cvslKu4qbdjjTM/4RHbo46V+aEGueHfTaUk/n2427eR4+X9WnSMejFwmI7hqQIG/1f JK9b6DwS86uDuSpsf54qrflIe2cuQsTGD50hi1UcnmRZxoKam3xMvqiKQqvwEgqQwZOs lJVj8C3w1cTRPKyCpXE3p/sk+J5CCwlnOGsmnsJhF9Rbx1r2FXIQyWlWo0lHMUKlYSPU QSwD0IuciLK73vnhB9Y9ZlfDSSvVKfUYmuB4L4moEg9p2smqZ7rUwToDvTx4hsS/1qAl TSnBaTFn9sonuNpD34zqO4fq7SFy60t12vHoXDdDY8vOvXq3nJwIHAsWFFBy5pU7wwqG frxQ== X-Gm-Message-State: AOAM530/vvFUAvElaqhfzI0C+xXguURIGVin/DoQjBJ8tZeIfPyxVghC xzCbVIwWs+lPX/6eWuaMJCLkzqMwdoQa6Q== X-Google-Smtp-Source: ABdhPJy1bfL/GnP4UEH++msVGtodUPR/E5eLZb4L00pqXs5+AqjVJynOYLKMMS7sgqzumAg2PccVFg== X-Received: by 2002:a63:77c1:: with SMTP id s184mr7947208pgc.420.1598389224653; Tue, 25 Aug 2020 14:00:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable Date: Tue, 25 Aug 2020 13:58:58 -0700 Message-Id: <20200825205950.730499-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 19 +++++++- linux-user/elfload.c | 2 +- target/microblaze/cpu.c | 4 +- target/microblaze/gdbstub.c | 4 +- target/microblaze/helper.c | 58 +++++++++++----------- target/microblaze/translate.c | 91 +++++++++++------------------------ 6 files changed, 82 insertions(+), 96 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7708c9a3d3..7066878ac7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -236,7 +236,8 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint32_t pc; - uint32_t msr; + uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ + uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ uint64_t ear; uint32_t esr; uint32_t fsr; @@ -327,6 +328,22 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr= addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 +static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) +{ + /* Replicate MSR[C] to MSR[CC]. */ + return env->msr | (env->msr_c * (MSR_C | MSR_CC)); +} + +static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) +{ + env->msr_c =3D (val >> 2) & 1; + /* + * Clear both MSR[C] and MSR[CC] from the saved copy. + * MSR_PVR is not writable and is always clear. + */ + env->msr =3D val & ~(MSR_C | MSR_CC | MSR_PVR); +} + void mb_tcg_init(void); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/linux-user/elfload.c b/linux-user/elfload.c index bbfb665321..98af4fe7e0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1033,7 +1033,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, const CPUMBState *env } =20 (*regs)[pos++] =3D tswapreg(env->pc); - (*regs)[pos++] =3D tswapreg(env->msr); + (*regs)[pos++] =3D tswapreg(mb_cpu_read_msr(env)); (*regs)[pos++] =3D 0; (*regs)[pos++] =3D tswapreg(env->ear); (*regs)[pos++] =3D 0; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0eac068570..1eabf5cc3f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev) =20 #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ - env->msr =3D MSR_EE | MSR_IE | MSR_VM | MSR_UM; + mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); #else - env->msr =3D 0; + mb_cpu_write_msr(env, 0); mmu_init(&env->mmu); env->mmu.c_mmu =3D 3; env->mmu.c_mmu_tlb_access =3D 3; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 9cba9d2215..08d6a0e807 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *me= m_buf, int n) val =3D env->pc; break; case GDB_MSR: - val =3D env->msr; + val =3D mb_cpu_read_msr(env); break; case GDB_EAR: val =3D env->ear; @@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) env->pc =3D tmp; break; case GDB_MSR: - env->msr =3D tmp; + mb_cpu_write_msr(env, tmp); break; case GDB_EAR: env->ear =3D tmp; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index b2373f6a23..9a95456401 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -112,12 +112,11 @@ void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; - uint32_t t; + uint32_t t, msr =3D mb_cpu_read_msr(env); =20 /* IMM flag cannot propagate across a branch and into the dslot. */ assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); -/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */ env->res_addr =3D RES_ADDR_NONE; switch (cs->exception_index) { case EXCP_HW_EXCP: @@ -136,11 +135,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 /* Disable the MMU. */ - t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |=3D t; + t =3D (msr & (MSR_VM | MSR_UM)) << 1; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |=3D t; /* Exception in progress. */ - env->msr |=3D MSR_EIP; + msr |=3D MSR_EIP; + mb_cpu_write_msr(env, msr); =20 qemu_log_mask(CPU_LOG_INT, "hw exception at pc=3D%x ear=3D%" PRIx64 " " @@ -178,11 +178,12 @@ void mb_cpu_do_interrupt(CPUState *cs) } =20 /* Disable the MMU. */ - t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; - env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |=3D t; + t =3D (msr & (MSR_VM | MSR_UM)) << 1; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |=3D t; /* Exception in progress. */ - env->msr |=3D MSR_EIP; + msr |=3D MSR_EIP; + mb_cpu_write_msr(env, msr); =20 qemu_log_mask(CPU_LOG_INT, "exception at pc=3D%x ear=3D%" PRIx64 " iflags= =3D%x\n", @@ -193,11 +194,11 @@ void mb_cpu_do_interrupt(CPUState *cs) break; =20 case EXCP_IRQ: - assert(!(env->msr & (MSR_EIP | MSR_BIP))); - assert(env->msr & MSR_IE); + assert(!(msr & (MSR_EIP | MSR_BIP))); + assert(msr & MSR_IE); assert(!(env->iflags & D_FLAG)); =20 - t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; + t =3D (msr & (MSR_VM | MSR_UM)) << 1; =20 #if 0 #include "disas/disas.h" @@ -212,21 +213,20 @@ void mb_cpu_do_interrupt(CPUState *cs) && (!strcmp("netif_rx", sym) || !strcmp("process_backlog", sym))) { =20 - qemu_log( - "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x sym= =3D%s\n", - env->pc, env->msr, t, env->iflags, - sym); + qemu_log("interrupt at pc=3D%x msr=3D%x %x iflags=3D%x= sym=3D%s\n", + env->pc, msr, t, env->iflags, sym); =20 log_cpu_state(cs, 0); } } #endif qemu_log_mask(CPU_LOG_INT, - "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, env->msr, t, env->iflags); + "interrupt at pc=3D%x msr=3D%x %x iflags=3D%x\n", + env->pc, msr, t, env->iflags); =20 - env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); - env->msr |=3D t; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE); + msr |=3D t; + mb_cpu_write_msr(env, msr); =20 env->regs[14] =3D env->pc; env->pc =3D cpu->cfg.base_vectors + 0x10; @@ -237,20 +237,22 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); - t =3D (env->msr & (MSR_VM | MSR_UM)) << 1; + t =3D (msr & (MSR_VM | MSR_UM)) << 1; qemu_log_mask(CPU_LOG_INT, "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", - env->pc, env->msr, t, env->iflags); + env->pc, msr, t, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); - env->msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); - env->msr |=3D t; - env->msr |=3D MSR_BIP; + msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); + msr |=3D t; + msr |=3D MSR_BIP; if (cs->exception_index =3D=3D EXCP_HW_BREAK) { env->regs[16] =3D env->pc; - env->msr |=3D MSR_BIP; + msr |=3D MSR_BIP; env->pc =3D cpu->cfg.base_vectors + 0x18; - } else + } else { env->pc =3D env->btarget; + } + mb_cpu_write_msr(env, msr); break; default: cpu_abort(cs, "unhandled exception type=3D%d\n", diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e709884f2d..0c9b4ffa5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -56,6 +56,7 @@ static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; +static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; static TCGv_i32 cpu_btaken; static TCGv_i32 cpu_btarget; @@ -150,30 +151,6 @@ static void gen_goto_tb(DisasContext *dc, int n, targe= t_ulong dest) } } =20 -static void read_carry(DisasContext *dc, TCGv_i32 d) -{ - tcg_gen_shri_i32(d, cpu_msr, 31); -} - -/* - * write_carry sets the carry bits in MSR based on bit 0 of v. - * v[31:1] are ignored. - */ -static void write_carry(DisasContext *dc, TCGv_i32 v) -{ - /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); - tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); -} - -static void write_carryi(DisasContext *dc, bool carry) -{ - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(t0, carry); - write_carry(dc, t0); - tcg_temp_free_i32(t0); -} - /* * Returns true if the insn an illegal operation. * If exceptions are enabled, an exception is raised. @@ -243,11 +220,7 @@ static void dec_add(DisasContext *dc) =20 if (c) { /* c - Add carry into the result. */ - cf =3D tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -257,21 +230,15 @@ static void dec_add(DisasContext *dc) /* Extract carry. */ cf =3D tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 0); } =20 + gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf =3D tcg_temp_new_i32(); - gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); } @@ -309,11 +276,7 @@ static void dec_sub(DisasContext *dc) =20 if (c) { /* c - Add carry into the result. */ - cf =3D tcg_temp_new_i32(); - - read_carry(dc, cf); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - tcg_temp_free_i32(cf); + tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); } } return; @@ -324,7 +287,7 @@ static void dec_sub(DisasContext *dc) cf =3D tcg_temp_new_i32(); na =3D tcg_temp_new_i32(); if (c) { - read_carry(dc, cf); + tcg_gen_mov_i32(cf, cpu_msr_c); } else { tcg_gen_movi_i32(cf, 1); } @@ -332,16 +295,10 @@ static void dec_sub(DisasContext *dc) /* d =3D b + ~a + c. carry defaults to 1. */ tcg_gen_not_i32(na, cpu_R[dc->ra]); =20 + gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); if (dc->rd) { - TCGv_i32 ncf =3D tcg_temp_new_i32(); - gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - write_carry(dc, ncf); - tcg_temp_free_i32(ncf); - } else { - gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); - write_carry(dc, cf); } tcg_temp_free_i32(cf); tcg_temp_free_i32(na); @@ -429,16 +386,26 @@ static void dec_xor(DisasContext *dc) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } =20 -static inline void msr_read(DisasContext *dc, TCGv_i32 d) +static void msr_read(DisasContext *dc, TCGv_i32 d) { - tcg_gen_mov_i32(d, cpu_msr); + TCGv_i32 t; + + /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */ + t =3D tcg_temp_new_i32(); + tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); + tcg_gen_or_i32(d, cpu_msr, t); + tcg_temp_free_i32(t); } =20 -static inline void msr_write(DisasContext *dc, TCGv_i32 v) +static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed =3D 1; - /* PVR bit is not writable, and is never set. */ - tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); + + /* Install MSR_C. */ + tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); + + /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clea= r. */ + tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } =20 static void dec_msr(DisasContext *dc) @@ -778,8 +745,8 @@ static void dec_bit(DisasContext *dc) t0 =3D tcg_temp_new_i32(); =20 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_shli_i32(t0, cpu_msr_c, 31); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); @@ -792,8 +759,7 @@ static void dec_bit(DisasContext *dc) /* srl. */ LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); =20 - /* Update carry. Note that write carry only looks at the LSB. = */ - write_carry(dc, cpu_R[dc->ra]); + tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op =3D=3D 0x41) tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); @@ -1042,7 +1008,7 @@ static void dec_load(DisasContext *dc) =20 if (ex) { /* lwx */ /* no support for AXI exclusive so always clear C */ - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); } =20 tcg_temp_free(addr); @@ -1093,7 +1059,7 @@ static void dec_store(DisasContext *dc) /* swx does not throw unaligned access errors, so force alignment = */ tcg_gen_andi_tl(addr, addr, ~3); =20 - write_carryi(dc, 1); + tcg_gen_movi_i32(cpu_msr_c, 1); swx_skip =3D gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); =20 @@ -1108,7 +1074,7 @@ static void dec_store(DisasContext *dc) mop); =20 tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - write_carryi(dc, 0); + tcg_gen_movi_i32(cpu_msr_c, 0); tcg_temp_free_i32(tval); } =20 @@ -1851,6 +1817,7 @@ void mb_tcg_init(void) =20 SP(pc), SP(msr), + SP(msr_c), SP(imm), SP(iflags), SP(btaken), --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389448; cv=none; d=zohomail.com; s=zohoarc; b=YOZfT5Jg0N39y/6iLkFKwDVoZJRDoIx0GycM/HXPdNfvGBgrmWXZL/iJ20zrnZZfeHcBojCdMxykmay/S8lguUnc95i7Psp0XG3/KISIT+v/QHCVJ2QY6YXQcVs9U66dtIu36ft2yCbBSZqFC841NxLQeKOm2azrj3ySqVk58Ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389448; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=IsMSyYfetmBAWTyssRESJqvoc73DQHdLrkIGdPMUY2fSUeceGJ6pKk/870SLYZ3rCTWMmGcX2V7xylI10fhu9l5PGeQm36KOoxIVdTCy0AKXrsUNe718RrtzLm815BNCmW5E8o38n02Cv54pHeVrl3j4iz6wfb4DT6EaN22ugwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389448064187.65789071252948; Tue, 25 Aug 2020 14:04:08 -0700 (PDT) Received: from localhost ([::1]:54448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAg6w-0004EO-Mf for importer@patchew.org; Tue, 25 Aug 2020 17:04:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3V-0007iz-2Q for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:34 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:41480) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3Q-0001ml-JH for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:32 -0400 Received: by mail-pf1-x444.google.com with SMTP id t9so4126902pfq.8 for ; Tue, 25 Aug 2020 14:00:26 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=Xt5JE9G85i3eZDXw3qRDWezs0DmH9p+/MSYAdzrtej6Sg6TLoDd4707qXx5UoZq95y 1uB+WZ/v+7ywlZbL8AB9+InqkWeGIRjlMOWvaVoj482u83u/uokVxXWUQw8xAGAgQE68 BIZ+IJ8et30Jiq+DAsFAiEZsVQcnzXmjw6+pSZ5DKaVIktlPGLJ8dWfeSbBJ8ALgfR1N PSBkAhuNjFi4n/bfQORYAcYwjbr4j7iX7PHmp8tUZFarszV8AjSSpMfCt8RDVN1hViNx MtCu6k4gqNHZRD5RsHtrTLOjwyHFR4JcdzyKaqmSWyeUdZIT0mlFeWUnQX9CsOJBlUTy E5tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXpLGSkTUh0l6cihbLBx2yxjRuaY4I2Cb0zQBnRmSlQ=; b=D4PTx6+DL2ZrMQvX0tR0PkZHxmxEDGHJ45ortiMe7/lAZlZzzxZUQKdu5b+jIpzfFR sS8cs9dLcOMc721OK0XJ5G2I1AavcdM1XPIxH5ojd9r77rfUorhRGz7MjoZP8ESXaQ26 YTLW+Iiidbg88P5kxxHM4DZQzs2DjEahZpo7O3HUnduwbUP/ENQqaPcH48pWCqp+DNzV z29S6pSEjP+z8MDQORWX00mhfxy2upBj2IgXh6flInbtI1A9/R1F5XFRFh6y0oPXqfeh Z/SwwBxY2KPwDrW62H0B/utn8/FzIM5XNEUwF8hA4HKdC4HpDBinlLBJTQOsTYJKKo5D EimA== X-Gm-Message-State: AOAM530gGeXx6i6+bUEcR3IQ7REBLGua+8msBMoIzsjXWIgnO0kiYVx/ RJbhEhJE47pKM2tvg9JewpLMRTLbB8CqDA== X-Google-Smtp-Source: ABdhPJyP0OS146Fbsadw8dr3iWkNmKoCpvC9i0GmzAsFx/0gnZoPIr3BBS183sgbliJoGKH7d6cROA== X-Received: by 2002:a17:902:c212:: with SMTP id 18mr9018374pll.250.1598389225716; Tue, 25 Aug 2020 14:00:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/77] target/microblaze: Use DISAS_NORETURN Date: Tue, 25 Aug 2020 13:58:59 -0700 Message-Id: <20200825205950.730499-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0c9b4ffa5a..53ca0bfb38 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -51,7 +51,6 @@ /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 static TCGv_i32 cpu_R[32]; static TCGv_i32 cpu_pc; @@ -111,7 +110,7 @@ static void gen_raise_exception(DisasContext *dc, uint3= 2_t index) =20 gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp =3D DISAS_UPDATE; + dc->is_jmp =3D DISAS_NORETURN; } =20 static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) @@ -149,6 +148,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->is_jmp =3D DISAS_NORETURN; } =20 /* @@ -1675,7 +1675,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) } else if (dc->jmp =3D=3D JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); - dc->is_jmp =3D DISAS_TB_JUMP; } else if (dc->jmp =3D=3D JMP_DIRECT_CC) { TCGLabel *l1 =3D gen_new_label(); t_sync_flags(dc); @@ -1684,8 +1683,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) gen_goto_tb(dc, 1, dc->pc); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); - - dc->is_jmp =3D DISAS_TB_JUMP; } break; } @@ -1717,7 +1714,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) } t_sync_flags(dc); =20 - if (unlikely(cs->singlestep_enabled)) { + if (dc->is_jmp =3D=3D DISAS_NORETURN) { + /* nothing more to generate */ + } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); =20 if (dc->is_jmp !=3D DISAS_JUMP) { @@ -1730,16 +1729,14 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; - default: case DISAS_JUMP: case DISAS_UPDATE: /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(NULL, 0); break; - case DISAS_TB_JUMP: - /* nothing more to generate */ - break; + default: + g_assert_not_reached(); } } gen_tb_end(tb, num_insns); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390401; cv=none; d=zohomail.com; s=zohoarc; b=bUwHF4bGACFr1llKL7+idSTUyXzFZw0ZTSPxJUGPNw2UUr3zRu1+sDBys1PtTmUPc7WE84D3VbX0gRxQ+mmOei0gQBeLAn+SuyUNUSLWGwfV+hTJ+XH34E1l4pYm3BK6u+bsPSNWnYcOhe/qg6iIveC3jnfcZLqV6SmaIyruHdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390401; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=C09j5aG3OWvzNM/AeLyfZV6sQZvmpUI2BP+8pJb19BPPtCHl+rPUkyxfxA8+u1w+MhJfSBncRLOYJMLq3MJfqsVSQfBT9rPb6JM1Os4MRZqyKZp1DIXj1sSzqUP36Wwis7vWCybSJf/Dyq+c9AfcTm15AeNLy1XEfuuRd+GdSzY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390401383981.8771655924548; Tue, 25 Aug 2020 14:20:01 -0700 (PDT) Received: from localhost ([::1]:59260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgMK-00047v-54 for importer@patchew.org; Tue, 25 Aug 2020 17:20:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3X-0007kU-3v for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:36 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42052) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3Q-0001nR-Ks for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:33 -0400 Received: by mail-pg1-x541.google.com with SMTP id g1so3877987pgm.9 for ; Tue, 25 Aug 2020 14:00:28 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=B8Uu8iDoxOG0+lWySO7Vk2GvwdOBihkCDODrs9X9UigfE4Vv0JHSggtZGBbSCYZexa w5AqSeJSQWg1CcRuZRI5naiMxdfY9MrJOVLe+DX8/1JiLWkkTUp55Se7GFTlO+ROPXM3 UJvVvDF81tPiMVO1m7odPomrnssmnd9RJ9QlGHgtOYl3WW6of41q5ECbyz7pcmy1hPUL gEpZWK2upfkYY+R6mVNSqOEB2w3z7nUtZEEZPvkEqJ+LAK63pvh4BngYyBUq2J+4HdvZ kaapqEnoP3pIz96euGL1+bglT7bAQRWd0apfClM4MT1P1sf6SgqWnrztbJQKS/CNw12b EiQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vRHfeWYe4t2JOdjOnGDnZu1tFFPEQawCvJ5AdLU8/XA=; b=mqtLwGG9blg7fIFyxGJ/vXQK2oCX4bhlTWUyKaSXWsg+19B4bWipCiKxLZt9KJRD8W /i0JXW1xu5brCoWU5J/zw27zwKBcBd9i/V7Mi81UGAAsqljHsaFD3Mbm290PG6igamj/ WYHkQR81o/1X3rDOP+s91rhYosCeGnm84er/aj2c2ODh9xjXadKeEvivO7r31Tg8kZ5w LoDwP5oSC68I7/MuAjtGU64zFyIr92QJgjAzqsmcDV6w5OPFvG0jpmjYGw7y/AhmLRlz yC3SMf6nZaZHhATiS0ReyTha5kkfDK3Dp464XQlStnll5ZizufMQsjmQDaZeoAYFlTUf EwNA== X-Gm-Message-State: AOAM532sbC9e+NII1Q+CVEaqeKODnSixMoCr+jFxbGFLAyrsEmApk18B HTRS6dJth7LvYuDF8EmXaqeyd2dDWm315g== X-Google-Smtp-Source: ABdhPJw9V17b6eydCwKxrg3p7YnuUnuRDWWIegdCFgcNGFMjeACimgbU9XifywY6F3behHrJAoTkuQ== X-Received: by 2002:a63:4859:: with SMTP id x25mr8122986pgk.422.1598389226851; Tue, 25 Aug 2020 14:00:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb Date: Tue, 25 Aug 2020 13:59:00 -0700 Message-Id: <20200825205950.730499-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Do not use goto_tb if we're single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 53ca0bfb38..7d5b96c38b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -140,7 +140,12 @@ static inline bool use_goto_tb(DisasContext *dc, targe= t_ulong dest) =20 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (use_goto_tb(dc, dest)) { + if (dc->singlestep_enabled) { + TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); + tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + gen_helper_raise_exception(cpu_env, tmp); + tcg_temp_free_i32(tmp); + } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(dc->tb, n); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390459; cv=none; d=zohomail.com; s=zohoarc; b=AjgPyaVc2Bm5QI33Cti/c+WuHTCQzvmCaKAJRnADCrKfWGL6DGpoG3KQOQ3tYdHMf61FzCLvRaoKtTfvht/Z9pCTDlYGmQLOu4cD8PF57ndOl8EYJ0rhgX7tHM8c5AasDYBgw6QyoPKUFUjxp1WvLgw1p5+oiVSp9O2eGBthR1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390459; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=ciPRap0w2cQylCViJDyhYtPGTKIGGcGc+12k5c2ydHOpeLPaxNY4Br14+dwkOCdPYnvCW94BYmmzfsV2i7pmNkAP7/BKsRf89p8grOHqvJSCtjzYOw00MwGi6Pml42/LzzqlSLeK2+zOlFNjdvOrNauZ1SIYPaWdIBTiZWbdhXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390459646374.5094045121107; Tue, 25 Aug 2020 14:20:59 -0700 (PDT) Received: from localhost ([::1]:35270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgNG-0005xL-AT for importer@patchew.org; Tue, 25 Aug 2020 17:20:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3X-0007ko-6t for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:36 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:45920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3S-0001om-KW for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:34 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 67so4561378pgd.12 for ; Tue, 25 Aug 2020 14:00:30 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=NERN6mRcxfwog3EP6b888jsaQ3Q9PdbsaAsQ6LOu4XGCTHhwdt69lQcy4Nz9g8t1zF gbMSXIdOaSnRW8SKtAo0lnLLd18gD6ViikiL4MQhJltg5VjpEXSxN9tLuwsM9SBNRNAt 8Bfbwj4o4JqU03coJb3CEYUCpy+GaQU1B10c92KNvHj/2+rT2CcSSYdf1X354uU17mJ3 F2Ma3YGEbj6g7wM2R0/mOHn6jnpos1NW25D3FIGh8UMD7CS0JKF+UzLO0r1u/EUxBLEy rnrCnKJLpiHN0YGMJuu8tokzJL6+nbxPCQbEVsd9gyeCaolPf7Pb3b4+OPjESztKnwet if4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kv9Q2CNP0xNdIj9IWSGlA1oMnFfXI9CS46hFWNSGG9w=; b=mXzlAMJymeS7ZSkrW6e2MoPyMvUHGzDIs22sxtAdeHAWX8L5fAPRdAY+/97pj3cCl7 +9wUc27X9OVwKbMBdhscfJYQZVjE5NO1PRQ66fSFV0VOHZv1uKax3cyjnCIDBnELf+9p dX42eJRry///Q23NO1vW7QWG2Kx5Mh18dzoQ7iYXLVv1gRXB22LUd6MJq3uQNdQNOZs9 pi7uX/46zlFzzozJbJWRTtcxQjJml2OtLTJJYdyv1Rib/UhlgsSo3R0GUiFvtm0CvoIk HyZOVy7n+LYVWH7KSlAc1ddxQwg4AvbQtk2iyamyBH7rRTVMUClV/jYCC9h0Xp0LjzPb 2i4A== X-Gm-Message-State: AOAM530qKMCCVTVtmqrQl1zDrpJuqcR93YMh/nb6lZY7PqKnbRi0LuzC BpNoqvqqZOAUCD540KDDXcMivJjRJ8yf6g== X-Google-Smtp-Source: ABdhPJzz7HS6gekNaWNfeAWW2C03W5Luo7TM6mtSl6+7H7ZMmeIZ4ZJY0j8P/2HLW4MhfUn5LAo9Ew== X-Received: by 2002:a63:5961:: with SMTP id j33mr8057262pgm.130.1598389228413; Tue, 25 Aug 2020 14:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/77] target/microblaze: Convert to DisasContextBase Date: Tue, 25 Aug 2020 13:59:01 -0700 Message-Id: <20200825205950.730499-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 104 +++++++++++++++++----------------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d5b96c38b..45b1555f85 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -67,8 +67,8 @@ static TCGv_i32 cpu_res_val; =20 /* This is the state at translation time. */ typedef struct DisasContext { + DisasContextBase base; MicroBlazeCPU *cpu; - uint32_t pc; =20 /* Decoder. */ int type_b; @@ -81,7 +81,6 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; - int is_jmp; =20 #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -91,8 +90,6 @@ typedef struct DisasContext { uint32_t jmp_pc; =20 int abort_at_next_insn; - struct TranslationBlock *tb; - int singlestep_enabled; } DisasContext; =20 static inline void t_sync_flags(DisasContext *dc) @@ -110,13 +107,13 @@ static void gen_raise_exception(DisasContext *dc, uin= t32_t index) =20 gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) { t_sync_flags(dc); - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_raise_exception(dc, index); } =20 @@ -132,7 +129,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_= t esr_ec) static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK= ); + return (dc->base.pc_first & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PA= GE_MASK); #else return true; #endif @@ -140,20 +137,20 @@ static inline bool use_goto_tb(DisasContext *dc, targ= et_ulong dest) =20 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) { - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); - tcg_gen_movi_i64(cpu_SR[SR_PC], dest); + tcg_gen_movi_i32(cpu_pc, dest); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(dc->tb, n); + tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 /* @@ -468,8 +465,8 @@ static void dec_msr(DisasContext *dc) msr_write(dc, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); - dc->is_jmp =3D DISAS_UPDATE; + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + dc->base.is_jmp =3D DISAS_UPDATE; return; } =20 @@ -546,7 +543,7 @@ static void dec_msr(DisasContext *dc) =20 switch (sr) { case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); break; case SR_MSR: msr_read(dc, cpu_R[dc->rd]); @@ -813,7 +810,7 @@ static void dec_bit(DisasContext *dc) break; default: cpu_abort(cs, "unknown bit oc=3D%x op=3D%x rd=3D%d ra=3D%d rb= =3D%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->= rb); break; } } @@ -994,7 +991,7 @@ static void dec_load(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_helper_memalign(cpu_env, addr, treg, t0, tsize); =20 tcg_temp_free_i32(t0); @@ -1114,7 +1111,7 @@ static void dec_store(DisasContext *dc) TCGv_i32 treg =3D tcg_const_i32(dc->rd); TCGv_i32 tsize =3D tcg_const_i32(size - 1); =20 - tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe * the MMU prior to the memaccess, thay way we could put @@ -1201,12 +1198,12 @@ static void dec_bcc(DisasContext *dc) if (dec_alu_op_b_is_small_imm(dc)) { int32_t offset =3D (int32_t)((int16_t)dc->imm); /* sign-extend. */ =20 - tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); + tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); dc->jmp =3D JMP_DIRECT_CC; - dc->jmp_pc =3D dc->pc + offset; + dc->jmp_pc =3D dc->base.pc_next + offset; } else { dc->jmp =3D JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1250,7 +1247,7 @@ static void dec_br(DisasContext *dc) +offsetof(CPUState, halted)); tcg_temp_free_i32(tmp_1); =20 - tcg_gen_movi_i32(cpu_pc, dc->pc + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); =20 gen_raise_exception(dc, EXCP_HLT); return; @@ -1270,7 +1267,7 @@ static void dec_br(DisasContext *dc) dec_setup_dslot(dc); } if (link && dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); + tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); =20 dc->jmp =3D JMP_INDIRECT; if (abs) { @@ -1291,10 +1288,10 @@ static void dec_br(DisasContext *dc) } else { if (dec_alu_op_b_is_small_imm(dc)) { dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D dc->pc + (int32_t)((int16_t)dc->imm); + dc->jmp_pc =3D dc->base.pc_next + (int32_t)((int16_t)dc->imm); } else { tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); + tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_n= ext); } } } @@ -1459,7 +1456,8 @@ static void dec_fpu(DisasContext *dc) qemu_log_mask(LOG_UNIMP, "unimplemented fcmp fpu_insn=3D%x pc=3D%= x" " opc=3D%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, + dc->opcode); dc->abort_at_next_insn =3D 1; break; } @@ -1489,7 +1487,7 @@ static void dec_fpu(DisasContext *dc) default: qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=3D%x= pc=3D%x" " opc=3D%x\n", - fpu_insn, dc->pc, dc->opcode); + fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode= ); dc->abort_at_next_insn =3D 1; break; } @@ -1500,7 +1498,8 @@ static void dec_null(DisasContext *dc) if (trap_illegal(dc, true)) { return; } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=3D%x opc=3D%x\n", dc->= pc, dc->opcode); + qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=3D%x opc=3D%x\n", + (uint32_t)dc->base.pc_next, dc->opcode); dc->abort_at_next_insn =3D 1; } =20 @@ -1610,19 +1609,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) =20 pc_start =3D tb->pc; dc->cpu =3D cpu; - dc->tb =3D tb; org_flags =3D dc->synced_flags =3D dc->tb_flags =3D tb->flags; =20 - dc->is_jmp =3D DISAS_NEXT; dc->jmp =3D 0; dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); if (dc->delayed_branch) { dc->jmp =3D JMP_INDIRECT; } - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->base.pc_first =3D pc_start; + dc->base.pc_next =3D pc_start; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.tb =3D tb; =20 if (pc_start & 3) { cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", pc_start); @@ -1634,31 +1634,31 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) gen_tb_start(tb); do { - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->base.pc_next); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { gen_raise_exception_sync(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc->pc +=3D 4; + dc->base.pc_next +=3D 4; break; } =20 /* Pretty disas. */ - LOG_DIS("%8.8x:\t", dc->pc); + LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); =20 if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 dc->clear_imm =3D 1; - decode(dc, cpu_ldl_code(env, dc->pc)); + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); if (dc->clear_imm) dc->tb_flags &=3D ~IMM_FLAG; - dc->pc +=3D 4; + dc->base.pc_next +=3D 4; =20 if (dc->delayed_branch) { dc->delayed_branch--; @@ -1673,10 +1673,10 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) dc->tb_flags &=3D ~D_FLAG; /* If it is a direct jump, try direct chaining. */ if (dc->jmp =3D=3D JMP_INDIRECT) { - TCGv_i32 tmp_pc =3D tcg_const_i32(dc->pc); + TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); eval_cond_jmp(dc, cpu_btarget, tmp_pc); tcg_temp_free_i32(tmp_pc); - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } else if (dc->jmp =3D=3D JMP_DIRECT) { t_sync_flags(dc); gen_goto_tb(dc, 0, dc->jmp_pc); @@ -1685,26 +1685,26 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) t_sync_flags(dc); /* Conditional jmp. */ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->pc); + gen_goto_tb(dc, 1, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 0, dc->jmp_pc); } break; } } - if (cs->singlestep_enabled) { + if (dc->base.singlestep_enabled) { break; } - } while (!dc->is_jmp && !dc->cpustate_changed + } while (!dc->base.is_jmp && !dc->cpustate_changed && !tcg_op_buf_full() && !singlestep - && (dc->pc - page_start < TARGET_PAGE_SIZE) + && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) && num_insns < max_insns); =20 - npc =3D dc->pc; + npc =3D dc->base.pc_next; if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { if (dc->tb_flags & D_FLAG) { - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); sync_jmpstate(dc); } else @@ -1712,25 +1712,25 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) } =20 /* Force an update if the per-tb cpu state has changed. */ - if (dc->is_jmp =3D=3D DISAS_NEXT + if (dc->base.is_jmp =3D=3D DISAS_NEXT && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; tcg_gen_movi_i32(cpu_pc, npc); } t_sync_flags(dc); =20 - if (dc->is_jmp =3D=3D DISAS_NORETURN) { + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { /* nothing more to generate */ } else if (unlikely(cs->singlestep_enabled)) { TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); =20 - if (dc->is_jmp !=3D DISAS_JUMP) { + if (dc->base.is_jmp !=3D DISAS_JUMP) { tcg_gen_movi_i32(cpu_pc, npc); } gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } else { - switch(dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, npc); break; @@ -1746,7 +1746,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) } gen_tb_end(tb, num_insns); =20 - tb->size =3D dc->pc - pc_start; + tb->size =3D dc->base.pc_next - pc_start; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS @@ -1755,7 +1755,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { FILE *logfile =3D qemu_log_lock(); qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start); + log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); qemu_log_unlock(logfile); } #endif --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390544; cv=none; d=zohomail.com; s=zohoarc; b=YmJo+DP1ks/cRQ6lvTGoklKGNHk7UNbnKH+QAf2eQ+/rq3XzXBTkjkpP6OJ8u4UhcPP/5VtNSlVrcxT4kNYcQJuiJm+6sDHUmyeS1BSl8Aq+YqjHvkzlxXt8Y+lkxSd6Gc/PV66WT1uQkcn9tG1tAaGVqrUwbzsMZsZlKUxZ+rQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390544; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M605GjYj/TsAqS9LhAzYjh6MlBkWbkHJca8j+nbMmp4=; b=jcvqyZnThZ/3ASU91duPjcaQ7BdUAPmcwiKJovm/prHu5wf2MepgTAbmV6egLNARHE 8t29ZrUtBnhTNE4tdanV1o+IkBO55oPTUERBp/j1CjiPdiYzsNreLUH8UiMPKkQHyRh2 lSpyTxhdVA6fwVYS+SvrL5RY6h62/l9UzcLxO6FhOlcZkZEa1iNPCEsIzP94LD+mbu3i u8UEy5pKY8j4MaBfi64Hdzu14yBu6iHxGTQYa8lW5iWzG7PJVN0EguWNqrGDAOe8Vgv9 b6zw2UzodXn2BdanjCBOBSo97P7B6A8kzj7+BUbBf0mlpW5wWYPTShwjF01SpxdR3tEb d+LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M605GjYj/TsAqS9LhAzYjh6MlBkWbkHJca8j+nbMmp4=; b=a75wgPiUfXzi+2SpCDkVRcI3aBHuX+Yr+MjCXUw0JqJAoeWPuB1jnMnTv52A+wU9+F +Em/d+rzWM6RQfoLHRatlWnmK4Qgp9i8iBlIQ3YoN5I7TVTFhtrTDgjm4a0a+9LKiVYF NtLUeTp9zlW9MmfstD0CevzcyN4ayTQI1HqD1eheTvKCG1LEEx6lGYIxlXHDdcXithSJ MKupOeUQ2Z+xUTMmxLD+wJJapjIE0CUx0PEbOoZOIjHwIrb+Af/frySUhVMEEiBIzvIW Tl5q0XmvytUUabMeBujt6R/Ojr1YPGAVGomsF1RPhFmWuneKE08F43G8eY84zQvsG5Qw fo5Q== X-Gm-Message-State: AOAM5326DKWgyNS7Gre7yzfWj4T7p+LRh3k/1KFoCtgT38sinqiSB7BF enRkJAHcxp1doJziotBZ2fVQp0KWVhlCdA== X-Google-Smtp-Source: ABdhPJw/Moh5vxoSlhVdWC1DXqJPoH5MIWmlkNClwi8E39OayFE4i966A7kwPz+T6CMC8FgYVRMjnw== X-Received: by 2002:aa7:9552:: with SMTP id w18mr9374849pfq.150.1598389229530; Tue, 25 Aug 2020 14:00:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/77] target/microblaze: Convert to translator_loop Date: Tue, 25 Aug 2020 13:59:02 -0700 Message-Id: <20200825205950.730499-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Part two of conversion to the generic translator_loop. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++++++++++++++++++---------------- 1 file changed, 149 insertions(+), 140 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 45b1555f85..6a9710d76d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint3= 2_t ir) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { - CPUMBState *env =3D cs->env_ptr; - MicroBlazeCPU *cpu =3D env_archcpu(env); - uint32_t pc_start; - struct DisasContext ctx; - struct DisasContext *dc =3D &ctx; - uint32_t page_start, org_flags; - uint32_t npc; - int num_insns; + DisasContext *dc =3D container_of(dcb, DisasContext, base); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + int bound; =20 - pc_start =3D tb->pc; dc->cpu =3D cpu; - org_flags =3D dc->synced_flags =3D dc->tb_flags =3D tb->flags; - - dc->jmp =3D 0; + dc->synced_flags =3D dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); - if (dc->delayed_branch) { - dc->jmp =3D JMP_INDIRECT; - } - dc->base.pc_first =3D pc_start; - dc->base.pc_next =3D pc_start; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.tb =3D tb; =20 - if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", pc_start); + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); +} + +static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) +{ +} + +static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) +{ + tcg_gen_insn_start(dcb->pc_next); +} + +static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + gen_raise_exception_sync(dc, EXCP_DEBUG); + + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + dc->base.pc_next +=3D 4; + return true; +} + +static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + CPUMBState *env =3D cs->env_ptr; + + /* TODO: This should raise an exception, not terminate qemu. */ + if (dc->base.pc_next & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", + (uint32_t)dc->base.pc_next); } =20 - page_start =3D pc_start & TARGET_PAGE_MASK; - num_insns =3D 0; + dc->clear_imm =3D 1; + decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + if (dc->clear_imm) { + dc->tb_flags &=3D ~IMM_FLAG; + } + dc->base.pc_next +=3D 4; =20 - gen_tb_start(tb); - do - { - tcg_gen_insn_start(dc->base.pc_next); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - gen_raise_exception_sync(dc, EXCP_DEBUG); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - break; + if (dc->delayed_branch && --dc->delayed_branch =3D=3D 0) { + if (dc->tb_flags & DRTI_FLAG) { + do_rti(dc); } - - /* Pretty disas. */ - LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next); - - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); + if (dc->tb_flags & DRTB_FLAG) { + do_rtb(dc); } - - dc->clear_imm =3D 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) - dc->tb_flags &=3D ~IMM_FLAG; - dc->base.pc_next +=3D 4; - - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - if (dc->tb_flags & DRTI_FLAG) - do_rti(dc); - if (dc->tb_flags & DRTB_FLAG) - do_rtb(dc); - if (dc->tb_flags & DRTE_FLAG) - do_rte(dc); - /* Clear the delay slot flag. */ - dc->tb_flags &=3D ~D_FLAG; - /* If it is a direct jump, try direct chaining. */ - if (dc->jmp =3D=3D JMP_INDIRECT) { - TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); - dc->base.is_jmp =3D DISAS_JUMP; - } else if (dc->jmp =3D=3D JMP_DIRECT) { - t_sync_flags(dc); - gen_goto_tb(dc, 0, dc->jmp_pc); - } else if (dc->jmp =3D=3D JMP_DIRECT_CC) { - TCGLabel *l1 =3D gen_new_label(); - t_sync_flags(dc); - /* Conditional jmp. */ - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); - gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); - gen_goto_tb(dc, 0, dc->jmp_pc); - } - break; - } + if (dc->tb_flags & DRTE_FLAG) { + do_rte(dc); } - if (dc->base.singlestep_enabled) { - break; - } - } while (!dc->base.is_jmp && !dc->cpustate_changed - && !tcg_op_buf_full() - && !singlestep - && (dc->base.pc_next - page_start < TARGET_PAGE_SIZE) - && num_insns < max_insns); - - npc =3D dc->base.pc_next; - if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { - if (dc->tb_flags & D_FLAG) { - dc->base.is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); - sync_jmpstate(dc); - } else - npc =3D dc->jmp_pc; + /* Clear the delay slot flag. */ + dc->tb_flags &=3D ~D_FLAG; + dc->base.is_jmp =3D DISAS_JUMP; } =20 - /* Force an update if the per-tb cpu state has changed. */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT - && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { + /* Force an exit if the per-tb cpu state has changed. */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT && dc->cpustate_changed) { dc->base.is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_i32(cpu_pc, npc); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); } - t_sync_flags(dc); +} + +static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + assert(!dc->abort_at_next_insn); =20 if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - /* nothing more to generate */ - } else if (unlikely(cs->singlestep_enabled)) { - TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); - - if (dc->base.is_jmp !=3D DISAS_JUMP) { - tcg_gen_movi_i32(cpu_pc, npc); - } - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - gen_goto_tb(dc, 1, npc); - break; - case DISAS_JUMP: - case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ - tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); - } + /* We have already exited the TB. */ + return; } - gen_tb_end(tb, num_insns); =20 - tb->size =3D dc->base.pc_next - pc_start; - tb->icount =3D num_insns; + t_sync_flags(dc); + if (dc->tb_flags & D_FLAG) { + sync_jmpstate(dc); + dc->jmp =3D JMP_NOJMP; + } =20 + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + assert(dc->jmp =3D=3D JMP_NOJMP); + gen_goto_tb(dc, 0, dc->base.pc_next); + return; + + case DISAS_UPDATE: + assert(dc->jmp =3D=3D JMP_NOJMP); + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; + + case DISAS_JUMP: + switch (dc->jmp) { + case JMP_INDIRECT: + { + TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); + eval_cond_jmp(dc, cpu_btarget, tmp_pc); + tcg_temp_free_i32(tmp_pc); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + } + return; + + case JMP_DIRECT_CC: + { + TCGLabel *l1 =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + gen_goto_tb(dc, 1, dc->base.pc_next); + gen_set_label(l1); + } + /* fall through */ + + case JMP_DIRECT: + gen_goto_tb(dc, 0, dc->jmp_pc); + return; + } + /* fall through */ + + default: + g_assert_not_reached(); + } +} + +static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) +{ #ifdef DEBUG_DISAS #if !SIM_COMPAT - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - FILE *logfile =3D qemu_log_lock(); - qemu_log("--------------\n"); - log_target_disas(cs, pc_start, dc->base.pc_next - pc_start); - qemu_log_unlock(logfile); - } + qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); + log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif #endif - assert(!dc->abort_at_next_insn); +} + +static const TranslatorOps mb_tr_ops =3D { + .init_disas_context =3D mb_tr_init_disas_context, + .tb_start =3D mb_tr_tb_start, + .insn_start =3D mb_tr_insn_start, + .breakpoint_check =3D mb_tr_breakpoint_check, + .translate_insn =3D mb_tr_translate_insn, + .tb_stop =3D mb_tr_tb_stop, + .disas_log =3D mb_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) +{ + DisasContext dc; + translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389584; cv=none; d=zohomail.com; s=zohoarc; b=j+B3K0+McwOrbrtC7jzJgcwcCSAcmqnX5LY3uh2lxo8nWJ6mBTER8BUYP8C3nSEO8g76brjXv02hU6p5pq0QoD3KdwYyf/MxvK1Q3BlmC+1wdY7zLfqY6R2FgR9pKZx0fQB40mWpc7WXFpmSGer4PRgymsgaH56wCp+vKQo/Cs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a9710d76d..a90e56a17f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,10 +34,9 @@ #include "exec/log.h" =20 =20 -#define SIM_COMPAT 0 #define DISAS_GNU 1 #define DISAS_MB 1 -#if DISAS_MB && !SIM_COMPAT +#if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) #else # define LOG_DIS(...) do { } while (0) @@ -1749,11 +1748,9 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPU= State *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { #ifdef DEBUG_DISAS -#if !SIM_COMPAT qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); #endif -#endif } =20 static const TranslatorOps mb_tr_ops =3D { --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389705; cv=none; d=zohomail.com; s=zohoarc; b=Z03Saq50UfcAAx42WBPCDMHgbpKgthNcz/JIO6/kw7j1TNrebjfDEV2KEznpoRUxdUnq3ye4ielqgUCKl6Bn+GDY7hEL3DUDu87W73RYzuzzWeN9R9MjgLPysfe+JTQ0y45MeuU++mTn43DfqY/HQ1X98vtV/xPsu3hY9l+kNQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389705; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Vc1/n0PAMq2ruFSCbPStrg/chGbNzuC4FGRX/oeXBs0=; b=O6/KD6FOLMEk/bxBFFappxALsYHYY3TZz0D0aP9nyowR2jR909PS4nadcC7JZND/dBIRtn7PdTmY2j07a901c/n0S5ytOfPYgJlQzq8lGsLE+SE0By2ob13k0mPaERQIFOd2Ap9v2vLtmBkjipPlNGE8OkX9n3R97Qm96Kza+/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159838970546290.51421531790254; Tue, 25 Aug 2020 14:08:25 -0700 (PDT) Received: from localhost ([::1]:42888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgB6-0002iL-56 for importer@patchew.org; Tue, 25 Aug 2020 17:08:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3b-0007rY-2Y for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:39 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:44497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3V-0001qC-PM for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:38 -0400 Received: by mail-pf1-x42b.google.com with SMTP id p11so5117211pfn.11 for ; Tue, 25 Aug 2020 14:00:33 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -34,7 +34,6 @@ #include "exec/log.h" =20 =20 -#define DISAS_GNU 1 #define DISAS_MB 1 #if DISAS_MB # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390585; cv=none; d=zohomail.com; s=zohoarc; b=iSmk0EMBhjs36jRMWAq61TRZt/FIn+oE/9I/nCV8PDlCMsZPZ22nSmx1sJ78PBsACtwV2gNY36zHL+UmDHWILkkyolJHKQbVUVuTLYj4uP3Kie3pYST8Ew5427W+HAk/W+K1Fz/HNQmYCoEQ35aqvC6rKF2bUtrzdvYs0iy7aaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390585; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=MDXvej4iFCNcbbfRtIfTZmFi2qtwZJ/fH55LdtGMK4OmemwXpqIYjWrZCU701NSGCb1+Bl6BF8Kbu5QlR/8427ZekViH1tG1cbONcZ0uagJsNOkf5BYcjNu2PHk7JqwQwfsqI2LzJw/Wo2Auc1InCW5BXqR2h/puMJvUE8SDb+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390585652349.697283376139; Tue, 25 Aug 2020 14:23:05 -0700 (PDT) Received: from localhost ([::1]:47468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgPI-0002W3-AO for importer@patchew.org; Tue, 25 Aug 2020 17:23:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3a-0007r1-Qq for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:38 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40288) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3W-0001qK-UY for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:38 -0400 Received: by mail-pf1-x443.google.com with SMTP id k18so8289934pfp.7 for ; Tue, 25 Aug 2020 14:00:34 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=B0twTuksnwz7HZ+KtuQhPiyv5xfA0oLn/CccM6Ql26TDaoQWI2B8eWPlsWtpbhecey uSA172Q6JQ9m1HLO/CGWZF4n6anl6yCUL3HnGqppFtwsKobmxcpDRVfo71h1WlxdDOIl SbIqBY9iXZuCMxL5TsvZaigVz3/3/go12CEBXwVF6C5xSbMKUWZDYauqtEa9SHwSAW0Y 7szCyjEzMk10FcKwBlkznELjrBIyF91Ce7zFI8B3SKf1fBS+Xe8LpX9R1iu/o4KDnHFG KmUGqcfcVs3UehoiCqG3p4YWcWss4HGTs7dWZ8nUe4MXgbg8OK5uh4BWgtJUKR4rcsOK 01Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b/4g1T+WE9RDnuv3IAKyPSAVgdbvulTxnio8bcXmxqI=; b=UMQag2IZEN2qeSPXh6Qe0KLKflByGiYkBaooyAmZQMgh80crEL71WbgkI4DOkI0qaS R3f/gieRv3U9XRC1W5S7tHljc71+N6fUTkwJ5AfKkDl0W1kVmUvacwnCaGUJt27b6d/0 3zxCnlPwgFZMqkDHwMPU/GuEpBoTPiW+3+hGpYaxmSJJvOsnUPk4xtGmuG+6QPIBpCZN YAZMZgsjuQYGarz/x/D/vB0tWnDEYGHbCJs1bnnABEO6tspnTOvgwLaQrMSQW04VQiK1 yRQIaFbmuKyu+3RBTeselA74NqWnmvCvc9VIZE1ZoVGRQq3Je2JpvaHA2zVoW8Fdu0da s/Ow== X-Gm-Message-State: AOAM531Qhtjshj8b0xHK5Ij4U7kuZbF9fugVrLyPPO8C+mp0qn/BLVfQ V6idvKC3wCsmr+TeXO1LDZsa8YdQQ/Volg== X-Google-Smtp-Source: ABdhPJy4ITh0mGPprZXHrELKExwI8yMYm9RSrajy26YrksYkcVmC1hJ24xL4EsqpkYKw5nKkkETN7g== X-Received: by 2002:a17:902:343:: with SMTP id 61mr8991627pld.274.1598389233135; Tue, 25 Aug 2020 14:00:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/77] target/microblaze: Remove empty D macros Date: Tue, 25 Aug 2020 13:59:05 -0700 Message-Id: <20200825205950.730499-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Signed-off-by: Richard Henderson --- target/microblaze/helper.c | 11 ++++------- target/microblaze/op_helper.c | 2 -- target/microblaze/translate.c | 2 -- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9a95456401..f8e2ca12a9 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -24,8 +24,6 @@ #include "qemu/host-utils.h" #include "exec/log.h" =20 -#define D(x) - #if defined(CONFIG_USER_ONLY) =20 void mb_cpu_do_interrupt(CPUState *cs) @@ -155,10 +153,13 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] =3D env->pc; =20 + qemu_log_mask(CPU_LOG_INT, + "MMU exception at pc=3D%x iflags=3D%x ear=3D%" P= RIx64 "\n", + env->pc, env->iflags, env->ear); + env->esr &=3D ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - D(qemu_log("D_FLAG set at exception bimm=3D%d\n", env->bim= m)); env->esr |=3D 1 << 12 ; env->btr =3D env->btarget; =20 @@ -166,14 +167,10 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[17] -=3D 4; /* was the branch immprefixed?. */ if (env->bimm) { - qemu_log_mask(CPU_LOG_INT, - "bimm exception at pc=3D%x iflags=3D%x\n= ", - env->pc, env->iflags); env->regs[17] -=3D 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { - D(qemu_log("IMM_FLAG set at exception\n")); env->regs[17] -=3D 4; } =20 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d79202c3f8..decdca0fd8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -26,8 +26,6 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" =20 -#define D(x) - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test =3D ctrl & STREAM_TEST; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6757720776..860859324a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -41,8 +41,6 @@ # define LOG_DIS(...) do { } while (0) #endif =20 -#define D(x) - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390782; cv=none; d=zohomail.com; s=zohoarc; b=Obeam37f87eQ8Vy0mWHsqNYLfqhimlyMVhroso8Y/J6aNJL+CPHJpRNtL0tGUe1zatMVggmd2QP3gwmDoNg3qHF9pvN6Y1qpmshm3csSkG+4HtpGwfTWs6JZSiQVsFL85q3LmowdlATi/QiZVw2KZUD/lNCm/m6w6WxU/MStYgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390782; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KOp/91/a2BIVMe1u/E83L0OjODEkWinQdZcmcUxF1f8=; b=EDh3kX8wg04gQmdfuAhMkXptUoiNzCIWhGkcJG9rlPY7ZG09WWJgR2wC8zx8N1mnrzAxfZExmrfLVnR4wgYZdywu8RnSq4ZoCGlh9ehPxrH5yjm9YAZ75TpKGcBgC1Vmwj413rFgi0z97VXtYRTBA52Q4uBYF8FK1hZ2N652Qas= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159839078215285.48738473130766; Tue, 25 Aug 2020 14:26:22 -0700 (PDT) Received: from localhost ([::1]:36074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgSS-0000wR-PX for importer@patchew.org; Tue, 25 Aug 2020 17:26:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3e-0007xX-0p for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:42 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:45872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3Y-0001qV-TZ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:41 -0400 Received: by mail-pf1-x42a.google.com with SMTP id k15so1821853pfc.12 for ; Tue, 25 Aug 2020 14:00:36 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KOp/91/a2BIVMe1u/E83L0OjODEkWinQdZcmcUxF1f8=; b=BftyHZ81nmXQu4GNpN+047U+NQ8+Obxyd+5taeX0NMuEXVfTchuuL2uOP8a2u/yb0R PYLFlFJVe6gb4ZFmXtQBAj9j830Yk4InMT3uZCmUkoMdqzC9JR9uzhA95jW6D434CrgY KGTXnKQQeDGAYUonY2d9Ybzp9jqM51dWMrNK0jRIg9rofee9nDxzvafRO7dvnxp2kyVR KjElWZhBCzFWJJ4QSqIPFy9A7RDQzkMZW04htH10JjGGtGYIGXG5s5TR8CJR5YkO+H7n YmIqRGFDb3r4YkoMFdHnwmdruwMy9Po3vE848s8HqVJPa8BqHTR0eTYNqsjxyUfwJDzP t3sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KOp/91/a2BIVMe1u/E83L0OjODEkWinQdZcmcUxF1f8=; b=I8/2uphtZnWscjvXOkzsXXd88BXJlllu/dGFTPO9nfcc08Z3UA/YKmMgsCQQX8H6V0 Gzu/iJfbgobZgDX+xvxf36/VnSeWNUAmKGnXv4L24Nh3hmIEHU0acKqYWsRvkG7zAYt7 VDFJ1jF+vZ91HHQ9WGJ9Ik4kVy4yMy1tJhhSGd4W3NYjxm4NYWG0NOVCaPEgJu9Uy7Ta t1j9fbbtwUlaTQCWHvIU3T1K2OxNuhFsaw/OR9rlW5I6jMaF+EBc0TzZaUp8grSylwNy FxIOwRRGfv2BNxcxFHL/oZkOh1FNKxSMgkN/U6ycw3xNza4KVLT4YjSduRppeYeuV41F 4vdg== X-Gm-Message-State: AOAM533/tPngS1B5ZQx3rEvrS5ag2da3hOfvlRD86JWGI1Q2ybc35Bsn AcfnkUdt9oJT/UO04BymCnWM102ymvqBTQ== X-Google-Smtp-Source: ABdhPJyjMyYXWhwn8YHj8hyQRMdQN22HEy6/x2J1eBXKNzzvqO8FpseiyOYmc+z4THTCQtPwkCc5AA== X-Received: by 2002:a63:d40d:: with SMTP id a13mr8115918pgh.232.1598389234536; Tue, 25 Aug 2020 14:00:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 33/77] target/microblaze: Remove LOG_DIS Date: Tue, 25 Aug 2020 13:59:06 -0700 Message-Id: <20200825205950.730499-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 78 +---------------------------------- 1 file changed, 1 insertion(+), 77 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 860859324a..133ec24870 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -33,14 +33,6 @@ #include "trace-tcg.h" #include "exec/log.h" =20 - -#define DISAS_MB 1 -#if DISAS_MB -# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -# define LOG_DIS(...) do { } while (0) -#endif - #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 @@ -205,10 +197,6 @@ static void dec_add(DisasContext *dc) k =3D dc->opcode & 4; c =3D dc->opcode & 2; =20 - LOG_DIS("add%s%s%s r%d r%d r%d\n", - dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", - dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -252,7 +240,6 @@ static void dec_sub(DisasContext *dc) cmp =3D (dc->imm & 1) && (!dc->type_b) && k; =20 if (cmp) { - LOG_DIS("cmp%s r%d, r%d ir=3D%x\n", u ? "u" : "", dc->rd, dc->ra, = dc->ir); if (dc->rd) { if (u) gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb= ]); @@ -262,9 +249,6 @@ static void dec_sub(DisasContext *dc) return; } =20 - LOG_DIS("sub%s%s r%d, r%d r%d\n", - k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); - /* Take care of the easy cases first. */ if (k) { /* k - keep carry, no need to update MSR. */ @@ -314,19 +298,16 @@ static void dec_pattern(DisasContext *dc) switch (mode) { case 0: /* pcmpbf. */ - LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->= rb]); break; case 2: - LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); } break; case 3: - LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); if (dc->rd) { tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); @@ -349,7 +330,6 @@ static void dec_and(DisasContext *dc) } =20 not =3D dc->opcode & (1 << 1); - LOG_DIS("and%s\n", not ? "n" : ""); =20 if (!dc->rd) return; @@ -367,7 +347,6 @@ static void dec_or(DisasContext *dc) return; } =20 - LOG_DIS("or r%d r%d r%d imm=3D%x\n", dc->rd, dc->ra, dc->rb, dc->imm); if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -379,7 +358,6 @@ static void dec_xor(DisasContext *dc) return; } =20 - LOG_DIS("xor r%d\n", dc->rd); if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } @@ -433,9 +411,6 @@ static void dec_msr(DisasContext *dc) if (clrset) { bool clr =3D extract32(dc->ir, 16, 1); =20 - LOG_DIS("msr%s r%d imm=3D%x\n", clr ? "clr" : "set", - dc->rd, dc->imm); - if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; @@ -478,7 +453,6 @@ static void dec_msr(DisasContext *dc) =20 sr &=3D 7; tmp_sr =3D tcg_const_i32(sr); - LOG_DIS("m%ss sr%d r%d imm=3D%x\n", to ? "t" : "f", sr, dc->ra, dc= ->imm); if (to) { gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); } else { @@ -491,7 +465,6 @@ static void dec_msr(DisasContext *dc) #endif =20 if (to) { - LOG_DIS("m%ss sr%x r%d imm=3D%x\n", to ? "t" : "f", sr, dc->ra, dc= ->imm); switch (sr) { case SR_PC: break; @@ -535,8 +508,6 @@ static void dec_msr(DisasContext *dc) break; } } else { - LOG_DIS("m%ss r%d sr%x imm=3D%x\n", to ? "t" : "f", dc->rd, sr, dc= ->imm); - switch (sr) { case SR_PC: tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); @@ -609,7 +580,6 @@ static void dec_mul(DisasContext *dc) subcode =3D dc->imm & 3; =20 if (dc->type_b) { - LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); return; } @@ -622,21 +592,17 @@ static void dec_mul(DisasContext *dc) tmp =3D tcg_temp_new_i32(); switch (subcode) { case 0: - LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: - LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: - LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: - LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc-= >rb]); break; default: @@ -652,7 +618,6 @@ static void dec_div(DisasContext *dc) unsigned int u; =20 u =3D dc->imm & 2;=20 - LOG_DIS("div\n"); =20 if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { return; @@ -688,10 +653,6 @@ static void dec_barrel(DisasContext *dc) imm_w =3D extract32(dc->imm, 6, 5); imm_s =3D extract32(dc->imm, 0, 5); =20 - LOG_DIS("bs%s%s%s r%d r%d r%d\n", - e ? "e" : "", - s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); - if (e) { if (imm_w + imm_s > 32 || imm_w =3D=3D 0) { /* These inputs have an undefined behavior. */ @@ -742,7 +703,6 @@ static void dec_bit(DisasContext *dc) /* src. */ t0 =3D tcg_temp_new_i32(); =20 - LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); tcg_gen_shli_i32(t0, cpu_msr_c, 31); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { @@ -755,8 +715,6 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); if (dc->rd) { if (op =3D=3D 0x41) @@ -766,11 +724,9 @@ static void dec_bit(DisasContext *dc) } break; case 0x60: - LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x61: - LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x64: @@ -778,12 +734,10 @@ static void dec_bit(DisasContext *dc) case 0x74: case 0x76: /* wdc. */ - LOG_DIS("wdc r%d\n", dc->ra); trap_userspace(dc, true); break; case 0x68: /* wic. */ - LOG_DIS("wic r%d\n", dc->ra); trap_userspace(dc, true); break; case 0xe0: @@ -796,12 +750,10 @@ static void dec_bit(DisasContext *dc) break; case 0x1e0: /* swapb */ - LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); break; case 0x1e2: /*swaph */ - LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: @@ -824,7 +776,6 @@ static inline void sync_jmpstate(DisasContext *dc) =20 static void dec_imm(DisasContext *dc) { - LOG_DIS("imm %x\n", dc->imm << 16); tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); dc->tb_flags |=3D IMM_FLAG; dc->clear_imm =3D 0; @@ -928,10 +879,6 @@ static void dec_load(DisasContext *dc) return; } =20 - LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); - t_sync_flags(dc); addr =3D tcg_temp_new(); compute_ldst_addr(dc, ea, addr); @@ -1039,9 +986,6 @@ static void dec_store(DisasContext *dc) =20 trap_userspace(dc, ea); =20 - LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", - ex ? "x" : "", - ea ? "ea" : ""); t_sync_flags(dc); /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); @@ -1184,7 +1128,6 @@ static void dec_bcc(DisasContext *dc) =20 cc =3D EXTRACT_FIELD(dc->ir, 21, 23); dslot =3D dc->ir & (1 << 25); - LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); =20 dc->delayed_branch =3D 1; if (dslot) { @@ -1217,8 +1160,6 @@ static void dec_br(DisasContext *dc) if (mbar =3D=3D 2 && dc->imm =3D=3D 4) { uint16_t mbar_imm =3D dc->rd; =20 - LOG_DIS("mbar %d\n", mbar_imm); - /* Data access memory barrier. */ if ((mbar_imm & 2) =3D=3D 0) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); @@ -1228,8 +1169,6 @@ static void dec_br(DisasContext *dc) if (mbar_imm & 16) { TCGv_i32 tmp_1; =20 - LOG_DIS("sleep\n"); - if (trap_userspace(dc, true)) { /* Sleep is a privileged instruction. */ return; @@ -1253,11 +1192,6 @@ static void dec_br(DisasContext *dc) return; } =20 - LOG_DIS("br%s%s%s%s imm=3D%x\n", - abs ? "a" : "", link ? "l" : "", - dc->type_b ? "i" : "", dslot ? "d" : "", - dc->imm); - dc->delayed_branch =3D 1; if (dslot) { dec_setup_dslot(dc); @@ -1363,16 +1297,12 @@ static void dec_rts(DisasContext *dc) dec_setup_dslot(dc); =20 if (i_bit) { - LOG_DIS("rtid ir=3D%x\n", dc->ir); dc->tb_flags |=3D DRTI_FLAG; } else if (b_bit) { - LOG_DIS("rtbd ir=3D%x\n", dc->ir); dc->tb_flags |=3D DRTB_FLAG; } else if (e_bit) { - LOG_DIS("rted ir=3D%x\n", dc->ir); dc->tb_flags |=3D DRTE_FLAG; - } else - LOG_DIS("rts ir=3D%x\n", dc->ir); + } =20 dc->jmp =3D JMP_INDIRECT; tcg_gen_movi_i32(cpu_btaken, 1); @@ -1505,9 +1435,6 @@ static void dec_stream(DisasContext *dc) TCGv_i32 t_id, t_ctrl; int ctrl; =20 - LOG_DIS("%s%s imm=3D%x\n", dc->rd ? "get" : "put", - dc->type_b ? "" : "d", dc->imm); - if (trap_userspace(dc, true)) { return; } @@ -1565,7 +1492,6 @@ static inline void decode(DisasContext *dc, uint32_t = ir) int i; =20 dc->ir =3D ir; - LOG_DIS("%8.8x\t", dc->ir); =20 if (ir =3D=3D 0) { trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); @@ -1744,10 +1670,8 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPU= State *cs) =20 static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) { -#ifdef DEBUG_DISAS qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); log_target_disas(cs, dcb->pc_first, dcb->tb->size); -#endif } =20 static const TranslatorOps mb_tr_ops =3D { --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390631; cv=none; d=zohomail.com; s=zohoarc; b=UvtE/1t+eCVfMM1QbQvMGR1D9t+BSxjSRZnwVdsTrJqUxQo1Dh+pysXVIhRJlucXfS8NYFavOwyGrNOhK2mbKFlmf8QZfAc3FBS7dUIwUE+vVItjJc8QVbZG9D8Zz/s+m7oSokMolFVXr9UO+TVkZYY9Sj9lwqlH+O9vcT/mcoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390631; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=D1BnS1GQ51WrLIc/SbVeGPXDqQfgkX10QugH6/vfs46DReBDSGBH4dR8BdnfKibxlLhiMLe6uQgW1dJWNVryQhQpyBCGtOWR+HD3UgOVgno8sbaeNnheU991AQ26uuCbKaZeMRWceJAjrmt/ZxidZ+sncWzW7nTDuvweNJhc8q4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390631218969.5343968941028; Tue, 25 Aug 2020 14:23:51 -0700 (PDT) Received: from localhost ([::1]:51890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgQ1-0004Gy-Lp for importer@patchew.org; Tue, 25 Aug 2020 17:23:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3c-0007uR-Bi for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:40 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:40897) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3Z-0001qe-Oe for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:39 -0400 Received: by mail-pj1-x1034.google.com with SMTP id kx11so117296pjb.5 for ; Tue, 25 Aug 2020 14:00:37 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=qvup682KlHmC6NHpdjStw6DoA6H7z+FFELiqX1kk3MhAe3NdEI4K856PV9u8uqE3Yq lZQrTdSVRGxEawqC0LTxRiKVq+P5iEOxTK/3sBBFnrPSVuOLT9qSeI93LTE/pGQBOdSQ xBvUv05slXAMSHJ9kHRUWuyf6o71LzbJETBfzTL+lEnTVjU7dzlyWrkFGCtIobPRu2a3 +M0IGDGT1f6mom9jbShcNMHwp7U9mspy6rIhaiCzM8tGnrxw32HDZLPb0FZLXFM66lzp mVDR92iTE6Sa9SyeYSHbj1N+4+hoQVxrUZhQbtaW14GzyXNScAxEnvS9L4c/YdtKSB6h Hoig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wse7zD0pJo6WjEez5LvLZIudG6q/fbgb3bbbGW9ilgU=; b=rp7E+rJqNXmxo9uc8UDiImpWAt62zWvVATqJ77/p4DqLaiJBkkBejK15o/JNSi8Jxv UUL2I1sQGHKMOeeOtNYp2sDVPUaIbzegvO2kmb+3s++lQieG0iUCyNWU9WPj1OECSUtT Vy33WSposO4XXlJLk77bUmOe9xEoBDv7ugwuu8iBr+Zh19CaV71pt3Sz+GxntnS/d9yi SVGHNcDsI3Dkswkx5tJSkyuyPF2vbawrmoWpdh7nKHEIgCGsgM1VykBS+SLy+xe5ALFI YcIhrzb7Mt1xKU6hVwukiJhoi4Vo1CtqsVMPMDBr6l0tITw/WRJ2AyXpdFoTTlkg4Rpm Z4jQ== X-Gm-Message-State: AOAM531byIW58JfGCDCmWBMjDjXDAZMPi3Ve7Oe49zFd7c4BovbpuiRC iEDnnbJftg6ln21u0vS+jId6NyXEF2/jWQ== X-Google-Smtp-Source: ABdhPJz4nHZ9fPnjKq8LNvUpv7voVQ8QEWrFWVB/JlSjN2zeZjkZPm8CZp0Y61igN+gWwxC8DZa3tw== X-Received: by 2002:a17:90a:a101:: with SMTP id s1mr2841013pjp.205.1598389235827; Tue, 25 Aug 2020 14:00:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 34/77] target/microblaze: Ensure imm constant is always available Date: Tue, 25 Aug 2020 13:59:07 -0700 Message-Id: <20200825205950.730499-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 111 ++++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 46 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7066878ac7..013858b8e0 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env= , target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; - *cs_base =3D 0; *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 133ec24870..65ce8f3cd6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -61,6 +61,7 @@ typedef struct DisasContext { /* Decoder. */ int type_b; uint32_t ir; + uint32_t ext_imm; uint8_t opcode; uint8_t rd, ra, rb; uint16_t imm; @@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool con= d) return cond_user; } =20 -/* True if ALU operand b is a small immediate that may deserve - faster treatment. */ -static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) +static int32_t dec_alu_typeb_imm(DisasContext *dc) { - /* Immediate insn without the imm prefix ? */ - return dc->type_b && !(dc->tb_flags & IMM_FLAG); + tcg_debug_assert(dc->type_b); + if (dc->tb_flags & IMM_FLAG) { + return dc->ext_imm | dc->imm; + } else { + return (int16_t)dc->imm; + } } =20 static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) { if (dc->type_b) { - if (dc->tb_flags & IMM_FLAG) - tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm); - else - tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm)); + tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); return &cpu_imm; - } else - return &cpu_R[dc->rb]; + } + return &cpu_R[dc->rb]; } =20 static void dec_add(DisasContext *dc) @@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc) =20 static void dec_imm(DisasContext *dc) { - tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); + dc->ext_imm =3D dc->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); dc->tb_flags |=3D IMM_FLAG; dc->clear_imm =3D 0; } =20 static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { - bool extimm =3D dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ bool stackprot =3D false; TCGv_i32 t32; @@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc,= bool ea, TCGv t) } /* Immediate. */ t32 =3D tcg_temp_new_i32(); - if (!extimm) { - tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); - } else { - tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); tcg_gen_extu_i32_tl(t, t32); tcg_temp_free_i32(t32); =20 @@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc) dec_setup_dslot(dc); } =20 - if (dec_alu_op_b_is_small_imm(dc)) { - int32_t offset =3D (int32_t)((int16_t)dc->imm); /* sign-extend. */ - - tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset); + if (dc->type_b) { dc->jmp =3D JMP_DIRECT_CC; - dc->jmp_pc =3D dc->base.pc_next + offset; + dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp =3D JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); } @@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc) return; } =20 + if (abs && link && !dslot) { + if (dc->type_b) { + /* BRKI */ + uint32_t imm =3D dec_alu_typeb_imm(dc); + if (trap_userspace(dc, imm !=3D 8 && imm !=3D 0x18)) { + return; + } + } else { + /* BRK */ + if (trap_userspace(dc, true)) { + return; + } + } + } + dc->delayed_branch =3D 1; if (dslot) { dec_setup_dslot(dc); } - if (link && dc->rd) + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); + } =20 - dc->jmp =3D JMP_INDIRECT; if (abs) { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); - if (link && !dslot) { - if (!(dc->tb_flags & IMM_FLAG) && - (dc->imm =3D=3D 8 || dc->imm =3D=3D 0x18)) { + if (dc->type_b) { + uint32_t dest =3D dec_alu_typeb_imm(dc); + + dc->jmp =3D JMP_DIRECT; + dc->jmp_pc =3D dest; + tcg_gen_movi_i32(cpu_btarget, dest); + if (link && !dslot) { + switch (dest) { + case 8: + case 0x18: + gen_raise_exception_sync(dc, EXCP_BREAK); + break; + case 0: + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + } + } + } else { + dc->jmp =3D JMP_INDIRECT; + tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); + if (link && !dslot) { gen_raise_exception_sync(dc, EXCP_BREAK); } - if (dc->imm =3D=3D 0) { - if (trap_userspace(dc, true)) { - return; - } - gen_raise_exception_sync(dc, EXCP_DEBUG); - } } + } else if (dc->type_b) { + dc->jmp =3D JMP_DIRECT; + dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { - if (dec_alu_op_b_is_small_imm(dc)) { - dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D dc->base.pc_next + (int32_t)((int16_t)dc->imm); - } else { - tcg_gen_movi_i32(cpu_btaken, 1); - tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_n= ext); - } + dc->jmp =3D JMP_INDIRECT; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); } + tcg_gen_movi_i32(cpu_btaken, 1); } =20 static inline void do_rti(DisasContext *dc) @@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; + dc->ext_imm =3D dc->base.tb->cs_base; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); @@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 dc->clear_imm =3D 1; decode(dc, cpu_ldl_code(env, dc->base.pc_next)); - if (dc->clear_imm) { + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &=3D ~IMM_FLAG; + tcg_gen_discard_i32(cpu_imm); } dc->base.pc_next +=3D 4; =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390678; cv=none; d=zohomail.com; s=zohoarc; b=C0IeTUpmU0z6GJsOiZFtwUoITbZyRwVPFTA8xuYh6LJ7lgBNu/EipxTL+l1AlJs+ZroOHSrpcOeX16A9u1zgqRiuoLzsjh2sKvisa42ys0GIlCnn5R/O9c2/Zkkb37MP5D+AQDrxXICI6D2gheBchYRx/vYsF7ON3azFIK5Qsew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390678; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=FbvKuapm41QhP3xbMoCc6PTDReK/ZHtUo+ZYMSpkK4NTweOLNizHvR/oOx21dIYlfJiS52K0ANxE8RSyG1mL8x344+RIQ9USRz5icSZ2iE+KvAP0jn3Jphw7Om+VPLytlnRX6GDPVUR9+W1FCd4Cp264iEKDBGiZEQ3koDijAbY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390678028912.261275535753; Tue, 25 Aug 2020 14:24:38 -0700 (PDT) Received: from localhost ([::1]:55870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgQm-0005tR-NX for importer@patchew.org; Tue, 25 Aug 2020 17:24:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3d-0007vl-0v for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:41 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:36391) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3a-0001qp-Oz for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:40 -0400 Received: by mail-pj1-x1041.google.com with SMTP id q1so127786pjd.1 for ; Tue, 25 Aug 2020 14:00:38 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=JirQcFosAldNZ6rO3H280is1x7IULX1PDBdPGd8uRJlUHzt6usQsJH4G2C84x3Dqf5 PIJnchcgAlY1gX9d766RFTcyWGdA8uL1xcje11qb4LJzA7s7YtVI+gextsJNbIslVILB Iln98xYoWhJmuOhEXeNV+kuRRJU8QfdfePFFG5mTupp+dNBrK4mGmgcmnVV+DiLDcd49 XRYvgWFVVuN9D/twJTqSR8d52JT9BvaDiPSy4Kx+RPgYEhfSMk7ufnb4+MfbxG2IPcAa 8ccHya6h9jHcVU29TNiknuLdgcn1gglsYlTg7LuJu7lrJYQZONEgkYyE7XWfrO2qUgrw a7pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kEx0UptQCrtmnph6sgV6tFoh7UCNGXW3aCpI+f1tQA=; b=BfpjMmrNVvM8mbEpvwEyexnau48jZ/K2Cz4jCREjnHDomXq21Q0jDYKcei5ecR44iw 8KPJmxIB6dgEM8F1YKEmT2uBsf7Z3uDZHTnG1kTe6wkCUtiP37RunLxjy1CvtAHlkT7o TxG4bs51IJZpomD3JCw55K2yMmkVlj6W1lbtPHB+SeSLN0t9YMEvo/WtzXYZ4IiTb0ha 73NszmMhhes1acn3NW2m+W1yYohqVYmbWNHswSRQDPaGumYo4EZk0QS5tCAAp0jSWz/2 gQNu19sd91WAbYiuGie/hWYFy5nCty5GCLriurJSX8ukvyGV+tsGBs5bX7BGTccktFgS sEoA== X-Gm-Message-State: AOAM532i3+cr2mBD9ixltLGs8qiw8vrVKCld62DyPS8aa0QTHVjJe9yC ZevtSFhW1xn6J85tbNSLwOV8x0uUOnw6dQ== X-Google-Smtp-Source: ABdhPJwuLlJ8t9RgDEIv81vfPjWICQjTgUAwio3om+FZ90Sq/Iwgaz7OyXK+kwHwpviVWMqHugVGdQ== X-Received: by 2002:a17:90b:1108:: with SMTP id gi8mr2960746pjb.7.1598389237031; Tue, 25 Aug 2020 14:00:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 35/77] target/microblaze: Add decodetree infrastructure Date: Tue, 25 Aug 2020 13:59:08 -0700 Message-Id: <20200825205950.730499-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++++++++++++++++++ target/microblaze/translate.c | 11 +++++++++-- target/microblaze/meson.build | 3 +++ 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 target/microblaze/insns.decode diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode new file mode 100644 index 0000000000..1ed9ca0731 --- /dev/null +++ b/target/microblaze/insns.decode @@ -0,0 +1,18 @@ +# +# MicroBlaze instruction decode definitions. +# +# Copyright (c) 2020 Richard Henderson +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 65ce8f3cd6..e624093745 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -81,6 +81,9 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; =20 +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1506,7 +1509,7 @@ static struct decoder_info { {{0, 0}, dec_null} }; =20 -static inline void decode(DisasContext *dc, uint32_t ir) +static void old_decode(DisasContext *dc, uint32_t ir) { int i; =20 @@ -1584,6 +1587,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); CPUMBState *env =3D cs->env_ptr; + uint32_t ir; =20 /* TODO: This should raise an exception, not terminate qemu. */ if (dc->base.pc_next & 3) { @@ -1592,7 +1596,10 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) } =20 dc->clear_imm =3D 1; - decode(dc, cpu_ldl_code(env, dc->base.pc_next)); + ir =3D cpu_ldl_code(env, dc->base.pc_next); + if (!decode(dc, ir)) { + old_decode(dc, ir); + } if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &=3D ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index b8fe4afe61..639c3f73a8 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -1,4 +1,7 @@ +gen =3D decodetree.process('insns.decode') + microblaze_ss =3D ss.source_set() +microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', 'gdbstub.c', --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598389865; cv=none; d=zohomail.com; s=zohoarc; b=Axi2UmNBxmPQqb7GvgYivy+JfXMjCe7arRG4rwMpT6GPS6zS3iF3TK0Iz38zW27Ej2n9+cjOo7L6PBN/IO17hrTHLiX9zpD71BsJlAxM4gHIPdIwX2+X71dGfkuTQl0oA5ytt8NCu2eCbNYJzU3RWw9niRQyslPd/uF/8A1mcu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598389865; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3tIkPYiOnQsOVuosyAmz/ThXo6OaMIkZVJ4NrFAYJ24=; b=ZAmOKiVggNoyFPi3PAoNC7L4ykjmCnThzYs3BYOfYeiSLVfxwaIxJJZcCNhfARs72TtkSZmafIoBWU89m7Rm417n26Tvl6iAPHi3qEZCq+Xxrxy/hlWHtKnnTjSJeTblgEg+EKSuRjQFstV9mPzsN9v9wCTIBfCnmANYD1AlmWQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598389865985360.271665593355; Tue, 25 Aug 2020 14:11:05 -0700 (PDT) Received: from localhost ([::1]:51264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgDg-00069M-JC for importer@patchew.org; Tue, 25 Aug 2020 17:11:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3f-0007z1-32 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:43 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:40609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3c-0001r0-Gg for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:42 -0400 Received: by mail-pf1-x434.google.com with SMTP id k18so8290128pfp.7 for ; Tue, 25 Aug 2020 14:00:39 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 21 ++++ target/microblaze/translate.c | 185 +++++++++++++++++++++++++-------- 2 files changed, 165 insertions(+), 41 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 1ed9ca0731..c62f826bcc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -16,3 +16,24 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&typea rd ra rb +&typeb rd ra imm + +# Include any IMM prefix in the value reported. +%extimm 0:s16 !function=3Dtypeb_imm + +@typea ...... rd:5 ra:5 rb:5 ... .... .... &typea +@typeb ...... rd:5 ra:5 ................ &typeb imm=3D%exti= mm + +### + +add 000000 ..... ..... ..... 000 0000 0000 @typea +addc 000010 ..... ..... ..... 000 0000 0000 @typea +addk 000100 ..... ..... ..... 000 0000 0000 @typea +addkc 000110 ..... ..... ..... 000 0000 0000 @typea + +addi 001000 ..... ..... ................ @typeb +addic 001010 ..... ..... ................ @typeb +addik 001100 ..... ..... ................ @typeb +addikc 001110 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e624093745..c3cc4db629 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; =20 + TCGv_i32 r0; + bool r0_set; + /* Decoder. */ int type_b; uint32_t ir; @@ -81,6 +84,14 @@ typedef struct DisasContext { int abort_at_next_insn; } DisasContext; =20 +static int typeb_imm(DisasContext *dc, int x) +{ + if (dc->tb_flags & IMM_FLAG) { + return deposit32(dc->ext_imm, 0, 16, x); + } + return x; +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" =20 @@ -176,11 +187,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) static int32_t dec_alu_typeb_imm(DisasContext *dc) { tcg_debug_assert(dc->type_b); - if (dc->tb_flags & IMM_FLAG) { - return dc->ext_imm | dc->imm; - } else { - return (int16_t)dc->imm; - } + return typeb_imm(dc, (int16_t)dc->imm); } =20 static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) @@ -192,46 +199,134 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *d= c) return &cpu_R[dc->rb]; } =20 -static void dec_add(DisasContext *dc) +static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { - unsigned int k, c; - TCGv_i32 cf; - - k =3D dc->opcode & 4; - c =3D dc->opcode & 2; - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd =3D=3D r0, it's a nop. */ - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(d= c))); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } + if (likely(reg !=3D 0)) { + return cpu_R[reg]; + } + if (!dc->r0_set) { + if (dc->r0 =3D=3D NULL) { + dc->r0 =3D tcg_temp_new_i32(); } - return; + tcg_gen_movi_i32(dc->r0, 0); + dc->r0_set =3D true; } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. */ - cf =3D tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 0); - } - - gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); + return dc->r0; } =20 +static TCGv_i32 reg_for_write(DisasContext *dc, int reg) +{ + if (likely(reg !=3D 0)) { + return cpu_R[reg]; + } + if (dc->r0 =3D=3D NULL) { + dc->r0 =3D tcg_temp_new_i32(); + } + return dc->r0; +} + +static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, rb; + + if (arg->rd =3D=3D 0 && !side_effects) { + return true; + } + + rd =3D reg_for_write(dc, arg->rd); + ra =3D reg_for_read(dc, arg->ra); + rb =3D reg_for_read(dc, arg->rb); + fn(rd, ra, rb); + return true; +} + +static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effec= ts, + void (*fni)(TCGv_i32, TCGv_i32, int32_t)) +{ + TCGv_i32 rd, ra; + + if (arg->rd =3D=3D 0 && !side_effects) { + return true; + } + + rd =3D reg_for_write(dc, arg->rd); + ra =3D reg_for_read(dc, arg->ra); + fni(rd, ra, arg->imm); + return true; +} + +static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effec= ts, + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra, imm; + + if (arg->rd =3D=3D 0 && !side_effects) { + return true; + } + + rd =3D reg_for_write(dc, arg->rd); + ra =3D reg_for_read(dc, arg->ra); + imm =3D tcg_const_i32(arg->imm); + + fn(rd, ra, imm); + + tcg_temp_free_i32(imm); + return true; +} + +#define DO_TYPEA(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return do_typea(dc, a, SE, FN); } + +#define DO_TYPEBI(NAME, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_imm(dc, a, SE, FNI); } + +#define DO_TYPEBV(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return do_typeb_val(dc, a, SE, FN); } + +/* No input carry, but output carry. */ +static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero =3D tcg_const_i32(0); + + tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); + + tcg_temp_free_i32(zero); +} + +/* Input and output carry. */ +static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(zero); +} + +/* Input carry, but no output carry. */ +static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_add_i32(out, ina, inb); + tcg_gen_add_i32(out, out, cpu_msr_c); +} + +DO_TYPEA(add, true, gen_add) +DO_TYPEA(addc, true, gen_addc) +DO_TYPEA(addk, false, tcg_gen_add_i32) +DO_TYPEA(addkc, true, gen_addkc) + +DO_TYPEBV(addi, true, gen_add) +DO_TYPEBV(addic, true, gen_addc) +DO_TYPEBI(addik, false, tcg_gen_addi_i32) +DO_TYPEBV(addikc, true, gen_addkc) + static void dec_sub(DisasContext *dc) { unsigned int u, cmp, k, c; @@ -1488,7 +1583,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_ADD, dec_add}, {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, @@ -1552,6 +1646,8 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; dc->ext_imm =3D dc->base.tb->cs_base; + dc->r0 =3D NULL; + dc->r0_set =3D false; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); @@ -1600,6 +1696,13 @@ static void mb_tr_translate_insn(DisasContextBase *d= cb, CPUState *cs) if (!decode(dc, ir)) { old_decode(dc, ir); } + + if (dc->r0) { + tcg_temp_free_i32(dc->r0); + dc->r0 =3D NULL; + dc->r0_set =3D false; + } + if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags &=3D ~IMM_FLAG; tcg_gen_discard_i32(cpu_imm); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=52+gLLOfsTHLGvsiEqn5D8Con58Yn2k7gp1YJlK0G5Q=; b=hTvvp9yj2N8foHkD2ug5g7F5FI8EQ9jfKMb0VnZabua3pAvWRVG/ajWmf7Q4yx9kBV Ui58laJka1mGYGI12mDvtWrkIyVGvMkZDCzscIwELzCs0CmUlfQrpGlhWLjL/yWptrE8 ZerDtpSu7T+UgArhOPWA7rxSb7QKNg1CbSMOIviN81wWuYcv2QY1uQCqq+9dqtkjWtJJ 2Rg5zVWfnu1xGx1LiizdxwNDp8F4qWo3K8zY7M1klzOpolxEvnGatOiu+plwBQ23vn1J 5LvY1tYoZ9qp/6DeurdlJrqQMYP8rxIT47dkn/FnZ5Mt4fJFj+HMfxYhl158Oog+lZfG IKQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=52+gLLOfsTHLGvsiEqn5D8Con58Yn2k7gp1YJlK0G5Q=; b=iivvUwOdlghc5W3OAArAXvECmXgDDl2TW+dDPFR35DSoZf7EBlqKnvM80BZtPXxvnC NcqEWJ0xVEhUsRzvKq5UcQ9TG8GOZi4Pzwb+AGx+atRYHGJv8z0bV8reLB8FGnyHBsGg 4JHO6IvglMp7hLGyfCyqeaqdacMrDk2CfsvZX3WstBaOHsHsoE7KTQ/lfhOLCFlWWT36 lWutizhhAk0iUILUCb3j86orr68Odq48f/fI0UecD6BHNjKIEKoKiAdEGaesquNXjPJ3 K5ry7+dpLH0GbBBJ3JujzpbGM35mcKsO5zEeW7564b1+s3uUdmP+mFlw6vYIFDsWXRFp 7Dyg== X-Gm-Message-State: AOAM5322GtwUVcKR9Sdlq6j0reRq8abgRI8bVYCjEzdBnvOd9inS/ru+ CaUY2xX/XUy0N7SelK3O2Ka2DzD73T5y5Q== X-Google-Smtp-Source: ABdhPJxu2Gt6lrwjKxglnd6s2x0liq681n4iwUjMNgD9etPrVOB15+apZMJ0XqWYZJ11X1UUVxYXBw== X-Received: by 2002:a17:90b:1b47:: with SMTP id nv7mr2886233pjb.128.1598389239342; Tue, 25 Aug 2020 14:00:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 37/77] target/microblaze: Convert dec_sub to decodetree Date: Tue, 25 Aug 2020 13:59:10 -0700 Message-Id: <20200825205950.730499-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 1 - target/microblaze/insns.decode | 13 +++++ target/microblaze/op_helper.c | 16 ----- target/microblaze/translate.c | 104 ++++++++++++++++----------------- 4 files changed, 62 insertions(+), 72 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 9309142f8d..988abf7661 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) =20 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index c62f826bcc..3f5f7b1852 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -37,3 +37,16 @@ addi 001000 ..... ..... ................ = @typeb addic 001010 ..... ..... ................ @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb + +cmp 000101 ..... ..... ..... 000 0000 0001 @typea +cmpu 000101 ..... ..... ..... 000 0000 0011 @typea + +rsub 000001 ..... ..... ..... 000 0000 0000 @typea +rsubc 000011 ..... ..... ..... 000 0000 0000 @typea +rsubk 000101 ..... ..... ..... 000 0000 0000 @typea +rsubkc 000111 ..... ..... ..... 000 0000 0000 @typea + +rsubi 001001 ..... ..... ................ @typeb +rsubic 001011 ..... ..... ................ @typeb +rsubik 001101 ..... ..... ................ @typeb +rsubikc 001111 ..... ..... ................ @typeb diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index decdca0fd8..9bb6a2ad76 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,17 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t in= dex) cpu_loop_exit(cs); } =20 -static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) -{ - uint32_t cout =3D 0; - - if ((b =3D=3D ~0) && cin) - cout =3D 1; - else if ((~0 - a) < (b + cin)) - cout =3D 1; - return cout; -} - uint32_t helper_cmp(uint32_t a, uint32_t b) { uint32_t t; @@ -100,11 +89,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b) return t; } =20 -uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) -{ - return compute_carry(a, b, cf); -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu =3D env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c3cc4db629..98050f64b7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,63 +327,58 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) =20 -static void dec_sub(DisasContext *dc) +DO_TYPEA(cmp, false, gen_helper_cmp) +DO_TYPEA(cmpu, false, gen_helper_cmpu) + +/* No input carry, but output carry. */ +static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { - unsigned int u, cmp, k, c; - TCGv_i32 cf, na; - - u =3D dc->imm & 2; - k =3D dc->opcode & 4; - c =3D dc->opcode & 2; - cmp =3D (dc->imm & 1) && (!dc->type_b) && k; - - if (cmp) { - if (dc->rd) { - if (u) - gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb= ]); - else - gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]= ); - } - return; - } - - /* Take care of the easy cases first. */ - if (k) { - /* k - keep carry, no need to update MSR. */ - /* If rd =3D=3D r0, it's a nop. */ - if (dc->rd) { - tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->= ra]); - - if (c) { - /* c - Add carry into the result. */ - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c); - } - } - return; - } - - /* From now on, we can assume k is zero. So we need to update MSR. */ - /* Extract carry. And complement a into na. */ - cf =3D tcg_temp_new_i32(); - na =3D tcg_temp_new_i32(); - if (c) { - tcg_gen_mov_i32(cf, cpu_msr_c); - } else { - tcg_gen_movi_i32(cf, 1); - } - - /* d =3D b + ~a + c. carry defaults to 1. */ - tcg_gen_not_i32(na, cpu_R[dc->ra]); - - gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf); - if (dc->rd) { - tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); - tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); - } - tcg_temp_free_i32(cf); - tcg_temp_free_i32(na); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); + tcg_gen_sub_i32(out, inb, ina); } =20 +/* Input and output carry. */ +static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_not_i32(tmp, ina); + tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); + tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); + + tcg_temp_free_i32(zero); + tcg_temp_free_i32(tmp); +} + +/* No input or output carry. */ +static void gen_rsubk(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_sub_i32(out, inb, ina); +} + +/* Input carry, no output carry. */ +static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 nota =3D tcg_temp_new_i32(); + + tcg_gen_not_i32(nota, ina); + tcg_gen_add_i32(out, inb, nota); + tcg_gen_add_i32(out, out, cpu_msr_c); + + tcg_temp_free_i32(nota); +} + +DO_TYPEA(rsub, true, gen_rsub) +DO_TYPEA(rsubc, true, gen_rsubc) +DO_TYPEA(rsubk, false, gen_rsubk) +DO_TYPEA(rsubkc, true, gen_rsubkc) + +DO_TYPEBV(rsubi, true, gen_rsub) +DO_TYPEBV(rsubic, true, gen_rsubc) +DO_TYPEBV(rsubik, false, gen_rsubk) +DO_TYPEBV(rsubikc, true, gen_rsubkc) + static void dec_pattern(DisasContext *dc) { unsigned int mode; @@ -1583,7 +1578,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_SUB, dec_sub}, {DEC_AND, dec_and}, {DEC_XOR, dec_xor}, {DEC_OR, dec_or}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390772; cv=none; d=zohomail.com; s=zohoarc; b=Vc01sO0Q4psP/zLQMUiUdn32hD9NkJ/tBjb4/Ju0g3T1NuBTuNEwTfn06XKNjT7X/p9Q9Lt9kon84oQueKgAF+G6ReXYNOnUeaIwv/ajgHGT/q05kCsBTAajojfhrS7m3+JGFxSgOBNuo58GXwov5INKdAMTATSt4X9els4jV4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390772; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=028+vI/58nZnbjOmGLeS9QgMrm8aOm1Pu2VJuR4D8gY=; b=bTC90YinIVZIHj6rVn3vGmhtUqUQMjNMcPeG/sGb42UK0rkyE6i1xQO6lzzc4Ghqf4/syvlzjUVnXsVtaJY2iQE0VY0yp7BejFuzzKDU9MJlAFZsbIsIeVNTO1+D12vi2wztFSPNfy14Hhi4SxgBnVTQAhgfyNDL1hf3XgE2Mqo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390772366405.93206750421496; Tue, 25 Aug 2020 14:26:12 -0700 (PDT) Received: from localhost ([::1]:35198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgSJ-0000Vw-2z for importer@patchew.org; Tue, 25 Aug 2020 17:26:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3g-00082t-J5 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:44 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35173) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3e-0001rJ-Kl for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:44 -0400 Received: by mail-pg1-x542.google.com with SMTP id o5so7679541pgb.2 for ; Tue, 25 Aug 2020 14:00:42 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=028+vI/58nZnbjOmGLeS9QgMrm8aOm1Pu2VJuR4D8gY=; b=A857IRIF5+n8uvaxlKuvmwHYD8/DlykEw7qpdmXUw/ryNi+lKjYoCMYBZJDyVGTzFl YFAp/hC8DduUE2sffbfRP3gVKLEtK4inRGZ4RatA0HJXUigDbs6wB47P4ZSK6qx0G18I 7Rq73sjcZOoYqtmtKNQxbbnKpmrUu7hmBMWXeNclgsthlXGMtSvxUY7IXXMaqUk1zvma THrK3KUsd0+0+RFmNs7Xz5kCLCHqgS4NjpugyttU0N5wsPZsxpo8jEmP9kYdjFH7gzvk SdB8W/7KjM9UMNSnI916kCrbUO0MoD4cXMNluYmqrZJ8sg0zcTrdVU4n0xRhf26YQVMQ x5Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=028+vI/58nZnbjOmGLeS9QgMrm8aOm1Pu2VJuR4D8gY=; b=IhbAcGAwvR7tuZBUookBUHdNRz27glSFM0UYQGudAjevBZFWmgex6+piCoIqygdFnG iCi60sca5xq0HM6ilCiogHg8YnrNiWovtxFw8nxhK+kqfdxV1aziSluCqMgm78kn5eQV UlIwzKynxueOZwDcZTK0YUj9tmeTXxZDgDYVdk3jtXGYR/3dpeBtilrh1lNb8R3vH71G /mnoiY5ulAo2zsmP+yyLudhong+JfjVZ+y5xgi+RjNT2ucHOfZkz2upjzwbnpEp9YmEt gu2MI4B40h6iR+bYnUllCU19pC05xnzqEqmhW0r3cDoyP+gt8J20ItEMGGSgM4+wEqzZ r4sA== X-Gm-Message-State: AOAM531muZxu2bigT4VW1q2qYV0b8CQNfgl00hx8Jyou71mknv0ticCX 7X/rcUpsmKLiTwXuvQT3IYyaX+jZQc6L8A== X-Google-Smtp-Source: ABdhPJy5waXekXkk/vfJY+MGcmTsUvs647KFVIh0RYDwI60R3F2LKcsK7kcPagVbLEUkW2Zpd34HCg== X-Received: by 2002:a62:1d0:: with SMTP id 199mr9523009pfb.189.1598389240500; Tue, 25 Aug 2020 14:00:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline Date: Tue, 25 Aug 2020 13:59:11 -0700 Message-Id: <20200825205950.730499-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These are simple enough operations; we do not need to call an out-of-line helper. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 -- target/microblaze/op_helper.c | 20 -------------------- target/microblaze/translate.c | 24 ++++++++++++++++++++++-- 3 files changed, 22 insertions(+), 24 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 988abf7661..6f7f96421f 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,6 +1,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) -DEF_HELPER_2(cmp, i32, i32, i32) -DEF_HELPER_2(cmpu, i32, i32, i32) =20 DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 9bb6a2ad76..f976d112eb 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t in= dex) cpu_loop_exit(cs); } =20 -uint32_t helper_cmp(uint32_t a, uint32_t b) -{ - uint32_t t; - - t =3D b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t =3D (t & 0x7fffffff) | (b & 0x80000000); - return t; -} - -uint32_t helper_cmpu(uint32_t a, uint32_t b) -{ - uint32_t t; - - t =3D b + ~a + 1; - if ((b & 0x80000000) ^ (a & 0x80000000)) - t =3D (t & 0x7fffffff) | (a & 0x80000000); - return t; -} - static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { MicroBlazeCPU *cpu =3D env_archcpu(env); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 98050f64b7..ce91645f05 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -327,8 +327,28 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) =20 -DO_TYPEA(cmp, false, gen_helper_cmp) -DO_TYPEA(cmpu, false, gen_helper_cmpu) +static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt =3D tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 lt =3D tcg_temp_new_i32(); + + tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); + tcg_gen_sub_i32(out, inb, ina); + tcg_gen_deposit_i32(out, out, lt, 31, 1); + tcg_temp_free_i32(lt); +} + +DO_TYPEA(cmp, false, gen_cmp) +DO_TYPEA(cmpu, false, gen_cmpu) =20 /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390894; cv=none; d=zohomail.com; s=zohoarc; b=QWEfX27x16Ta+6Og5bl5Hr9Qek+SLs3y8ZXyhqByJJiFWPqSCzq2ypFSzlR7BgVn/bAPdSKyC1NIOTdZdxY6ow+6hr1jAfM822VJe+sto/i15skCGTvEjbValwlnZmgSBR6uvnN5DNM/8mfCAhqvHi+atXBreBdI5OpW2yg573I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390894; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SnN2rcoH8SEue8/YmUSsyA4G1cGVPVXaIp+iYJ1qNQA=; b=bbRaZ17FRqggkpfxHQ6MaF+MxAMNTkzPopAwXbwABTW9yxYfcZa44ODh1HVc1BuEbzb8grZQ++TW1uAj971iTPiaWvmta1h1zNn+nPOvKsxh5iExKoB71MsnGLxePZX9vTmscQ4HmZdh1P4GWxQTYhXQKgz2u6GeajmIgCyxDXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390894621690.8313042271417; Tue, 25 Aug 2020 14:28:14 -0700 (PDT) Received: from localhost ([::1]:44266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgUH-0004GX-5C for importer@patchew.org; Tue, 25 Aug 2020 17:28:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3h-00085K-Lr for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:45 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:35884) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3f-0001rQ-Eh for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:45 -0400 Received: by mail-pf1-x436.google.com with SMTP id m8so8306626pfh.3 for ; Tue, 25 Aug 2020 14:00:42 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SnN2rcoH8SEue8/YmUSsyA4G1cGVPVXaIp+iYJ1qNQA=; b=tqaRjjtsWSmUHQ6a/EJNgzvWcL9kP3ImCmobt/Zy8ILxkhecloVzdTMtcx5+s0Cn1y 76wHqHkCihr3eIKAuADSorQoOzLIZxfzl1/qI5KIdHp6nEYNMAdR3m/mkA5Q4sCSMgww k942D5TqCyGfJWG1KF+pJA+wfP4KdkEmamy7zDAlIJ/zmIl/OORL4DB9Btx2VTkO7PXe rfDpMWVkHg1XlZLWbOPeOZx+9OUndnswaz4OG+/aWcTPQwZt7i85vsUgYjyGLTS9SoTk biQI+aAvl7bv9P+F2h2hKvLRjeWXIpsl0MiZBxRF3vQ2gaZlcmYQi6yLw/xtmJKScPpU EEkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SnN2rcoH8SEue8/YmUSsyA4G1cGVPVXaIp+iYJ1qNQA=; b=Tm3ucQhLZa8hMKfbQEQJhgPgN4VMfA+La6vcUyFJSGTNtzmedeVzP1FFHD2A4lVu2v 2fQHvf6Rnogc0HddiY8kRTCaDiYWzpNKl/NpoTI1rTZsRloXmYjGGQef1S5NQ9ivKbcD ICEWE5gcbkEU7wyExeCwOa0DXIQqYqUyEHas1Mp0t/cclUsxdtXVudaqccRkw7e8pjmP N9WgknWXnIe6QOyYIuc95odgOhTOWTrI53O41Ll4kIt4CUlvsuFW/No/AplZco4oc7tX WjhwegAzYnf+HiCISrhvvAtV5OjX3jnZjhnQJt53Njucdtzjan2xcjJYNdpQf9Svdema /lVg== X-Gm-Message-State: AOAM530GlNYmXxHFY3NWDSovMvoPi3/LGdoksTA+uKi1SgFcOvPFmdzG Xdq2BeXD7uhqyNPb2O6m0RVGHyEcbgcQwg== X-Google-Smtp-Source: ABdhPJxVzHa3t1mCAOv+gYijGRzIxC2HjTIK11kMP1KbxUHvtnNwNSL+U2jshiwyf8+GElMNxU4atg== X-Received: by 2002:a62:26c2:: with SMTP id m185mr9533310pfm.115.1598389241600; Tue, 25 Aug 2020 14:00:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree Date: Tue, 25 Aug 2020 13:59:12 -0700 Message-Id: <20200825205950.730499-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 4 ++ target/microblaze/translate.c | 67 +++++++++------------------------- 2 files changed, 22 insertions(+), 49 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 3f5f7b1852..8d3de039fb 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -41,6 +41,10 @@ addikc 001110 ..... ..... ................ = @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 +pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea +pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea +pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ce91645f05..de2cf5b153 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -279,6 +279,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *= arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return do_typea(dc, a, SE, FN); } =20 +#define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ + { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -350,6 +354,20 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_= i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) =20 +static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); +} + +static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); +} + +DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf) +DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq) +DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne) + /* No input carry, but output carry. */ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -399,49 +417,10 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) =20 -static void dec_pattern(DisasContext *dc) -{ - unsigned int mode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - - mode =3D dc->opcode & 3; - switch (mode) { - case 0: - /* pcmpbf. */ - if (dc->rd) - gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->= rb]); - break; - case 2: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - case 3: - if (dc->rd) { - tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - } - break; - default: - cpu_abort(CPU(dc->cpu), - "unsupported pattern insn opcode=3D%x\n", dc->opcode= ); - break; - } -} - static void dec_and(DisasContext *dc) { unsigned int not; =20 - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - not =3D dc->opcode & (1 << 1); =20 if (!dc->rd) @@ -455,22 +434,12 @@ static void dec_and(DisasContext *dc) =20 static void dec_or(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } =20 static void dec_xor(DisasContext *dc) { - if (!dc->type_b && (dc->imm & (1 << 10))) { - dec_pattern(dc); - return; - } - if (dc->rd) tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390884; cv=none; d=zohomail.com; s=zohoarc; b=nIqv/Q/RKNQWUCpmhiTquVTvd5RY9Y2M4my5ncicKgZ55p7bJoGf0dh7k8zcSv7hn9pNlYyOvTbyJZWKlDWHpjlgKxhHcvMLgltHrfQqqcVJMHrKejN+vvtL/1sO7/+SfgN88iKLwUSp6yza/YigwT20WkWVWtxuoLHsdsE9LmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390884; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SsU/apSMePMugaV3JgWngynDwxXG4uJq3nxeDvv6ZKI=; b=aPnp9n+Ga23x/zM7vJyS67pzNbQsCWuexzVbTCCZiChxxra+Fw73umXihyHQeNMI8l KHpFMkXhpTHOGLwKftuXkI6cw7m8aZ+zJojnflgsbpxpsEYdz8fITv/A3KYR9cgAnX+p FEHWC19BzBpgkj8jI9b6aCllcBijozZ7oGbbuTdUs8BDC+vEcjIEJxrLBjtT5g9PA2iB JTmGayAWUHzYVrJS4r60eS2U8C1c8y1OtfxoMeMutUF4IWFoD9Zbl9FjrS79uixofGER 6IKrAF5YI/YOVVhTRJmg32z2G42qxKorNBSdWdAhESyF6NcelVATwR7HNWh2AWHOOmSB 3jxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SsU/apSMePMugaV3JgWngynDwxXG4uJq3nxeDvv6ZKI=; b=gZKYY3PLRym4bgufpEF+iFFle082/D3CrByFzU792L25Kp8AP964IpH1hcxgDa1f55 9/nn8gBTAnxwkElC1/2aHifu4N2a1m0DNKeLB7cIDIFJ+at7FnxdcX6EutyMeAqAQuET M1z2CSfoJwcq5bIcrJcyDbbaprAKMe0jby4FSfY5AygCa+W/EOjO8Dg+5VeRV7hSmHkW BWUYT6isEucbrs/hBfr9UgzYpcQqKqaHGWsVhA+ckFvWZK63beVJAEiDdLAeCCm+9Hmg Mk8FxHP0SZfl4iwshlOQCk+nbU6K4cwQpVY0REDtRsW0TDVJuP0v6f6gO3FCXOlsJHp/ 9FaA== X-Gm-Message-State: AOAM532r/LWkmrn5gF1j9F2L3xVBU/XAXI3vE5l57heBPtgK0smhoM+a Vyw6miUzILpScf7U0WSnb9riYkL4YpCKPA== X-Google-Smtp-Source: ABdhPJx43c7yBLMrIxlV2ubC7hixSwP0UDL2Zj8Q6Kp26NmxTrEeqEo7jCKFaKv84O9AR/aqm7CgAA== X-Received: by 2002:aa7:92d7:: with SMTP id k23mr9123640pfa.295.1598389242728; Tue, 25 Aug 2020 14:00:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 40/77] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree Date: Tue, 25 Aug 2020 13:59:13 -0700 Message-Id: <20200825205950.730499-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 12 ++++++++++ target/microblaze/translate.c | 44 ++++++++++++---------------------- 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 8d3de039fb..6b3cc9a182 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -38,9 +38,18 @@ addic 001010 ..... ..... ................ = @typeb addik 001100 ..... ..... ................ @typeb addikc 001110 ..... ..... ................ @typeb =20 +and 100001 ..... ..... ..... 000 0000 0000 @typea +andi 101001 ..... ..... ................ @typeb + +andn 100011 ..... ..... ..... 000 0000 0000 @typea +andni 101011 ..... ..... ................ @typeb + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 +or 100000 ..... ..... ..... 000 0000 0000 @typea +ori 101000 ..... ..... ................ @typeb + pcmpbf 100000 ..... ..... ..... 100 0000 0000 @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea @@ -54,3 +63,6 @@ rsubi 001001 ..... ..... ................ @= typeb rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb + +xor 100010 ..... ..... ..... 000 0000 0000 @typea +xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index de2cf5b153..5252790b09 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -331,6 +331,16 @@ DO_TYPEBV(addic, true, gen_addc) DO_TYPEBI(addik, false, tcg_gen_addi_i32) DO_TYPEBV(addikc, true, gen_addkc) =20 +static void gen_andni(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + tcg_gen_andi_i32(out, ina, ~imm); +} + +DO_TYPEA(and, false, tcg_gen_and_i32) +DO_TYPEBI(andi, false, tcg_gen_andi_i32) +DO_TYPEA(andn, false, tcg_gen_andc_i32) +DO_TYPEBI(andni, false, gen_andni) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt =3D tcg_temp_new_i32(); @@ -354,6 +364,9 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) =20 +DO_TYPEA(or, false, tcg_gen_or_i32) +DO_TYPEBI(ori, false, tcg_gen_ori_i32) + static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); @@ -417,32 +430,8 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) =20 -static void dec_and(DisasContext *dc) -{ - unsigned int not; - - not =3D dc->opcode & (1 << 1); - - if (!dc->rd) - return; - - if (not) { - tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))= ); - } else - tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_or(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} - -static void dec_xor(DisasContext *dc) -{ - if (dc->rd) - tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); -} +DO_TYPEA(xor, false, tcg_gen_xor_i32) +DO_TYPEBI(xori, false, tcg_gen_xori_i32) =20 static void msr_read(DisasContext *dc, TCGv_i32 d) { @@ -1567,9 +1556,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_AND, dec_and}, - {DEC_XOR, dec_xor}, - {DEC_OR, dec_or}, {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y0GhQmIlcg+ScCvY3Co9GQAvD5jBxaWm8gs041r/HXU=; b=JTRGB80qZ7pHKoUrhtdI4wnlB54v+X4kdzI66ft1KLDH8CAsN6G+LcEoc1Fuu2xaCh xYXeLNcz6D4EpaJK60Itg++p5xUt2B/s58vP3eNUSW8ZFFOUHpf50cpnb72+gdpNq4Fi nOosvOa27HclkMuU9d4yF3BQd1WGAfTm+x/49fZF5M4GMMYC7RljdxL3B2UetlpPBoc3 c7xXoc8eifb20aIUeEN3fX/h3VGIby5IJcN4vnFpYuEe03HNNYaTRn570QftFdddTTSy slRKEufoVXnmsFys/4qpfYJ3aSBV6a8WLDFmhMRlhZSrO0WaLuaG0MK4CZGyk8w/ZzT1 bbyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y0GhQmIlcg+ScCvY3Co9GQAvD5jBxaWm8gs041r/HXU=; b=ostWOsrYjjeq4xkOGSzRqIZdxKQmPCtv+d8lH4QIFRUaTd8kksYWQ3chmmEamb2CSk F9yNC7Kq89xr5il5L++cfGSSlA4rrz5FMg2Kzv5wGsyu0ntjpRW1RtwetP2DRmpJ6psA R8zDD1pql+KMYiJlc5EwVqxLFbJEXDGqPRPofT/+1/K0vHpwotoVNqe/3jz21+GbGZI6 +wdDz9smBPf4lZ8y2/mKJ/QSdV9jOY7ptK9xo/+fgnHO4nR4Y8L+ba2cXkkf1PuSTDA/ R9uPVJOS2rh6IWsE089wSefOmZHPrMonb3ZzeOMtF2AorCa8RQF2/0WPf5TzekoDQRPz q2Kw== X-Gm-Message-State: AOAM5335iVYxGTHn8eLytLMtzpV+cW3gIMFfeeHTgRA9vOsRa9saylEA sY8yCbgvxwdMVWg/IfFp0k107HKBAR++yw== X-Google-Smtp-Source: ABdhPJyryqiC4ubkBeFxiAwFn/ROxqQ4r+6fSQ6op9MOlTFpCTqtJY5ZgH1aHFxdc048GcwaaWuE0g== X-Received: by 2002:aa7:8699:: with SMTP id d25mr1013097pfo.191.1598389243875; Tue, 25 Aug 2020 14:00:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 41/77] target/microblaze: Convert dec_mul to decodetree Date: Tue, 25 Aug 2020 13:59:14 -0700 Message-Id: <20200825205950.730499-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++++++++++++++-------------------- 2 files changed, 37 insertions(+), 46 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 6b3cc9a182..65a8a53b54 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -47,6 +47,12 @@ andni 101011 ..... ..... ................ = @typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 +mul 010000 ..... ..... ..... 000 0000 0000 @typea +mulh 010000 ..... ..... ..... 000 0000 0001 @typea +mulhu 010000 ..... ..... ..... 000 0000 0011 @typea +mulhsu 010000 ..... ..... ..... 000 0000 0010 @typea +muli 011000 ..... ..... ................ @typeb + or 100000 ..... ..... ..... 000 0000 0000 @typea ori 101000 ..... ..... ................ @typeb =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5252790b09..dc6ea523b5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -287,6 +287,10 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *= arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } =20 +#define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ + { return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); } + #define DO_TYPEBV(NAME, SE, FN) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } @@ -364,6 +368,33 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_= i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) =20 +static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_muls2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_mulu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_mulsu2_i32(tmp, out, ina, inb); + tcg_temp_free_i32(tmp); +} + +DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32) +DO_TYPEA_CFG(mulh, use_hw_mul >=3D 2, false, gen_mulh) +DO_TYPEA_CFG(mulhu, use_hw_mul >=3D 2, false, gen_mulhu) +DO_TYPEA_CFG(mulhsu, use_hw_mul >=3D 2, false, gen_mulhsu) +DO_TYPEBI_CFG(muli, use_hw_mul, false, tcg_gen_muli_i32) + DO_TYPEA(or, false, tcg_gen_or_i32) DO_TYPEBI(ori, false, tcg_gen_ori_i32) =20 @@ -638,51 +669,6 @@ static void dec_msr(DisasContext *dc) } } =20 -/* Multiplier unit. */ -static void dec_mul(DisasContext *dc) -{ - TCGv_i32 tmp; - unsigned int subcode; - - if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { - return; - } - - subcode =3D dc->imm & 3; - - if (dc->type_b) { - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - return; - } - - /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ - if (subcode >=3D 1 && subcode <=3D 3 && dc->cpu->cfg.use_hw_mul < 2) { - /* nop??? */ - } - - tmp =3D tcg_temp_new_i32(); - switch (subcode) { - case 0: - tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc-= >rb]); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); - break; - } - tcg_temp_free_i32(tmp); -} - /* Div unit. */ static void dec_div(DisasContext *dc) { @@ -1565,7 +1551,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_MUL, dec_mul}, {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391021; cv=none; d=zohomail.com; s=zohoarc; b=KJxmew2P5VQUhDgo57DrocLygdjDY0SHfjCWRw7ukTYjGyH5B2PexR8JZYPFF2onirkGLh6yNYKSMjkZ5oFnQgSILbMOvccTUL8t9ihsvxyXsiXqhDr50n3ny553G1BFWTJwCpfYIRhI/M2vPCetZDU2AQqQGC5QBUjsXv5nQBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391021; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k4SMKMjkRRkG1Mjn2l2ewz/RkrM2zbTl1em1p59D3mo=; b=Pfj26DAp7KMfb6rxEjsQcxvJysdbigqxgUUIcpCRfA2udXLwSIjWpX/sQXGx8XV+HURoLs92nCoDrceya90w47poAqojt9ABT3WsVJgTQk6A+xcsELqw1ijt0u0wcuGvEx3j1Pjy0Qik4IP5BwoJ0PPWCSl2alkH66TswJ52ppg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391021148199.87845807868746; Tue, 25 Aug 2020 14:30:21 -0700 (PDT) Received: from localhost ([::1]:52552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgWJ-0007dk-Qw for importer@patchew.org; Tue, 25 Aug 2020 17:30:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3k-0008Bf-OS for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:48 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:46066) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3i-0001s8-Qk for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:48 -0400 Received: by mail-pf1-x441.google.com with SMTP id k15so1822227pfc.12 for ; Tue, 25 Aug 2020 14:00:46 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k4SMKMjkRRkG1Mjn2l2ewz/RkrM2zbTl1em1p59D3mo=; b=XOMZ4l05D5Rfa+RZYvVOAmYA4Ea7BrPh93a/iBcTGBXiFOijdkTlviHEy5BVinV0Bt uPVhZkwGUaeXcbde/ZogK+xLVh6tAJXqNSNMUgFZhZ0YA5xWn/hzJVin5dTzMyB/F/Qj O1O4UQnstTqY73sF9zq37W1rQeWL+bCQXWuvR/abF2vc0hkiWCCg25ZY+SV7pSudZYwa qKxEOaS8HrgrPC5aoQ0lJGc5eEZ63hSRl9hw2VzQ5OA/GsMpUyGyDdTQPuTh6u/zI6Gv muqyWDCOrLwaRzJ/O7ui4WbA6QCMY4AJV84PYzpjmik8cEm0OAX6wAu8tKHuJjRMjSSg /nzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k4SMKMjkRRkG1Mjn2l2ewz/RkrM2zbTl1em1p59D3mo=; b=K72uHXzifAdeJpStBHI7XXIhrft/GrkdOFOdfRkoEkPRnI+6UBO7XcH3tb5YN+uzue t+zrN6hGTnrZ7lSnwkofedM0A6HIXY8KuDzzJ1kYMVPcwgoXiLoA6/ryfq7S4BAzvRTf 1U1wMZhnHTD9yJp4+Rmhg/tcBavlSu10TDZ8NeAagDRoLh35vEQpQGZz7M5S0pZytkL8 +oUwmLQfbWTG3yuG4tEvnlVEiXRznWgIbZyKwJJFdE0tOD0ECxCWmUixNB0+c0rE/8lR eTkQa4AqmSVG1yLIJ/4S8W3ynL51keBHkA0W9XmJWhr/tFqi6lTLnAH5EfnHlZVTyWBC bdIA== X-Gm-Message-State: AOAM531YO1XZKWp1+8eVEoUAofWVGlK/ehq/YkpYPElzZUfuMddPva+Y 5KZmJb8vkiS+K9OQiyEMdIGqlupy9f8koA== X-Google-Smtp-Source: ABdhPJwb2fi2TLa6HkBFE5JCLLRnBbPRsxq1cjUyFol06ztnQHVlPYwartnnqcslAOj+Ow5GyaXBXA== X-Received: by 2002:a62:2d1:: with SMTP id 200mr9524092pfc.154.1598389245007; Tue, 25 Aug 2020 14:00:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 42/77] target/microblaze: Convert dec_div to decodetree Date: Tue, 25 Aug 2020 13:59:15 -0700 Message-Id: <20200825205950.730499-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 +++ target/microblaze/translate.c | 35 +++++++++++++--------------------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 65a8a53b54..18619e923e 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -47,6 +47,9 @@ andni 101011 ..... ..... ................ @= typeb cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 +idiv 010010 ..... ..... ..... 000 0000 0000 @typea +idivu 010010 ..... ..... ..... 000 0000 0010 @typea + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index dc6ea523b5..1d54ea02f0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,19 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_= i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) =20 +static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divs(out, cpu_env, inb, ina); +} + +static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + gen_helper_divu(out, cpu_env, inb, ina); +} + +DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) +DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -669,27 +682,6 @@ static void dec_msr(DisasContext *dc) } } =20 -/* Div unit. */ -static void dec_div(DisasContext *dc) -{ - unsigned int u; - - u =3D dc->imm & 2;=20 - - if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { - return; - } - - if (u) - gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - else - gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), - cpu_R[dc->ra]); - if (!dc->rd) - tcg_gen_movi_i32(cpu_R[dc->rd], 0); -} - static void dec_barrel(DisasContext *dc) { TCGv_i32 t0; @@ -1551,7 +1543,6 @@ static struct decoder_info { {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_FPU, dec_fpu}, - {DEC_DIV, dec_div}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=QlQW0mthP7k6mEHQJjzG86WvF/cN8xdKjOgpDqAaksWh52IXrBrHdQtQiQOMbgCMA1 K20AGnts/TU1sEG0WneWRMxYI8aoJEF2SLU3nCqW4iCkFIZDMdK/kqOVgE5t2jpfhget drUViA2h9mtZRymTVVNJfTKVMhaHKw84LJN96OK9D/M10ppcDhnzpCe6lyqffpeScIEq BEUgoj5zlGrZLtxUYnTO7iJ4McZmTcfw/9j4a6JYwHDqZmZPrfVHKeEqw1Y22tN1QH+g g9oB6tgBZoNOo6lKloI2hAQF+bXO12vzGi07Yh3vA7RK9qqk9TDrxCG6kDQGt+GsJD9z VT8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bQC2NsHcUulzW6D5RhH+hzBIgYR+xbZNPdmPEiO9k08=; b=TIt7Ks7ek0YShkRSEDeltBCB4dIxe5J5eO1wPV9/V1YxmBX9awcBRCQ/WhgeiL0y5t EZNinra6c9eAAgUPw31+Dm7/HgacZuWUqfVDONKrHBZn7rIALQtlPxmxSQVNQ7OqJcBH EvCXaSb5VBsNP2CmyrJAoD8EHaaHn3QqTHbATpaHg3sXhFP+dTBF5OVGa4ITCy2LdkEC kbmKyLklIrhb5tdXwdR9lwCh+IGmREUnDEygs+UJKW/8FaQUUbCFIXgDA8XrD59H9SfV KIRunMOY8B7JaPAsVFC/4Ax8EvF8sR5RiArp+Dll4ttHAG4EgtrroqLYFKiWOgShZy4C 2yOw== X-Gm-Message-State: AOAM531VQoOd0c22wuTe/adrUI7ZeMzyc3eHT9E+hJiSjCGH07jlmBip y4vXHL7CwdTdYlYzz0F9mt4jd3B+e1gNIw== X-Google-Smtp-Source: ABdhPJzrbf2ZnHpbX7xMUZTBNSQUvqmHijaK/EduBn4nNhOi/m2ANF21pn5zM1OeGiH15MEM3guR8A== X-Received: by 2002:a62:1d05:: with SMTP id d5mr5505067pfd.63.1598389246141; Tue, 25 Aug 2020 14:00:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero Date: Tue, 25 Aug 2020 13:59:16 -0700 Message-Id: <20200825205950.730499-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 4 ++-- target/microblaze/op_helper.c | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 6f7f96421f..79e1e8ecc7 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -1,7 +1,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) =20 -DEF_HELPER_3(divs, i32, env, i32, i32) -DEF_HELPER_3(divu, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) =20 DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(frsub, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f976d112eb..d99d98051a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -69,26 +69,27 @@ void helper_raise_exception(CPUMBState *env, uint32_t i= ndex) cpu_loop_exit(cs); } =20 -static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t = ra) { - MicroBlazeCPU *cpu =3D env_archcpu(env); - - if (b =3D=3D 0) { + if (unlikely(b =3D=3D 0)) { env->msr |=3D MSR_DZ; =20 - if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs =3D env_cpu(env); + env->esr =3D ESR_EC_DIVZERO; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } - return 0; + return false; } - env->msr &=3D ~MSR_DZ; - return 1; + return true; } =20 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return (int32_t)a / (int32_t)b; @@ -96,7 +97,7 @@ uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_= t b) =20 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) { - if (!div_prepare(env, a, b)) { + if (!check_divz(env, a, b, GETPC())) { return 0; } return a / b; --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390228; cv=none; d=zohomail.com; s=zohoarc; b=ZgwHmllNedqZmKj8rE2b9/cH5Ln2gsvTU+mm6x70BQ/b1JdzbN9yEdFxK+V6pwI2/0lJi7klXKj3cDa/fFa+AYAu8zqGqhVuqTGP4BNfuP+ONKDC0CKrhyvjbTd8msMuBcsDJEzcZjB1bOVNuH+PYffF5aJS/tfgdLdgUHFLhYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390228; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EBVpcdmGEzyJpy5TxBqmLFo/yQsChKNTx1tPZX/BrS4=; b=DN29QXiosHhg/8sh7ZgLYlEuoRNtTNNNAWpJ+rARiWuQIcAzZX02sv23+kSbkgNDEcS1Mcb0TD7xbj6Rf8ROFPTGqnyLIBdBimo+zbrPJTWwjscLVjZxrOwnaItCauc1MZhJNjYgfMw6unIPb06XiiD0S+VngGZrgv1S52Fwo5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15983902289670.21555267843564252; Tue, 25 Aug 2020 14:17:08 -0700 (PDT) Received: from localhost ([::1]:48132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgJX-0007xi-Kn for importer@patchew.org; Tue, 25 Aug 2020 17:17:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3n-0008HV-QB for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:51 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3l-0001uC-2z for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:51 -0400 Received: by mail-pf1-x444.google.com with SMTP id y206so8287766pfb.10 for ; Tue, 25 Aug 2020 14:00:48 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EBVpcdmGEzyJpy5TxBqmLFo/yQsChKNTx1tPZX/BrS4=; b=G9oMrc3TDTy2qVaNzl/jLz8sZ8+MtQFzNkA4Q9NQtm/6nIewCWZxNY/NqObR2+hp/Q OJ6pjiDbtPqTvnfYpPRcYgWhm6LN5lTbFthO2izWDiTWFmn41VS+VAf9UhxILSbaj/Tu xeFrhb2XcrHx3yp3Hd5n8EGd59+QBhfq0D3/UGOXxLDAjqGIX14tXbln+QSxL9bSOGx4 fSjav3yBHYvnHSiOY1eXnPI0UN7FZqOX+UO8CC3NwKH4l/RATFSK/bwHQvyk5oINuHlC Qn3hqipb1SVF4VosvjUZ67iu9Nic0Vi2SsR/hF+gwgvs/ZiZ01q4f88T1IIMAkwhWBWQ rZDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EBVpcdmGEzyJpy5TxBqmLFo/yQsChKNTx1tPZX/BrS4=; b=s66TwZQykk994sd8P2TQ1NZrKSupUJIKYMPFYeIpTeNWcKvH0uYOvpOhugYBIpoFyo U2EoAMI5a3rKantfc5UsHfn/jLAyuYGDOYJkWEYMbMfK8HxuMnKsowO6xDGt6P+1aQsO YblUHJ547Zgw3PpwDcdBYs8zecBLVhvipUbOnr/BqXZmwvz7SBMyvsBM5zNrS+IKzByA 57bPQr+gNQv84L4l13FaUvhk03mXex2xZb49O+OVe9V/Kcyf7ucRO0+SCsYnNN/IDmMj FNNPgRxrOYZDHzGMGfJ4gZH99IgFtp29d0wgyTSCeBta6T+ZiJiWzYiEa7yXr0IaXXa4 J8gg== X-Gm-Message-State: AOAM531aYWPmtKPGMnZxB1lqB2Z7HDkiu66b/fhA42T3nXm6rkwjbH48 bi62zIs2g/fn9wsO3i7PBu/VVT2a9vBqyA== X-Google-Smtp-Source: ABdhPJzP050xianL0sYua5XFzEeWW11T5KMYUPmbZlJHqLNe1DI7a81y7mEa4UELj0VcrFchO26gMA== X-Received: by 2002:a63:5825:: with SMTP id m37mr8290222pgb.257.1598389247238; Tue, 25 Aug 2020 14:00:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 44/77] target/microblaze: Convert dec_bit to decodetree Date: Tue, 25 Aug 2020 13:59:17 -0700 Message-Id: <20200825205950.730499-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 +++++ target/microblaze/translate.c | 148 +++++++++++++++++---------------- 2 files changed, 95 insertions(+), 73 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 18619e923e..5666b381b9 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -17,6 +17,7 @@ # License along with this library; if not, see . # =20 +&typea0 rd ra &typea rd ra rb &typeb rd ra imm =20 @@ -26,6 +27,9 @@ @typea ...... rd:5 ra:5 rb:5 ... .... .... &typea @typeb ...... rd:5 ra:5 ................ &typeb imm=3D%exti= mm =20 +# Officially typea, but with rb=3D=3D0, which is not used. +@typea0 ...... rd:5 ra:5 ................ &typea0 + ### =20 add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -44,6 +48,8 @@ andi 101001 ..... ..... ................ @= typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb =20 +clz 100100 ..... ..... 00000 000 1110 0000 @typea0 + cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 @@ -73,5 +79,19 @@ rsubic 001011 ..... ..... ................ = @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb =20 +sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 +sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 + +sra 100100 ..... ..... 00000 000 0000 0001 @typea0 +src 100100 ..... ..... 00000 000 0010 0001 @typea0 +srl 100100 ..... ..... 00000 000 0100 0001 @typea0 + +swapb 100100 ..... ..... 00000 001 1110 0000 @typea0 +swaph 100100 ..... ..... 00000 001 1110 0010 @typea0 + +# Cache operations have no effect in qemu: discard the arguments. +wdic 100100 00000 ----- ----- -00 -11- 01-0 # wdc +wdic 100100 00000 ----- ----- 000 0110 1000 # wic + xor 100010 ..... ..... ..... 000 0000 0000 @typea xori 101010 ..... ..... ................ @typeb diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 1d54ea02f0..10ae369cb0 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -241,6 +241,21 @@ static bool do_typea(DisasContext *dc, arg_typea *arg,= bool side_effects, return true; } =20 +static bool do_typea0(DisasContext *dc, arg_typea0 *arg, bool side_effects, + void (*fn)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 rd, ra; + + if (arg->rd =3D=3D 0 && !side_effects) { + return true; + } + + rd =3D reg_for_write(dc, arg->rd); + ra =3D reg_for_read(dc, arg->ra); + fn(rd, ra); + return true; +} + static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effec= ts, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -283,6 +298,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *= arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } =20 +#define DO_TYPEA0(NAME, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return do_typea0(dc, a, SE, FN); } + +#define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ + static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \ + { return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); } + #define DO_TYPEBI(NAME, SE, FNI) \ static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_imm(dc, a, SE, FNI); } @@ -345,6 +368,13 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) =20 +static void gen_clz(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_clzi_i32(out, ina, 32); +} + +DO_TYPEA0_CFG(clz, use_pcmp_instr, false, gen_clz) + static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 lt =3D tcg_temp_new_i32(); @@ -474,6 +504,51 @@ DO_TYPEBV(rsubic, true, gen_rsubc) DO_TYPEBV(rsubik, false, gen_rsubk) DO_TYPEBV(rsubikc, true, gen_rsubkc) =20 +DO_TYPEA0(sext8, false, tcg_gen_ext8s_i32) +DO_TYPEA0(sext16, false, tcg_gen_ext16s_i32) + +static void gen_sra(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_sari_i32(out, ina, 1); +} + +static void gen_src(TCGv_i32 out, TCGv_i32 ina) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_msr_c); + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_extract2_i32(out, ina, tmp, 1); + + tcg_temp_free_i32(tmp); +} + +static void gen_srl(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_andi_i32(cpu_msr_c, ina, 1); + tcg_gen_shri_i32(out, ina, 1); +} + +DO_TYPEA0(sra, false, gen_sra) +DO_TYPEA0(src, false, gen_src) +DO_TYPEA0(srl, false, gen_srl) + +static void gen_swaph(TCGv_i32 out, TCGv_i32 ina) +{ + tcg_gen_rotri_i32(out, ina, 16); +} + +DO_TYPEA0(swapb, false, tcg_gen_bswap32_i32) +DO_TYPEA0(swaph, false, gen_swaph) + +static bool trans_wdic(DisasContext *dc, arg_wdic *a) +{ + /* Cache operations are nops: only check for supervisor mode. */ + trap_userspace(dc, true); + return true; +} + DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) =20 @@ -740,78 +815,6 @@ static void dec_barrel(DisasContext *dc) } } =20 -static void dec_bit(DisasContext *dc) -{ - CPUState *cs =3D CPU(dc->cpu); - TCGv_i32 t0; - unsigned int op; - - op =3D dc->ir & ((1 << 9) - 1); - switch (op) { - case 0x21: - /* src. */ - t0 =3D tcg_temp_new_i32(); - - tcg_gen_shli_i32(t0, cpu_msr_c, 31); - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); - } - tcg_temp_free_i32(t0); - break; - - case 0x1: - case 0x41: - /* srl. */ - tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); - if (dc->rd) { - if (op =3D=3D 0x41) - tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - else - tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); - } - break; - case 0x60: - tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x61: - tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x64: - case 0x66: - case 0x74: - case 0x76: - /* wdc. */ - trap_userspace(dc, true); - break; - case 0x68: - /* wic. */ - trap_userspace(dc, true); - break; - case 0xe0: - if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { - return; - } - if (dc->cpu->cfg.use_pcmp_instr) { - tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); - } - break; - case 0x1e0: - /* swapb */ - tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); - break; - case 0x1e2: - /*swaph */ - tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); - break; - default: - cpu_abort(cs, "unknown bit oc=3D%x op=3D%x rd=3D%d ra=3D%d rb= =3D%d\n", - (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->= rb); - break; - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { @@ -1534,7 +1537,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_BIT, dec_bit}, {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391009; cv=none; d=zohomail.com; s=zohoarc; b=BRIB4sMpiK7L+YcBHFIk9zhkw5XKxHK47lxS00vNcv+BrVKSH1x/K0i8U472+FPbkqcgEjf88sYGQbk5S4lwR64mddwjRZ4Z7sjp9q3eNs+QXVWKtSkSJGEknA2GFrU9vMx/dltega3nnK8lLA4m0Q95SZJlIA5F69Ixp+EivMo= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 ++++++ target/microblaze/translate.c | 125 +++++++++++++++++---------------- 2 files changed, 86 insertions(+), 59 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 5666b381b9..31e50549ea 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -30,6 +30,15 @@ # Officially typea, but with rb=3D=3D0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 =20 +# Officially typeb, but any immediate extension is unused. +@typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb + +# For convenience, extract the two imm_w/imm_s fields, then pack +# them back together as "imm". Doing this makes it easiest to +# match the required zero at bit 5. +%ieimm 6:5 0:5 +@typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=3D%ieimm + ### =20 add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -48,6 +57,17 @@ andi 101001 ..... ..... ................ = @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb =20 +bsrl 010001 ..... ..... ..... 000 0000 0000 @typea +bsra 010001 ..... ..... ..... 010 0000 0000 @typea +bsll 010001 ..... ..... ..... 100 0000 0000 @typea + +bsrli 011001 ..... ..... 00000 000000 ..... @typeb_bs +bsrai 011001 ..... ..... 00000 010000 ..... @typeb_bs +bslli 011001 ..... ..... 00000 100000 ..... @typeb_bs + +bsefi 011001 ..... ..... 01000 .....0 ..... @typeb_ie +bsifi 011001 ..... ..... 10000 .....0 ..... @typeb_ie + clz 100100 ..... ..... 00000 000 1110 0000 @typea0 =20 cmp 000101 ..... ..... ..... 000 0000 0001 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 10ae369cb0..8fdd03fb5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -368,6 +368,72 @@ DO_TYPEBI(andi, false, tcg_gen_andi_i32) DO_TYPEA(andn, false, tcg_gen_andc_i32) DO_TYPEBI(andni, false, gen_andni) =20 +static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_sar_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shr_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, inb, 31); + tcg_gen_shl_i32(out, ina, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w =3D extract32(imm, 5, 5); + int imm_s =3D extract32(imm, 0, 5); + + if (imm_w + imm_s > 32 || imm_w =3D=3D 0) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=3D%d s=3D%d\n", + imm_w, imm_s); + } else { + tcg_gen_extract_i32(out, ina, imm_s, imm_w); + } +} + +static void gen_bsifi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) +{ + /* Note that decodetree has extracted and reassembled imm_w/imm_s. */ + int imm_w =3D extract32(imm, 5, 5); + int imm_s =3D extract32(imm, 0, 5); + int width =3D imm_w - imm_s + 1; + + if (imm_w < imm_s) { + /* These inputs have an undefined behavior. */ + qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=3D%d s=3D%d\n", + imm_w, imm_s); + } else { + tcg_gen_deposit_i32(out, out, ina, imm_s, width); + } +} + +DO_TYPEA_CFG(bsra, use_barrel, false, gen_bsra) +DO_TYPEA_CFG(bsrl, use_barrel, false, gen_bsrl) +DO_TYPEA_CFG(bsll, use_barrel, false, gen_bsll) + +DO_TYPEBI_CFG(bsrai, use_barrel, false, tcg_gen_sari_i32) +DO_TYPEBI_CFG(bsrli, use_barrel, false, tcg_gen_shri_i32) +DO_TYPEBI_CFG(bslli, use_barrel, false, tcg_gen_shli_i32) + +DO_TYPEBI_CFG(bsefi, use_barrel, false, gen_bsefi) +DO_TYPEBI_CFG(bsifi, use_barrel, false, gen_bsifi) + static void gen_clz(TCGv_i32 out, TCGv_i32 ina) { tcg_gen_clzi_i32(out, ina, 32); @@ -757,64 +823,6 @@ static void dec_msr(DisasContext *dc) } } =20 -static void dec_barrel(DisasContext *dc) -{ - TCGv_i32 t0; - unsigned int imm_w, imm_s; - bool s, t, e =3D false, i =3D false; - - if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { - return; - } - - if (dc->type_b) { - /* Insert and extract are only available in immediate mode. */ - i =3D extract32(dc->imm, 15, 1); - e =3D extract32(dc->imm, 14, 1); - } - s =3D extract32(dc->imm, 10, 1); - t =3D extract32(dc->imm, 9, 1); - imm_w =3D extract32(dc->imm, 6, 5); - imm_s =3D extract32(dc->imm, 0, 5); - - if (e) { - if (imm_w + imm_s > 32 || imm_w =3D=3D 0) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=3D%d s=3D%d= \n", - imm_w, imm_s); - } else { - tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w= ); - } - } else if (i) { - int width =3D imm_w - imm_s + 1; - - if (imm_w < imm_s) { - /* These inputs have an undefined behavior. */ - qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=3D%d s=3D%d= \n", - imm_w, imm_s); - } else { - tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra= ], - imm_s, width); - } - } else { - t0 =3D tcg_temp_new_i32(); - - tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); - tcg_gen_andi_i32(t0, t0, 31); - - if (s) { - tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - if (t) { - tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } else { - tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); - } - } - tcg_temp_free_i32(t0); - } -} - static inline void sync_jmpstate(DisasContext *dc) { if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { @@ -1537,7 +1545,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_BARREL, dec_barrel}, {DEC_LD, dec_load}, {DEC_ST, dec_store}, {DEC_IMM, dec_imm}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 ++ target/microblaze/translate.c | 18 +++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 31e50549ea..a7eb7d4e6f 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -76,6 +76,8 @@ cmpu 000101 ..... ..... ..... 000 0000 0011 @= typea idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea =20 +imm 101100 00000 00000 imm:16 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8fdd03fb5a..c1d19f4678 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -477,6 +477,15 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv= _i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) =20 +static bool trans_imm(DisasContext *dc, arg_imm *arg) +{ + dc->ext_imm =3D arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags |=3D IMM_FLAG; + dc->clear_imm =3D 0; + return true; +} + static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -834,14 +843,6 @@ static inline void sync_jmpstate(DisasContext *dc) } } =20 -static void dec_imm(DisasContext *dc) -{ - dc->ext_imm =3D dc->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |=3D IMM_FLAG; - dc->clear_imm =3D 0; -} - static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) { /* Should be set to true if r1 is used by loadstores. */ @@ -1547,7 +1548,6 @@ static struct decoder_info { } decinfo[] =3D { {DEC_LD, dec_load}, {DEC_ST, dec_store}, - {DEC_IMM, dec_imm}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j79ljoP5zzbkRewQNHGjmrrLK+0Gv9JhkSWBpicBIVs=; b=ULTV3v1R49EuzP5+A8e98MreymoinxCGXW4hj6I06y34y8S2++ADqyyB8KUhNNwrd2 JfnMmung4nHdh8fqXI5JCIK3r4cWxRxNfhmbsQ+5fBdF3H8B0o6QzuNlJ9hSZcARWbWx TgZHRQxM4uPsrnLdbvwnWT10Do55njB6st4Fl5W4kr0WKnrnqAK1bDfHjoQ3gQqJWMuW KbtI1C+gV0zOajquPBa92GRLf65+MqeSqiHtC/FhPt+hymHEGEHrdcjColymG0yhS5xX yIFF4LasgomDH/Hfqj9fbQ9L0N2ldUabmPYd0W6HG4n/7VENjOdHYJ77tU94yZwbBhbH U8Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j79ljoP5zzbkRewQNHGjmrrLK+0Gv9JhkSWBpicBIVs=; b=WF/LqyjmiUDMwKdbuGCfG3vD9z9Vbcdhop4Qn7EHG3Mhuvp0ySgVzpojrwoWd31k6N LtOEhl8vA2YQRUNnDHQDCzVdkWVzXTHezmzl2Rqrf1Xi3Vb1QvtuQx9JiHlnuVenH/XM Pe1T/LpZQkluTn+Oma0hQqFhQ+Df6lDw1PJOV2I3+RzhZQsfrRLAGcjl+zD6R5OL62Ok zGyhkN2NpziKLAjeBzbViOxk88JQX5rRwjnYZMIgD3e/XozdZXQrjQ+UrQGAIDJTcMR8 HiG9nXH8YUwngty8ieJ10jRp46lb9g4H9vLrUe664n7EKxnadZiKBIJtVC7feeP5x9Gn bAYQ== X-Gm-Message-State: AOAM530/+4zDnSdpDdFUVt6olcZIaj8AM5l4Zs5E1/rY8JmCQKE+uH8h Ke0Dhy+ORkUq2JfYo7b338qayuU+1xD6AQ== X-Google-Smtp-Source: ABdhPJzp1+QLnqS5IBhF+RPWc/YkNV4NpbePqkuA/AfLmXRIiKIG0Vaeu6KKRUV+iD339E2azELTAQ== X-Received: by 2002:a17:90a:4803:: with SMTP id a3mr3094542pjh.192.1598389250812; Tue, 25 Aug 2020 14:00:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 47/77] target/microblaze: Convert dec_fpu to decodetree Date: Tue, 25 Aug 2020 13:59:20 -0700 Message-Id: <20200825205950.730499-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu =3D=3D 2. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 19 +++++ target/microblaze/translate.c | 152 +++++++++------------------------ 2 files changed, 60 insertions(+), 111 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index a7eb7d4e6f..ea6743c7e5 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -73,6 +73,25 @@ clz 100100 ..... ..... 00000 000 1110 0000 = @typea0 cmp 000101 ..... ..... ..... 000 0000 0001 @typea cmpu 000101 ..... ..... ..... 000 0000 0011 @typea =20 +fadd 010110 ..... ..... ..... 0000 000 0000 @typea +frsub 010110 ..... ..... ..... 0001 000 0000 @typea +fmul 010110 ..... ..... ..... 0010 000 0000 @typea +fdiv 010110 ..... ..... ..... 0011 000 0000 @typea +fcmp_un 010110 ..... ..... ..... 0100 000 0000 @typea +fcmp_lt 010110 ..... ..... ..... 0100 001 0000 @typea +fcmp_eq 010110 ..... ..... ..... 0100 010 0000 @typea +fcmp_le 010110 ..... ..... ..... 0100 011 0000 @typea +fcmp_gt 010110 ..... ..... ..... 0100 100 0000 @typea +fcmp_ne 010110 ..... ..... ..... 0100 101 0000 @typea +fcmp_ge 010110 ..... ..... ..... 0100 110 0000 @typea + +# Note that flt and fint, unlike fsqrt, are documented as having the RB +# operand which is unused. So allow the field to be non-zero but discard +# the value and treat as 2-operand insns. +flt 010110 ..... ..... ----- 0101 000 0000 @typea0 +fint 010110 ..... ..... ----- 0110 000 0000 @typea0 +fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c1d19f4678..7d1ada7aad 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -318,6 +318,14 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *= arg, bool side_effects, static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ { return do_typeb_val(dc, a, SE, FN); } =20 +#define ENV_WRAPPER2(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina) \ + { HELPER(out, cpu_env, ina); } + +#define ENV_WRAPPER3(NAME, HELPER) \ + static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ + { HELPER(out, cpu_env, ina, inb); } + /* No input carry, but output carry. */ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { @@ -464,6 +472,39 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_= i32 inb) DO_TYPEA(cmp, false, gen_cmp) DO_TYPEA(cmpu, false, gen_cmpu) =20 +ENV_WRAPPER3(gen_fadd, gen_helper_fadd) +ENV_WRAPPER3(gen_frsub, gen_helper_frsub) +ENV_WRAPPER3(gen_fmul, gen_helper_fmul) +ENV_WRAPPER3(gen_fdiv, gen_helper_fdiv) +ENV_WRAPPER3(gen_fcmp_un, gen_helper_fcmp_un) +ENV_WRAPPER3(gen_fcmp_lt, gen_helper_fcmp_lt) +ENV_WRAPPER3(gen_fcmp_eq, gen_helper_fcmp_eq) +ENV_WRAPPER3(gen_fcmp_le, gen_helper_fcmp_le) +ENV_WRAPPER3(gen_fcmp_gt, gen_helper_fcmp_gt) +ENV_WRAPPER3(gen_fcmp_ne, gen_helper_fcmp_ne) +ENV_WRAPPER3(gen_fcmp_ge, gen_helper_fcmp_ge) + +DO_TYPEA_CFG(fadd, use_fpu, true, gen_fadd) +DO_TYPEA_CFG(frsub, use_fpu, true, gen_frsub) +DO_TYPEA_CFG(fmul, use_fpu, true, gen_fmul) +DO_TYPEA_CFG(fdiv, use_fpu, true, gen_fdiv) +DO_TYPEA_CFG(fcmp_un, use_fpu, true, gen_fcmp_un) +DO_TYPEA_CFG(fcmp_lt, use_fpu, true, gen_fcmp_lt) +DO_TYPEA_CFG(fcmp_eq, use_fpu, true, gen_fcmp_eq) +DO_TYPEA_CFG(fcmp_le, use_fpu, true, gen_fcmp_le) +DO_TYPEA_CFG(fcmp_gt, use_fpu, true, gen_fcmp_gt) +DO_TYPEA_CFG(fcmp_ne, use_fpu, true, gen_fcmp_ne) +DO_TYPEA_CFG(fcmp_ge, use_fpu, true, gen_fcmp_ge) + +ENV_WRAPPER2(gen_flt, gen_helper_flt) +ENV_WRAPPER2(gen_fint, gen_helper_fint) +ENV_WRAPPER2(gen_fsqrt, gen_helper_fsqrt) + +DO_TYPEA0_CFG(flt, use_fpu >=3D 2, true, gen_flt) +DO_TYPEA0_CFG(fint, use_fpu >=3D 2, true, gen_fint) +DO_TYPEA0_CFG(fsqrt, use_fpu >=3D 2, true, gen_fsqrt) + +/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { gen_helper_divs(out, cpu_env, inb, ina); @@ -1389,116 +1430,6 @@ static void dec_rts(DisasContext *dc) tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } =20 -static int dec_check_fpuv2(DisasContext *dc) -{ - if ((dc->cpu->cfg.use_fpu !=3D 2) && (dc->tb_flags & MSR_EE_FLAG)) { - gen_raise_hw_excp(dc, ESR_EC_FPU); - } - return (dc->cpu->cfg.use_fpu =3D=3D 2) ? PVR2_USE_FPU2_MASK : 0; -} - -static void dec_fpu(DisasContext *dc) -{ - unsigned int fpu_insn; - - if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { - return; - } - - fpu_insn =3D (dc->ir >> 7) & 7; - - switch (fpu_insn) { - case 0: - gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 1: - gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 2: - gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 3: - gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], - cpu_R[dc->rb]); - break; - - case 4: - switch ((dc->ir >> 4) & 7) { - case 0: - gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 1: - gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 2: - gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 3: - gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 4: - gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 5: - gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - case 6: - gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, - cpu_R[dc->ra], cpu_R[dc->rb]); - break; - default: - qemu_log_mask(LOG_UNIMP, - "unimplemented fcmp fpu_insn=3D%x pc=3D%= x" - " opc=3D%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, - dc->opcode); - dc->abort_at_next_insn =3D 1; - break; - } - break; - - case 5: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 6: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - case 7: - if (!dec_check_fpuv2(dc)) { - return; - } - gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); - break; - - default: - qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=3D%x= pc=3D%x" - " opc=3D%x\n", - fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode= ); - dc->abort_at_next_insn =3D 1; - break; - } -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1551,7 +1482,6 @@ static struct decoder_info { {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, - {DEC_FPU, dec_fpu}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391301; cv=none; d=zohomail.com; s=zohoarc; b=jEmu189OQNpaG8++7Gwg85LA4b+CCDCG9k8DBPj5ZaJ+NQpFTTJE+NwskzjSDs9KZ1j/g3Q3HKzqtzK4bsNXtN+NP8u/Q7Kt33aUIj6MJt+Pg/4lbFxNZAi3xOUt7/f92fkoFKQnCZk8anoyGs/GtWM+sdHGkNjQXO40Yqgkrk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391301; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Gx/7ND2enUqh97byGs4EhjEjQPx9quOoqiJMUHgOSo=; b=cpdIf8EpUWs1LP2+1U4Waax2a8HLIt5RF7ktMYtsAQHHt+yCULaszNthCuVTSggQH7ROM7GdZaysys0GUFXCkYddxywkJ40JcUOGI9AGWOejdpGMYbcODbGFfZ2AoXWin+1nrgTE7VL4ePlC/DtmdLXKp3VLG3DQSfXDg10MHvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391301128208.43783222697766; Tue, 25 Aug 2020 14:35:01 -0700 (PDT) Received: from localhost ([::1]:40614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgap-00060N-Hv for importer@patchew.org; Tue, 25 Aug 2020 17:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3s-0008Pc-30 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:56 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:35621) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3p-0001xE-Rh for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:55 -0400 Received: by mail-pj1-x1044.google.com with SMTP id g6so130096pjl.0 for ; Tue, 25 Aug 2020 14:00:53 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Gx/7ND2enUqh97byGs4EhjEjQPx9quOoqiJMUHgOSo=; b=O45yb+jxuepWiNX5iiTN2suhFZOkV76zhEejPcjLvzeHyaVFUSeSxgEwonQrOcKn4I JCyknw1yiV2Bp+kMpEf7Zntqj6WS5A3CWj8YbHZdKw9t4VUJcds10QixF6qqPvj1Dz9c 77/99j8JjurUYt7vVd1S/aTG6BNR1dscG8Fj7SLnfa/spZFaoOzJ/eLFvf0Wyt3Bflv9 zwFnnqUaFVc9w3PKr+v5RcxKUJPtpjacoF29693NiCovODOxhqC5LkvCfl6rsWtZMQ7d FK+Vd2O7XewHG+2IGrwmqE5lNRIdaU+CDkCEzWUkampH8Bjtx4i1wC18EYRjT/4Vva3q 39dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Gx/7ND2enUqh97byGs4EhjEjQPx9quOoqiJMUHgOSo=; b=YMc7i0xNGARQ/gyzAo+v7YyjCX6nFqq8NnbXsWGAbnyZFH1zhqVKlVB+4WkWtwn0nd fEcQMM+REYoukXV9bwdiHa7GNoVWwLGC9g2jbIbOTBqgdyYSs7wE/07zXYwgtxoeiEvM e4lYxXVpAzR6R/4g9hLWPqRXDIpxPCQgCl98IqwrWBpsFqr6a50tyRT89XAVUNxzBu91 nm6ghrXQMo9mCSdQ12Ce1vjgOP+YaEaZUGouCybkxWMggEIpM3JeD72A3pwPNsdlkMsL yRhXVavkNH8JjfCa35RdZZ1xyG1cDY5KpNHEXCOLLbPPr1q6yF1Lo84oKnMd0HlJqSA8 dftQ== X-Gm-Message-State: AOAM5317IoWv0/OKlgJZoLgCJqM7GZNe2SXM1Hx78wnCgGLw9vpS1fAE ynGDqxDzmGRaub5yWqPFPmtWBPWTlurVPw== X-Google-Smtp-Source: ABdhPJyR/3RaPEK4HODR48MbmQrXXnFNYbdBkFLTm7FOxHZV9DHzDV8kamZj0/y9eoBmmUMDw932Bg== X-Received: by 2002:a17:90a:de10:: with SMTP id m16mr3098906pjv.34.1598389252138; Tue, 25 Aug 2020 14:00:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 48/77] target/microblaze: Fix cpu unwind for fpu exceptions Date: Tue, 25 Aug 2020 13:59:21 -0700 Message-Id: <20200825205950.730499-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index d99d98051a..2c59d4492d 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -104,13 +104,16 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uin= t32_t b) } =20 /* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env) +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) { + CPUState *cs =3D env_cpu(env); + env->esr =3D ESR_EC_FPU; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); } =20 -static void update_fpu_flags(CPUMBState *env, int flags) +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) { int raise =3D 0; =20 @@ -133,7 +136,7 @@ static void update_fpu_flags(CPUMBState *env, int flags) if (raise && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) && (env->msr & MSR_EE)) { - raise_fpu_exception(env); + raise_fpu_exception(env, ra); } } =20 @@ -148,7 +151,7 @@ uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint3= 2_t b) fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); =20 flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } =20 @@ -162,7 +165,7 @@ uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint= 32_t b) fb.l =3D b; fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); return fd.l; } =20 @@ -176,7 +179,7 @@ uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint3= 2_t b) fb.l =3D b; fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } @@ -191,7 +194,7 @@ uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint3= 2_t b) fb.l =3D b; fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } @@ -206,7 +209,7 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, ui= nt32_t b) =20 if (float32_is_signaling_nan(fa.f, &env->fp_status) || float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid); + update_fpu_flags(env, float_flag_invalid, GETPC()); r =3D 1; } =20 @@ -229,7 +232,7 @@ uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, ui= nt32_t b) fb.l =3D b; r =3D float32_lt(fb.f, fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -245,7 +248,7 @@ uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, ui= nt32_t b) fb.l =3D b; r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -261,7 +264,7 @@ uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D float32_le(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 =20 return r; @@ -277,7 +280,7 @@ uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D float32_lt(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); return r; } =20 @@ -291,7 +294,7 @@ uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -306,7 +309,7 @@ uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, ui= nt32_t b) set_float_exception_flags(0, &env->fp_status); r =3D !float32_lt(fa.f, fb.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); =20 return r; } @@ -330,7 +333,7 @@ uint32_t helper_fint(CPUMBState *env, uint32_t a) fa.l =3D a; r =3D float32_to_int32(fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return r; } @@ -344,7 +347,7 @@ uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) fa.l =3D a; fd.l =3D float32_sqrt(fa.f, &env->fp_status); flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags); + update_fpu_flags(env, flags, GETPC()); =20 return fd.l; } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391435; cv=none; d=zohomail.com; s=zohoarc; b=hCv3y+tC6FDE3FF0b3u0D6ET1LPeM5130PbJFIJqIuAmlerdfbVaVyFMX6zWRqSPK7U9Uht4jijSwbihlt64BJbNHmA7bEYs7FvM1WHUcUVkGQnmRUFBGqQXgN7loYNYOY5GMNcsTHTsNTYLQCQoah2EvvScycsbizECZHZ45/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391435; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=92AClQgNXABacQ0i61DaYrNKkj8PxXy6qywPLdGfziI=; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=92AClQgNXABacQ0i61DaYrNKkj8PxXy6qywPLdGfziI=; b=KBHxp79qnB44H5MyTBLuOwUI1CUO5kzYtE2cLl+IS2YRaYx0dK3lIqZDU7yENZQjc4 yQAelPZqpY1p5DnzJMBC/HyP++d97PGcRcbat40mM/MHZZkeh9Hu8LiUXnxYICFAigAN fkb3XSVDezESkxuPSZQuo42oVOagi2F3j8rLclIW0wyURj3VNmJPZQAr1He0XleiWtv9 NDRxn6VS/iqDj5Z9+t3cBoopsyGkQfektf9aVSEkQ2Jw3MTvyWWwlZ06gXEX/enOKGVD yX9fUQ1Wh1AF4LIAx50i5n3yizLRqzEFz6VdO2kC2a5iuDgBxXfDumtZt8R3BjQErpZ+ xOmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=92AClQgNXABacQ0i61DaYrNKkj8PxXy6qywPLdGfziI=; b=cS1oInutvkylfuBCY1qRD5D8n7789b/b7YdukxTgw1xgqJrcc1eja5MklkA0kp09gy tT6a+rQahIaSO/kao9U+fCwQCh8Pyr9fAjt+OPRwdUwt1JYHTAktk4pLmVwc9L59UVvh qIIgyUXqy7M3U6knT6anaFrP+0nOt7HGq0cDbC4FcFKzvnVentwz2ikSOdo7Ug/DnJoD /AvEWTTatU4nb4EQunZqs/YApabmhr7+PB8NGHKDyaoHU8GvnAPJPJM+K3KORJ3gKeH+ d5lP5nkbs3ss4bOn7v6MyhFR+D1DZmz9IZs6dmdGmmsKv5CgswqCoshNqKPNvhWLrUQp Js1g== X-Gm-Message-State: AOAM530FUu5EoMOpdz4/8tYBCNIfzJZWNWByyPGE1grYtqQYmVKPc6HL gkcyjzpDytUNhtSudDnCdZTUtQEg23rH3Q== X-Google-Smtp-Source: ABdhPJxw8zA6ZN4TKbN2+ABXBvzw8JwlC4F6Yl4aDDu3MLwomwmrW6fc1IHgkdty5lENgdUPzMdFaQ== X-Received: by 2002:a63:4e56:: with SMTP id o22mr7715010pgl.381.1598389253174; Tue, 25 Aug 2020 14:00:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Date: Tue, 25 Aug 2020 13:59:22 -0700 Message-Id: <20200825205950.730499-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that FSR is no longer a tcg global temp, we can say that the fpu helpers do not write to tcg temps. All temps are read implicitly by the fpu exception path. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 79e1e8ecc7..64816c89e1 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -3,21 +3,21 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noret= urn, env, i32) DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) =20 -DEF_HELPER_3(fadd, i32, env, i32, i32) -DEF_HELPER_3(frsub, i32, env, i32, i32) -DEF_HELPER_3(fmul, i32, env, i32, i32) -DEF_HELPER_3(fdiv, i32, env, i32, i32) -DEF_HELPER_2(flt, i32, env, i32) -DEF_HELPER_2(fint, i32, env, i32) -DEF_HELPER_2(fsqrt, i32, env, i32) +DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(frsub, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_2(flt, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fint, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(fsqrt, TCG_CALL_NO_WG, i32, env, i32) =20 -DEF_HELPER_3(fcmp_un, i32, env, i32, i32) -DEF_HELPER_3(fcmp_lt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_eq, i32, env, i32, i32) -DEF_HELPER_3(fcmp_le, i32, env, i32, i32) -DEF_HELPER_3(fcmp_gt, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ne, i32, env, i32, i32) -DEF_HELPER_3(fcmp_ge, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_un, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_lt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_eq, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_le, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_gt, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32) =20 DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390496; cv=none; d=zohomail.com; s=zohoarc; b=WcZ2h2vBu26l3s6zeX0un5c3G/e6I2NAXOSAj54uFIfO6SbtmbMWf8+dqDWnWTP5rKMJISxa1hFwfE9TSEqws/ea5wGkWg83gQ6qIMttYI6gyejDj3pBSC+LzlG90gTTXRThL/2+QmgL8vvD9duF5PzsMKMSfsCAk3G36OMemio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390496; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lr71+uB2rqlQWi1mZS+Omspl/b6K02nPk8zKl55dRRU=; b=aE/RNhKKB+wyPGMgc3v/5BEY/tU2w00LCr0p02G5Mu8/905Fu9higAL2zww9AcSyhW7eSx3Cot3+6TIaEl2eR7t/nbqpp/oj7Q58aZ7//uLbklMswTKc2umnkMTDauLW5DPLjNDd+i3wazOjRZwXdohbCt8hm+i8hv0IX87m1Ko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390496350737.7805874425833; Tue, 25 Aug 2020 14:21:36 -0700 (PDT) Received: from localhost ([::1]:38912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgNr-0007S9-3b for importer@patchew.org; Tue, 25 Aug 2020 17:21:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3t-0008Sx-U7 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:57 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:51218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3r-0001ym-W3 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:57 -0400 Received: by mail-pj1-x1042.google.com with SMTP id ds1so127720pjb.1 for ; Tue, 25 Aug 2020 14:00:55 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lr71+uB2rqlQWi1mZS+Omspl/b6K02nPk8zKl55dRRU=; b=xJwhO4GkFEIATLuB40u5lM7hIblRgfF2xH+g39N9MOv4qzLRNC1VSzJFU5snBvfZPO 8piLzuBeOwlB4uxhCMZBnV67tVpc0NhvPAsyStYU6eBpm2fWm7IaybIsz6iZsCO5IhQD jZo0UHcp2CTmRjLRbTcr+VUX2Zx9303xYJqjbOVW2yFz7bZ2PLZgLscDiBbJx9TrMNk6 Lzw7dp2gXSLBiZJ/JujiqDZHI4IVPwPG7j8gLLbr+7FUzBCR1twaVDziTzuPknw0r7Su YAOrwkFfZqm0KxwlM06TZSdXW9MxPo1ba3HCxNpb7HiKUcvDXhc57Gna+nOLFTDDSyur aSfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lr71+uB2rqlQWi1mZS+Omspl/b6K02nPk8zKl55dRRU=; b=RfmdvJ2D+pkM6qBon/e8CNILbWnzcfdxOcyEjAuQqTyslo6AydMJF2NypQvkGYNB4t fpqhH+jm6CSnAD9JahvUZVeqCiX0DmkRpmt6mFUZoEOc60vlTO82dSnDiTRxBjtikhB3 28fnIsd8We9EYk4xPoMqjrGXeZVuucyDmHNISWyG0EIz+LVHwN6npz47fAT9zvyatk14 P7e0/W6HQzUXCh0k3uuGhK4SgiHq+XVjzOsX9+1uqoXS4GVuIaOZh0+TA08HcpuJo0/J Qmeilmi7IGtQdrA031YC4ts/O84ikuBVrloT3iypRm3sjodZ78+7CGhPk0zG3+xYPY+A 8nsQ== X-Gm-Message-State: AOAM530sY8tJ114D2fVgpUt/y1HiEh8xPr9zjysdg6hImdlSJ23sXNi5 pKwPOYRxRJscZos7VwmB7EYsk2zoFidfUg== X-Google-Smtp-Source: ABdhPJybxn0bSrvHQxhD25Ecqmr2CfBs1e0P+0m9EHTCmfE90SeiQfnRhhx1PF+dTvOQj2wI6p8QzA== X-Received: by 2002:a17:90a:d510:: with SMTP id t16mr3293775pju.210.1598389254287; Tue, 25 Aug 2020 14:00:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Date: Tue, 25 Aug 2020 13:59:23 -0700 Message-Id: <20200825205950.730499-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 013858b8e0..594501e4e7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -254,7 +254,9 @@ struct CPUMBState { =20 /* Internal flags. */ #define IMM_FLAG 4 -#define MSR_EE_FLAG (1 << 8) +/* MSR_EE (1 << 8) */ +/* MSR_UM (1 << 11) */ +/* MSR_VM (1 << 13) */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7d1ada7aad..cb490488a6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -162,7 +162,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) */ static bool trap_illegal(DisasContext *dc, bool cond) { - if (cond && (dc->tb_flags & MSR_EE_FLAG) + if (cond && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.illegal_opcode_exception) { gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); } @@ -178,7 +178,7 @@ static bool trap_userspace(DisasContext *dc, bool cond) int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; =20 - if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { + if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); } return cond_user; --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391543; cv=none; d=zohomail.com; s=zohoarc; b=JGlLl8pBd4nrTykIYkakLfU7LxwYL267GqxInjMeafyZFRbG0izehtkZf+B9vzQZw35WfSyu82nQpUWQLoQvR89LVATrbXOXhIgKvzlSptOddV8bV8Ex4cjzqRLW65KfaZHIAoX6N7tq4jxQmAtMamK2McnOuvC5ixBZJbqZoAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391543; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=urcrD5NFXjwPKRscyzfCPuOFRd/yp7ofBRVH50uRonY=; b=eh26AA1z9eFry5zbJxU8aATZp6lWt4C73Hs/C234XB+OO70t6vPTeGyn4sBOSRJ2hQ/1WX1ZgZyN+GK3s4hvZ4PAQIzH2UPpQaF9p3Am+naqgJa7qS5q4o48PVZ9XisoHlxASgaBSye5ymxh6bA2wTGn3pXh6LWyhQaQU1Gspz4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391543404709.9289251543686; Tue, 25 Aug 2020 14:39:03 -0700 (PDT) Received: from localhost ([::1]:60398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgej-0005dn-Vx for importer@patchew.org; Tue, 25 Aug 2020 17:39:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3w-0008WE-Am for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:00 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:37544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3t-0001zE-K8 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:00:59 -0400 Received: by mail-pg1-x544.google.com with SMTP id g33so7674069pgb.4 for ; Tue, 25 Aug 2020 14:00:57 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=urcrD5NFXjwPKRscyzfCPuOFRd/yp7ofBRVH50uRonY=; b=C8Z2qsY7W3DgCrnXVzJA/tfYQkzOcZeSEpPy41F9NWTcSPTev5vDi2zhq0qOhfe6Xs PR35XOX2hkzwqiEmIwFLrsJLOj/RUZ21J+vB3Bjf9K6e6KMIAqMsq3bLAtQAVs+v8W+L uY8d1RPT2Cq6VvsjFSejeWPDHwjve2uJ5osmWRQPpzUDO0JpStlyDFedCBsaWXupXjxg 9GYQoKM06FRokkE7NT6csaUJzP2dM6dAGahD0/W5SaMFevMc4C/C1AxE4zueIxffc5up 7km7ruN4p69L8B1ezsTp9K4PPQQujEq4Vos+8M0L2O+OyGys7wdxsPyioNK1Tqb15GsS lpZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=urcrD5NFXjwPKRscyzfCPuOFRd/yp7ofBRVH50uRonY=; b=VrkQ6lC3hKwCVdKLM2LZbGjJ1c7AguIHExKrkPKjxVHfUACfVM74JgCTKOfi15AzmA G4dDzbZTISsg0d+JLvB2n2HlQ5Ty2hXstYAv7WCKg/DKqgbu/RjHaAiP1B592sioXzWS WO4ImrRu6INb92d8vkC9cxGw6JH0XigojZTDQ25YnyMkNPgxqOMzjSRr/i66LS/8OeAs Bp6FTg0kxlZpU6u8JD2HtyyxPzkvrdhORIwNSBoZh1kaQXfj9KpIlXnHO8L7bSoLxewy vJvB8yXc23wWZZZ9j513/QiCyMfXUISiOd1WyktppFLSZZ868ircl6GWkU0ZAvn4Ll1O wTJQ== X-Gm-Message-State: AOAM531HTfxdJFqYo+T7zHKYZ3+iW9ZgLDtezNhSww/6+MFYPvhoUM4H 6me9EzutTG9fuWW/lhq4lH+oNxFFstZjOA== X-Google-Smtp-Source: ABdhPJzkS8ll7HUSMh7X1UvTsWjO0CC5Mo4f5iANobusin1PDJXHqmItsDBPXF6Kbbinitczc1/Hsw== X-Received: by 2002:a63:a119:: with SMTP id b25mr7908105pgf.10.1598389255978; Tue, 25 Aug 2020 14:00:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 51/77] target/microblaze: Cache mem_index in DisasContext Date: Tue, 25 Aug 2020 13:59:24 -0700 Message-Id: <20200825205950.730499-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Ideally, nothing outside the top-level of translation even has access to env. Cache the value in init_disas_context. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index cb490488a6..8a251b35d9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { unsigned int delayed_branch; unsigned int tb_flags, synced_flags; /* tb dependent flags. */ unsigned int clear_imm; + int mem_index; =20 #define JMP_NOJMP 0 #define JMP_DIRECT 1 @@ -175,8 +176,7 @@ static bool trap_illegal(DisasContext *dc, bool cond) */ static bool trap_userspace(DisasContext *dc, bool cond) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - bool cond_user =3D cond && mem_index =3D=3D MMU_USER_IDX; + bool cond_user =3D cond && dc->mem_index =3D=3D MMU_USER_IDX; =20 if (cond_user && (dc->tb_flags & MSR_EE)) { gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); @@ -954,7 +954,7 @@ static void dec_load(DisasContext *dc) TCGv addr; unsigned int size; bool rev =3D false, ex =3D false, ea =3D false; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); + int mem_index =3D dc->mem_index; MemOp mop; =20 mop =3D dc->opcode & 3; @@ -1063,7 +1063,7 @@ static void dec_store(DisasContext *dc) TCGLabel *swx_skip =3D NULL; unsigned int size; bool rev =3D false, ex =3D false, ea =3D false; - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); + int mem_index =3D dc->mem_index; MemOp mop; =20 mop =3D dc->opcode & 3; @@ -1532,6 +1532,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; + dc->mem_index =3D cpu_mmu_index(&cpu->env, false); =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390358; cv=none; d=zohomail.com; s=zohoarc; b=njoKyTkUJufILs1h4YJY7T4/hXXZITemlAmRKc+go7EQBUQxmtcV7QUOzvuiZHki6rdpl23JuWvuh4/hjhyyb8nk9KonIOIauOPa5YYvLJvKCkDSXER9Ztb1VERQdYoGFxryb3Q/+dhd5ErZ3FQVXDeR0r9iWt4G6ArMKU86pPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390358; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R2cuEf3Qt/jcGcIZclz+3Hjy1ReL2CdcRjCqzKw0P3k=; b=OspT1SfIv74YCi7+Bouy3QFnw0vZhWz9mvzdPuwLSf5mfKfOTsmHDk56fg9F8JqpJHBo44qUxf2cS6jKX4KvWN9NN8ZiWCrpIbrgUYzhxREsMZSuesSjjHcUwxSLBuu7pGvNwsD6WyPO6GazcNyJNCi4xiK/MSomB90uTc9Tkjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390358513969.223829083749; Tue, 25 Aug 2020 14:19:18 -0700 (PDT) Received: from localhost ([::1]:56388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgLd-0002tD-6i for importer@patchew.org; Tue, 25 Aug 2020 17:19:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg3y-00005t-JF for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:02 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:37544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3v-0001zQ-KZ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:02 -0400 Received: by mail-pg1-x543.google.com with SMTP id g33so7674102pgb.4 for ; Tue, 25 Aug 2020 14:00:58 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R2cuEf3Qt/jcGcIZclz+3Hjy1ReL2CdcRjCqzKw0P3k=; b=y7j3LQ8ylTbYEThvqr4pjXq1SJaaM+ejNwiqt3pPalI8eEIngELZet7AzpvhZUCIbK UT6kcLnuLzCRpKJRaBEdQg0CcQvOLN94WxIrWx2kpQR5BSHISh6qtmzN+WsMPJfR+y1x jn1CJcegAJ5ULs+cEubVud5X6T2oBxqqLmttC4WRSk68hmNvf8UjIJZPCkGCcw2bVWS8 Dc23wCLpbwcU4EIbdUhCF+HhMrPF33Tf6colk+3SZrJkbh6tZ8IYeBBQ62NF4hiXlLV4 /HYz1tGyinXNirsETo5+N6meIcqpl4qWVM6YmQscBTpqMCjzhjuYoN1dPPW+8U8YR7Fn Uo9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R2cuEf3Qt/jcGcIZclz+3Hjy1ReL2CdcRjCqzKw0P3k=; b=fmFI8FhhTutP0rb1JhMT2so9Jt5TklK/1pHPW9hDsCx2jPl3fCJNjZ1A5iVzn8wHOd jjJJryiI8thdRZ46RwliHz4KEe2xfW8rOM3VGW8IkRyUocVaCA8PAItM+VbWSPkALJaR CiKFnHABaPJpsjMSm7EQBTX7Id9ucU+fKsiHBtNviJrLCywEAyfL5pK7CvHPJ5TCMCYx JZ7WpiSqTvklmM/tVphHXiHZYjfJj4mHL3C6TU/lFvCfpjuyqX42iqvPJDjClP4zhhJe czYy4Tre5Ifl9YHAC1m/tb/KzjBQVhnYJEcIvdfKAQyiG4CPNlcZQ1r6ehVoYODqAARa YR9Q== X-Gm-Message-State: AOAM530sWTwx/oEVAOOoiTKYj3XEiPcZQ6s1lJMGFmLoNWPZv9LNZOHk lS0tw5BQDUSCxtJfh/4hGUrDUVN4IeMyEA== X-Google-Smtp-Source: ABdhPJw084YLCaztS/w94Nssbz87gRFUwCbLnFVpIGNMKaKRT2uQeIplqYgVD+6SpiepcM2plaX64w== X-Received: by 2002:a63:ec04:: with SMTP id j4mr7979363pgh.393.1598389257218; Tue, 25 Aug 2020 14:00:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 52/77] target/microblaze: Fix cpu unwind for stackprot Date: Tue, 25 Aug 2020 13:59:25 -0700 Message-Id: <20200825205950.730499-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Restore the correct PC when an exception must be raised. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 2 +- target/microblaze/op_helper.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 64816c89e1..a473c1867b 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -26,7 +26,7 @@ DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif =20 DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) -DEF_HELPER_2(stackprot, void, env, tl) +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) =20 DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 2c59d4492d..a99c467364 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -389,12 +389,16 @@ void helper_memalign(CPUMBState *env, target_ulong ad= dr, void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { + CPUState *cs =3D env_cpu(env); + qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); + env->ear =3D addr; env->esr =3D ESR_EC_STACKPROT; - helper_raise_exception(env, EXCP_HW_EXCP); + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, GETPC()); } } =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391650; cv=none; d=zohomail.com; s=zohoarc; b=US/5TYadQ4yPpg4h5R5DtC9Rc/g3FI5Rk5sshz7orfAdPJ65jjEmqMOUIFLF1InLJB9kzD4ajUlaFSVC0XxHII9R/x82xu9A8Sk/3YHh43tdR9j9hC4quHQC4NH71XAVXkjVkJyX56meS9KoV5h1wiFnyp3F1Le7IdlLjH7jrzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391650; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WyzqXCeR3DuXy4jQfHiKsdQqH3q0PeYbF+siivFcZWI=; b=Ov3RgD7FcQZ3Of6VwdacUQi3NXlzrVYANrgrN3YHT9yehRXb6A56cZm6MFMyl1HK3p+gvMsF3FaRGsJkkt2JipPASKR92Fo7Dymt0BSbK7aDlB79Qu4WeBW9mrCPa55sfGr52mSCFzLPQ2Yd1TyE8aTiglEt3fA66zxoykpQjo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391650300575.112662181043; Tue, 25 Aug 2020 14:40:50 -0700 (PDT) Received: from localhost ([::1]:38598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAggS-0008Fy-QO for importer@patchew.org; Tue, 25 Aug 2020 17:40:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg42-00007u-As for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:06 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:43792) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3y-0001ze-6d for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:05 -0400 Received: by mail-pf1-x434.google.com with SMTP id y206so8288251pfb.10 for ; Tue, 25 Aug 2020 14:01:00 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WyzqXCeR3DuXy4jQfHiKsdQqH3q0PeYbF+siivFcZWI=; b=WTHBusgNkeDzvvSu4OaXylpBYB+PHtb/dvBPTuBd39UeZSLnWlTpTVkRxZlVUlQT1I 7ndxpIjcBFjSPHzztMGSelMOjZ+Suu+5q9Ht2ozbwdJnno7zYpoEFpWV76E6GEGCO97j Nv9lg9YhYysePC2EcGK3a8zbzdFEWzlJ1OqMDIFvhIr1ofBATuMpYAQ4WPcJ04N6/sso 88cCBV900OmcsowZIf1AaVFMSOZsBpwiLdEPylDnDnyG3Qi7WjgTyw+vG3KBJCLi9ObP tkKyawcO8T88GdhkID0bZzj8e1hS69HgI6DhGP0NRlOyybYJpVd6HNHoWVRWLoag+1Ka bxBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WyzqXCeR3DuXy4jQfHiKsdQqH3q0PeYbF+siivFcZWI=; b=UM/ksLh9Oa093SEyr8IrcjYLG83rE1OynG4V7BTZ7eckwvzwVC+iHiFK9ZiNOe8Xfg TwTR+ri9X4/Rd4Yp/Uh92bAQV0KcKAtidAbb02zLUg5LtCLLXhb3dZ4o4DjpEj5bATLW QooB0cYxESGSuY03voIY06gLhZT+eLq3rmMXQCVTFdVGXLz0gibu21uQ/ZwmwxUDhhqn mdZRltYUuGx8ZtpfEiFKLcvpTsCHAhwjNPR7gDr6WRguLK/q8rPqkv/UrDjCmoeIlvf9 VnmlO3+ac1miBSQQ/I6nDnbjXptCoeGBS9zqi0zhrtmFcR174CR0bjGnsWcBfI2z9Y8I 5zvQ== X-Gm-Message-State: AOAM533wyeTe+yZ1Z8R7mcT69uGKnM9gwAfHAR9obilk+sEoscemDVe9 Le4NCUTEs0lyc4RsV1W+otQfZaQ4DT+/wQ== X-Google-Smtp-Source: ABdhPJxqHvfPDIUDI3CCPAehAnMn3qE7gKcRQbIJm/H+6c8L7JlNHKTJ/eGAZ3XK6T3o6TzClqH/oQ== X-Received: by 2002:a63:dc4a:: with SMTP id f10mr7713657pgj.394.1598389258750; Tue, 25 Aug 2020 14:00:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 53/77] target/microblaze: Convert dec_load and dec_store to decodetree Date: Tue, 25 Aug 2020 13:59:26 -0700 Message-Id: <20200825205950.730499-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 32 ++ target/microblaze/translate.c | 723 +++++++++++++++++++-------------- 2 files changed, 456 insertions(+), 299 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index ea6743c7e5..998f997adc 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -97,6 +97,22 @@ idivu 010010 ..... ..... ..... 000 0000 0010 = @typea =20 imm 101100 00000 00000 imm:16 =20 +lbu 110000 ..... ..... ..... 0000 000 0000 @typea +lbur 110000 ..... ..... ..... 0100 000 0000 @typea +lbuea 110000 ..... ..... ..... 0001 000 0000 @typea +lbui 111000 ..... ..... ................ @typeb + +lhu 110001 ..... ..... ..... 0000 000 0000 @typea +lhur 110001 ..... ..... ..... 0100 000 0000 @typea +lhuea 110001 ..... ..... ..... 0001 000 0000 @typea +lhui 111001 ..... ..... ................ @typeb + +lw 110010 ..... ..... ..... 0000 000 0000 @typea +lwr 110010 ..... ..... ..... 0100 000 0000 @typea +lwea 110010 ..... ..... ..... 0001 000 0000 @typea +lwx 110010 ..... ..... ..... 1000 000 0000 @typea +lwi 111010 ..... ..... ................ @typeb + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea @@ -120,6 +136,22 @@ rsubic 001011 ..... ..... ................ = @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb =20 +sb 110100 ..... ..... ..... 0000 000 0000 @typea +sbr 110100 ..... ..... ..... 0100 000 0000 @typea +sbea 110100 ..... ..... ..... 0001 000 0000 @typea +sbi 111100 ..... ..... ................ @typeb + +sh 110101 ..... ..... ..... 0000 000 0000 @typea +shr 110101 ..... ..... ..... 0100 000 0000 @typea +shea 110101 ..... ..... ..... 0001 000 0000 @typea +shi 111101 ..... ..... ................ @typeb + +sw 110110 ..... ..... ..... 0000 000 0000 @typea +swr 110110 ..... ..... ..... 0100 000 0000 @typea +swea 110110 ..... ..... ..... 0001 000 0000 @typea +swx 110110 ..... ..... ..... 1000 000 0000 @typea +swi 111110 ..... ..... ................ @typeb + sext8 100100 ..... ..... 00000 000 0110 0000 @typea0 sext16 100100 ..... ..... 00000 000 0110 0001 @typea0 =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 8a251b35d9..42d6d2a593 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -105,6 +105,17 @@ static inline void t_sync_flags(DisasContext *dc) } } =20 +static inline void sync_jmpstate(DisasContext *dc) +{ + if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { + if (dc->jmp =3D=3D JMP_DIRECT) { + tcg_gen_movi_i32(cpu_btaken, 1); + } + dc->jmp =3D JMP_INDIRECT; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + } +} + static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp =3D tcg_const_i32(index); @@ -668,6 +679,419 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a) DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) =20 +static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) +{ + TCGv ret =3D tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra && rb) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else if (ra) { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + } else if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + + if ((ra =3D=3D 1 || rb =3D=3D 1) && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) +{ + TCGv ret =3D tcg_temp_new(); + + /* If any of the regs is r0, set t to the value of the other reg. */ + if (ra) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[ra], imm); + tcg_gen_extu_i32_tl(ret, tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_movi_tl(ret, (uint32_t)imm); + } + + if (ra =3D=3D 1 && dc->cpu->cfg.stackprot) { + gen_helper_stackprot(cpu_env, ret); + } + return ret; +} + +static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +{ + int addr_size =3D dc->cpu->cfg.addr_size; + TCGv ret =3D tcg_temp_new(); + + if (addr_size =3D=3D 32 || ra =3D=3D 0) { + if (rb) { + tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + } else { + tcg_gen_movi_tl(ret, 0); + } + } else { + if (rb) { + tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); + } else { + tcg_gen_extu_i32_tl(ret, cpu_R[ra]); + tcg_gen_shli_tl(ret, ret, 32); + } + if (addr_size < 64) { + /* Mask off out of range bits. */ + tcg_gen_andi_i64(ret, ret, MAKE_64BIT_MASK(0, addr_size)); + } + } + return ret; +} + +static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + TCGv_i32 v; + MemOp size =3D mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^=3D MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* + * Microblaze gives MMU faults priority over faults due to + * unaligned addresses. That's why we speculatively do the load + * into v. If the load succeeds, we verify alignment of the + * address and if that succeeds we write into the destination reg. + */ + v =3D tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t0 =3D tcg_const_i32(0); + TCGv_i32 treg =3D tcg_const_i32(rd); + TCGv_i32 tsize =3D tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + if (rd) { + tcg_gen_mov_i32(cpu_R[rd], v); + } + + tcg_temp_free_i32(v); + tcg_temp_free(addr); + return true; +} + +static bool trans_lbu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lbur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_lbuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_lbui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_lhu(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lhur(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_lhuea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_lhui(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_lw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_lwea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_lwi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_lwx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + + /* lwx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_mov_tl(cpu_res_addr, addr); + tcg_temp_free(addr); + + if (arg->rd) { + tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val); + } + + /* No support for AXI exclusive so always clear C */ + tcg_gen_movi_i32(cpu_msr_c, 0); + return true; +} + +static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, + int mem_index, bool rev) +{ + MemOp size =3D mop & MO_SIZE; + + /* + * When doing reverse accesses we need to do two things. + * + * 1. Reverse the address wrt endianness. + * 2. Byteswap the data lanes on the way back into the CPU core. + */ + if (rev) { + if (size > MO_8) { + mop ^=3D MO_BSWAP; + } + if (size < MO_32) { + tcg_gen_xori_tl(addr, addr, 3 - size); + } + } + + t_sync_flags(dc); + sync_jmpstate(dc); + + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + + /* TODO: Convert to CPUClass::do_unaligned_access. */ + if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { + TCGv_i32 t1 =3D tcg_const_i32(1); + TCGv_i32 treg =3D tcg_const_i32(rd); + TCGv_i32 tsize =3D tcg_const_i32((1 << size) - 1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + /* FIXME: if the alignment is wrong, we should restore the value + * in memory. One possible way to achieve this is to probe + * the MMU prior to the memaccess, thay way we could put + * the alignment checks in between the probe and the mem + * access. + */ + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); + } + + tcg_temp_free(addr); + return true; +} + +static bool trans_sb(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sbr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true); +} + +static bool trans_sbea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +} + +static bool trans_sbi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); +} + +static bool trans_sh(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_shr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); +} + +static bool trans_shea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +} + +static bool trans_shi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); +} + +static bool trans_sw(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swr(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); +} + +static bool trans_swea(DisasContext *dc, arg_typea *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); + return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +} + +static bool trans_swi(DisasContext *dc, arg_typeb *arg) +{ + TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); +} + +static bool trans_swx(DisasContext *dc, arg_typea *arg) +{ + TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCGLabel *swx_done =3D gen_new_label(); + TCGLabel *swx_fail =3D gen_new_label(); + TCGv_i32 tval; + + t_sync_flags(dc); + sync_jmpstate(dc); + + /* swx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(addr, addr, ~3); + + /* + * Compare the address vs the one we used during lwx. + * On mismatch, the operation fails. On match, addr dies at the + * branch, but we know we can use the equal version in the global. + * In either case, addr is no longer needed. + */ + tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail); + tcg_temp_free(addr); + + /* + * Compare the value loaded during lwx with current contents of + * the reserved location. + */ + tval =3D tcg_temp_new_i32(); + + tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, + reg_for_write(dc, arg->rd), + dc->mem_index, MO_TEUL); + + tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); + tcg_temp_free_i32(tval); + + /* Success */ + tcg_gen_movi_i32(cpu_msr_c, 0); + tcg_gen_br(swx_done); + + /* Failure */ + gen_set_label(swx_fail); + tcg_gen_movi_i32(cpu_msr_c, 1); + + gen_set_label(swx_done); + + /* + * Prevent the saved address from working again without another ldx. + * Akin to the pseudocode setting reservation =3D 0. + */ + tcg_gen_movi_tl(cpu_res_addr, -1); + return true; +} + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -873,303 +1297,6 @@ static void dec_msr(DisasContext *dc) } } =20 -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { - if (dc->jmp =3D=3D JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp =3D JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - -static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) -{ - /* Should be set to true if r1 is used by loadstores. */ - bool stackprot =3D false; - TCGv_i32 t32; - - /* All load/stores use ra. */ - if (dc->ra =3D=3D 1 && dc->cpu->cfg.stackprot) { - stackprot =3D true; - } - - /* Treat the common cases first. */ - if (!dc->type_b) { - if (ea) { - int addr_size =3D dc->cpu->cfg.addr_size; - - if (addr_size =3D=3D 32) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } - - tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); - if (addr_size < 64) { - /* Mask off out of range bits. */ - tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); - } - return; - } - - /* If any of the regs is r0, set t to the value of the other reg. = */ - if (dc->ra =3D=3D 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); - return; - } else if (dc->rb =3D=3D 0) { - tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); - return; - } - - if (dc->rb =3D=3D 1 && dc->cpu->cfg.stackprot) { - stackprot =3D true; - } - - t32 =3D tcg_temp_new_i32(); - tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; - } - /* Immediate. */ - t32 =3D tcg_temp_new_i32(); - tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); - tcg_gen_extu_i32_tl(t, t32); - tcg_temp_free_i32(t32); - - if (stackprot) { - gen_helper_stackprot(cpu_env, t); - } - return; -} - -static void dec_load(DisasContext *dc) -{ - TCGv_i32 v; - TCGv addr; - unsigned int size; - bool rev =3D false, ex =3D false, ea =3D false; - int mem_index =3D dc->mem_index; - MemOp mop; - - mop =3D dc->opcode & 3; - size =3D 1 << mop; - if (!dc->type_b) { - ea =3D extract32(dc->ir, 7, 1); - rev =3D extract32(dc->ir, 9, 1); - ex =3D extract32(dc->ir, 10, 1); - } - mop |=3D MO_TE; - if (rev) { - mop ^=3D MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - if (trap_userspace(dc, ea)) { - return; - } - - t_sync_flags(dc); - addr =3D tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index =3D ea ? MMU_NOMMU_IDX : mem_index; - - /* - * When doing reverse accesses we need to do two things. - * - * 1. Reverse the address wrt endianness. - * 2. Byteswap the data lanes on the way back into the CPU core. - */ - if (rev && size !=3D 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - /* lwx does not throw unaligned access errors, so force alignment */ - if (ex) { - tcg_gen_andi_tl(addr, addr, ~3); - } - - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - - /* Verify alignment if needed. */ - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t0 =3D tcg_const_i32(0); - TCGv_i32 treg =3D tcg_const_i32(dc->rd); - TCGv_i32 tsize =3D tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - tcg_gen_mov_tl(cpu_res_addr, addr); - tcg_gen_mov_i32(cpu_res_val, v); - } - if (dc->rd) { - tcg_gen_mov_i32(cpu_R[dc->rd], v); - } - tcg_temp_free_i32(v); - - if (ex) { /* lwx */ - /* no support for AXI exclusive so always clear C */ - tcg_gen_movi_i32(cpu_msr_c, 0); - } - - tcg_temp_free(addr); -} - -static void dec_store(DisasContext *dc) -{ - TCGv addr; - TCGLabel *swx_skip =3D NULL; - unsigned int size; - bool rev =3D false, ex =3D false, ea =3D false; - int mem_index =3D dc->mem_index; - MemOp mop; - - mop =3D dc->opcode & 3; - size =3D 1 << mop; - if (!dc->type_b) { - ea =3D extract32(dc->ir, 7, 1); - rev =3D extract32(dc->ir, 9, 1); - ex =3D extract32(dc->ir, 10, 1); - } - mop |=3D MO_TE; - if (rev) { - mop ^=3D MO_BSWAP; - } - - if (trap_illegal(dc, size > 4)) { - return; - } - - trap_userspace(dc, ea); - - t_sync_flags(dc); - /* If we get a fault on a dslot, the jmpstate better be in sync. */ - sync_jmpstate(dc); - /* SWX needs a temp_local. */ - addr =3D ex ? tcg_temp_local_new() : tcg_temp_new(); - compute_ldst_addr(dc, ea, addr); - /* Extended addressing bypasses the MMU. */ - mem_index =3D ea ? MMU_NOMMU_IDX : mem_index; - - if (ex) { /* swx */ - TCGv_i32 tval; - - /* swx does not throw unaligned access errors, so force alignment = */ - tcg_gen_andi_tl(addr, addr, ~3); - - tcg_gen_movi_i32(cpu_msr_c, 1); - swx_skip =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); - - /* - * Compare the value loaded at lwx with current contents of - * the reserved location. - */ - tval =3D tcg_temp_new_i32(); - - tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, - cpu_R[dc->rd], mem_index, - mop); - - tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); - tcg_gen_movi_i32(cpu_msr_c, 0); - tcg_temp_free_i32(tval); - } - - if (rev && size !=3D 4) { - /* Endian reverse the address. t is addr. */ - switch (size) { - case 1: - { - tcg_gen_xori_tl(addr, addr, 3); - break; - } - - case 2: - /* 00 -> 10 - 10 -> 00. */ - /* Force addr into the temp. */ - tcg_gen_xori_tl(addr, addr, 2); - break; - default: - cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); - break; - } - } - - if (!ex) { - tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); - } - - /* Verify alignment if needed. */ - if (dc->cpu->cfg.unaligned_exceptions && size > 1) { - TCGv_i32 t1 =3D tcg_const_i32(1); - TCGv_i32 treg =3D tcg_const_i32(dc->rd); - TCGv_i32 tsize =3D tcg_const_i32(size - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); - } - - if (ex) { - gen_set_label(swx_skip); - } - - tcg_temp_free(addr); -} - static inline void eval_cc(DisasContext *dc, unsigned int cc, TCGv_i32 d, TCGv_i32 a) { @@ -1477,8 +1604,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_LD, dec_load}, - {DEC_ST, dec_store}, {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390469; cv=none; d=zohomail.com; s=zohoarc; b=AxIND7PBtNfXqA9+OS29KQEcRkjcRR1wWn9JVUXmYHu8ShHXS9wXVsiVgE2rLMQjfogjyBeyeTSRO3DKK0uAXI5J/LaxrVlcEVUcnVHhCQsSPLPCj9goo6M+ZOWr9kvuVq/ys52mFn8k+S6eL3UUbOhBZwv2G0ILl7zs+rfTlSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390469; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=Pk240yUuYgqeMeKO9tGUcWYoRMgIwXIV0A08MIkurBZBeAArOLqd1YRiSxWgLETswK37M5IRLKtxd5fS4SkTbmDuky1E2DiTWIRdju19kiyDtYq8zGROkZU02RSCHBy4VzZKdkH8lGWYQoViFjesHby4yupfjDdps3JX8POXteA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390469064372.8329794805875; Tue, 25 Aug 2020 14:21:09 -0700 (PDT) Received: from localhost ([::1]:36312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgNP-0006Ob-Rw for importer@patchew.org; Tue, 25 Aug 2020 17:21:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg40-00006c-Cp for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:04 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:37182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3y-0001zi-74 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:04 -0400 Received: by mail-pj1-x1042.google.com with SMTP id mw10so125102pjb.2 for ; Tue, 25 Aug 2020 14:01:01 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=qQpzcyXPHl5M2j5TPXNFFdiSYbAEmQ3fn4o0rqJKPi2ReviyKR89mQP3kQC8ZmUse6 6pWzET3aU3LrOT58ZejZZ//AqmjVl57MhjNpNzkBUSF2WWp60YlFzBtSmdYASTv1oD5O lRrWQXIP2qZzG6HUTHnoqFNd31uoW3nHCkK3zzl5Acyye7ZhUdX+7rsauxeyxHs3gTAf oYb4zQmYgMeBUtNcCMZ0qeLXn4QQ65Po3dniUrwTOFgKI2TpcKLijihXDQQMUHJb5eEi GHLFMVvpcx7v88HN9AtKj3spm4lnj5OcjAv7meCPAKBHmyTtvjr7UtlOSa41AQzvBdOE et0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=50E0hW76gnTgLCYM21b2+hcWFagS0hoFg/XoJTnl9H8=; b=ugJTGPKSeCQkGnmSGWQUf9rRto9dmg70cJ8SS6WYxaBiGg8F7SzcWwPO4mAfzpf/Je YZ4J9XL9k3OKPg8ff2RqQlDyqd6d+RxsJxAIRe9hnGL5+cxlBbdP+zusLawepMsAKzjc ZW4LcPxKyF98K/6wq0llLOD33WVglJGW3G9pO2qJKnHVoQ4zI7Ns8xAtDsu64BzPhORc URaVAbYKsAVp7ncFovTwhl1vP3x5cM2Dn+h4D55HYVoREK78NTRBWw1+ytK5fu+kt/9O +CY7pZyBPMZpXfPkRHlXrmTa+p3J6ueb5/UwcUxZSmhfF8FQH2XVVvpxtBx2+KifPVhI aQSg== X-Gm-Message-State: AOAM533UNKC/EjxvmdN0Y5WQyjugTaehcv26N6qFvr4NjPhrehlKAL4J 9Kwyen8+6ZzfhFfYQkitf5kWYoZxyaXrCA== X-Google-Smtp-Source: ABdhPJyw8+AdkWYQCVGur+z4KFmsCkuFJrprta2T019tMcFqehLZttCj5o21jVn5WTi3JEeB4iXZIQ== X-Received: by 2002:a17:90b:110a:: with SMTP id gi10mr3107685pjb.104.1598389259764; Tue, 25 Aug 2020 14:00:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 54/77] target/microblaze: Assert no overlap in flags making up tb_flags Date: Tue, 25 Aug 2020 13:59:27 -0700 Message-Id: <20200825205950.730499-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 594501e4e7..2fc7cf26f1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -261,8 +261,11 @@ struct CPUMBState { #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) #define D_FLAG (1 << 19) /* Bit in ESR. */ + /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_= FLAG) +#define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) + uint32_t iflags; =20 #if !defined(CONFIG_USER_ONLY) @@ -372,12 +375,14 @@ typedef MicroBlazeCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 +/* Ensure there is no overlap between the two masks. */ +QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); + static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | - (env->msr & (MSR_UM | MSR_VM | MSR_EE)); + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); } =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390550; cv=none; d=zohomail.com; s=zohoarc; b=lzSAmjXeLY0DzIwx7jv4Rh/p+WkkcqkM4RHFNjISfGfNIsLNQumMk5siydwr6tmo+CBZnV96KhX0OctzcEAdCmZbIBIss4ZaWKeOx9TxrwaQudgiTLX4WA0tumU40zyboSEQnTt2VcLcuNX5OIVTs62ATPBOAvgJ62VS3WJU074= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8b0bp9mk+1WbNfIATZBmVlR2NfvcC4JEryF82Ik81YY=; b=LOo3SrWUS6Wa58UT3xGr/IerpZ5qqZ3HQBmun83mEjxKVyxv0+57EqIdr2Bw0X0LORBgyYpyL6cdny43IPOU/Fg/u+lrOk/P851rNmMnLvb4vPGCbR8Bl4PTDNEA9SxDQ12HqrevXq0jtFv3tneDaNglCXEQS8Am+EdaXfl4S6w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390550859867.6190429199206; Tue, 25 Aug 2020 14:22:30 -0700 (PDT) Received: from localhost ([::1]:44238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgOj-0001Cj-JO for importer@patchew.org; Tue, 25 Aug 2020 17:22:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg43-000099-6a for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:08 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:56102) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg3z-0001zq-6t for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:06 -0400 Received: by mail-pj1-x102f.google.com with SMTP id 2so118328pjx.5 for ; Tue, 25 Aug 2020 14:01:02 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8b0bp9mk+1WbNfIATZBmVlR2NfvcC4JEryF82Ik81YY=; b=r2HUuPvhKirChEZkUK4KJtTJepETf/6ibKth2j7LthDaibAOMUyHDGPttbFvSVoPrm C0u4l7nJDt9e5WaFlon9bNzBC5mL1dBYmxYTo4zQFDo+hOIZ63CdVSMgw4+IgCqeHg8Q dHQ5Dwz2kgkL7sS0vviy/r/P++szwMibw0unNxk7Sev5vB168PtNMTGgiV1VBe9Upczl PCOpcxCmih2CZGa4451c/HsrSO6qOJE8EpaJsqs7BMvyXh/slnfTGHtBqKdjId9cOxfl M2bxTAdJm4JYMxuQeLpOz7fMFDf24dz3t1/auM6jX+GX2usLaw/my3g/lw6EeGeM/MHH nO+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8b0bp9mk+1WbNfIATZBmVlR2NfvcC4JEryF82Ik81YY=; b=k4fApancvQgYrGJLGOOz++2EILUGM12nabdmu5MKpygOSxgPzzReQf9fah2QAe6BzA mTuZTy/nwDKbefPDUiij4QtAbqRRuhCEkwgRLqLErDyg3UEPalRGvVSGW91YkyFlSRxW 6dAvsdj1qC7CrB3YHlzdwbh2QSkowdNva2BARcdFZVfbIEFvn3H+0l0NZDHyVBRCnhBi UHfxU4syo0ivluJF3n0b/FElzv7QLWN1sW6LKsWC+enZfS+FoHjtmdny9uwdKU3oyqCt 3eTZjYHtnTWNtI/NYgw1roUfLjsZZPBQbo0Ubm2L3ntuycULqxpjTqsnATYFtPb+1gvP fasg== X-Gm-Message-State: AOAM533ai1pF4B3UlRzCvj1JllW2UwgkrJsBdL+OqlK5R69yx5zAytr1 DBU/Hkloe+hClpHtbFW7GzJV6XaAlkYNmA== X-Google-Smtp-Source: ABdhPJy92C8yJUoJLSw6lQRCe3zrFRjRsaL+lsk2+yuHn9MS+isRdn0E/lV+eGfmnF5k32i78bnSNQ== X-Received: by 2002:a17:90b:40cb:: with SMTP id hj11mr3227959pjb.67.1598389260896; Tue, 25 Aug 2020 14:01:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 55/77] target/microblaze: Move bimm to BIMM_FLAG Date: Tue, 25 Aug 2020 13:59:28 -0700 Message-Id: <20200825205950.730499-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular significance; pack these two flags at the bottom of the bitfield. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 ++-- target/microblaze/helper.c | 2 +- target/microblaze/translate.c | 12 +++++------- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2fc7cf26f1..a5df1fa28f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,7 +231,6 @@ typedef struct CPUMBState CPUMBState; struct CPUMBState { uint32_t btaken; uint32_t btarget; - uint32_t bimm; =20 uint32_t imm; uint32_t regs[32]; @@ -253,7 +252,8 @@ struct CPUMBState { uint32_t res_val; =20 /* Internal flags. */ -#define IMM_FLAG 4 +#define IMM_FLAG (1 << 0) +#define BIMM_FLAG (1 << 1) /* MSR_EE (1 << 8) */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index f8e2ca12a9..06f4322e09 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -166,7 +166,7 @@ void mb_cpu_do_interrupt(CPUState *cs) /* Reexecute the branch. */ env->regs[17] -=3D 4; /* was the branch immprefixed?. */ - if (env->bimm) { + if (env->iflags & BIMM_FLAG) { env->regs[17] -=3D 4; log_cpu_state_mask(CPU_LOG_INT, cs, 0); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 42d6d2a593..7fd1efd3fb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1337,13 +1337,11 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i3= 2 pc_true, TCGv_i32 pc_false) =20 static void dec_setup_dslot(DisasContext *dc) { - TCGv_i32 tmp =3D tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_F= LAG)); - - dc->delayed_branch =3D 2; - dc->tb_flags |=3D D_FLAG; - - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); - tcg_temp_free_i32(tmp); + dc->delayed_branch =3D 2; + dc->tb_flags |=3D D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags |=3D BIMM_FLAG; + } } =20 static void dec_bcc(DisasContext *dc) --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391730; cv=none; d=zohomail.com; s=zohoarc; b=GaGrRgSebtXVL1YQI38cBoUyuP3U4vMxubI8oNKlEfd62GyyM25kuTTmhDfsi/37ie1gnv9X64C1rAjnaEx+wLFAach+0gUsfNIWJ2GVabozd28f3xUIX79CNGVTpiBNR4fF/DzeUNbGjj1Igotw5c6/ZHIyO+NnUcseDtKfbMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391730; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RvFJSD7Zh4rSxdM1y2eF+nLQTn/KQL07U6ICYBiMb68=; b=KH1+Tzs32VRSX+S/3X2lKYSeQeauUIrH8MIxKLcWyEvWS1ZO6JXgl8CkMDG/WvVBfFVs/QMIqfNkeRx8k4PuqMKBw336fAEiejTPb1RQvK9V+w1cfGQO6ItDnF5wDBRD6Ei49kxvb8paMq5g7rj2ajE4dtTzwo4eTdA2xL9tTTE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391730283497.3010453304854; Tue, 25 Aug 2020 14:42:10 -0700 (PDT) Received: from localhost ([::1]:44066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAghl-00029C-1x for importer@patchew.org; Tue, 25 Aug 2020 17:42:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg42-00008S-T0 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:08 -0400 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:38471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg40-000205-45 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:06 -0400 Received: by mail-pj1-x1041.google.com with SMTP id ls14so122955pjb.3 for ; Tue, 25 Aug 2020 14:01:03 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RvFJSD7Zh4rSxdM1y2eF+nLQTn/KQL07U6ICYBiMb68=; b=kFRER9DxURxEDgZHd7YIls5QJIoQuf5VY76p0sYQWvgvG30AC/w4r0qgKGCCbRshOq 3xPCwnwPVH4THKI+nuHNpCdaTKZEzpBKONg/7utJb0r5ahOUj/evI/P9cUeMyPu3kRWo eQFqoMkIUXNutGmyH41oqKTb9ykpl8UjBhm4HxhNr1MYRmIqTdDSmu6++daJyzMJLsPN tnhydTFtk0xrs+op55sLV4gOZRdFLRUoAiwJ1aHZANTBNNQ96RdfUghAFOkcs1rnzDMK K1HoXStMGS8AUKwglwal5ZvfJTdDGtdykgzIWsQqjuRZX2iNNiKVS/ZTuYDIy38zeMmO DRfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RvFJSD7Zh4rSxdM1y2eF+nLQTn/KQL07U6ICYBiMb68=; b=slKzL3mSMsKta4qPRdkmgv6m4+1+3bLx7UyYoxDxsYKO0yCL0ye+r8vLrUlESldOMF SSc7qwJ7IYcrmUkTjc0qKJvBqHr7P1W86sfmmhsp7Yf6Qvp2dSfBTnnuagk94ijgWeWw QkmvvfsXeTAcPwb75j82wB/I+1HAzwCQIn8tUmRVwQpirHvFqDECpPjuzT1Wy/L74X9h gkacLmHsFvi7Yol910V6K4y5i5zhFFcJqX9NuiD3jzvDEAFgGQneKiMmQJAHR0K7PAAE lvyYHWr1EpJ1NHM3pE5T77tHQdWvdaLlzzi6KuBZY2OwaR7DeMBjxsjl5cPtKEfTrVUX 79Tg== X-Gm-Message-State: AOAM530YRBtP8q+fzffvz74FrZudptUJLmcAiMvSC4C77SnZtJwYT1uq sY2WY34aqUz1EC7vayzbREdefcfXel2vjA== X-Google-Smtp-Source: ABdhPJwxSah2AsMJMCzFF8mNxcJsHCH0YcWffJr1X7m3hdpNOZSdfSIeCp4DAwisxNRQDmwM3hYkLA== X-Received: by 2002:a17:90a:fc98:: with SMTP id ci24mr3152772pjb.101.1598389262443; Tue, 25 Aug 2020 14:01:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 56/77] target/microblaze: Store "current" iflags in insn_start Date: Tue, 25 Aug 2020 13:59:29 -0700 Message-Id: <20200825205950.730499-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 ++ target/microblaze/translate.c | 24 +++++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a5df1fa28f..83fadd36a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + struct CPUMBState { uint32_t btaken; uint32_t btarget; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7fd1efd3fb..930b8a9600 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,6 +58,9 @@ typedef struct DisasContext { DisasContextBase base; MicroBlazeCPU *cpu; =20 + /* TCG op of the current insn_start. */ + TCGOp *insn_start; + TCGv_i32 r0; bool r0_set; =20 @@ -71,7 +74,7 @@ typedef struct DisasContext { =20 unsigned int cpustate_changed; unsigned int delayed_branch; - unsigned int tb_flags, synced_flags; /* tb dependent flags. */ + unsigned int tb_flags; unsigned int clear_imm; int mem_index; =20 @@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" =20 -static inline void t_sync_flags(DisasContext *dc) +static void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ - if (dc->tb_flags !=3D dc->synced_flags) { - tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); - dc->synced_flags =3D dc->tb_flags; + if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) { + tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK); } } =20 @@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr= , MemOp mop, } } =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 /* @@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); @@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, } } =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); @@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) TCGLabel *swx_fail =3D gen_new_label(); TCGv_i32 tval; =20 - t_sync_flags(dc); sync_jmpstate(dc); =20 /* swx does not throw unaligned access errors, so force alignment */ @@ -1647,7 +1645,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) int bound; =20 dc->cpu =3D cpu; - dc->synced_flags =3D dc->tb_flags =3D dc->base.tb->flags; + dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; @@ -1667,7 +1665,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CP= UState *cs) =20 static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) { - tcg_gen_insn_start(dcb->pc_next); + DisasContext *dc =3D container_of(dcb, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + dc->insn_start =3D tcg_last_op(); } =20 static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, @@ -1909,4 +1910,5 @@ void restore_state_to_opc(CPUMBState *env, Translatio= nBlock *tb, target_ulong *data) { env->pc =3D data[0]; + env->iflags =3D data[1]; } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391150; cv=none; d=zohomail.com; s=zohoarc; b=ImV/i8NQ4JkucvZ3rczZTPWBMHFI7jF/zt+MDY5Ke9K6aSnXMdwfvF1iHOkxfed5P6sNLdpbG7YwuNucDus1SNnOFfhzXbNMPcx+PiNVc7peqrhU1VqPDW/k+fpleSEvfp0Kkg56IBJv5Ca8ssyydsQMTi6ZnaNltxxhsYpAcM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391150; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p+iYZfUiWvOiZ4jhf/t12sD37PNbPvTJo79LCNu2vXI=; b=h0TstLm7dgZ9/wb5tn2m9FwhvUUkm5v7bQBms0fyQNEN5HkyOlQg9Ug/V9J45nDLqVIJNTFhJ2xa7SAxFM2uKDcPi9kSN4TvuYx789mki7ITOVPzEULtoSsDIop4ewVXZU8ZVgtbjM457rSmze+jYTCsXNsL31AVvpuUf1Iun5Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159839115029515.644747641689605; Tue, 25 Aug 2020 14:32:30 -0700 (PDT) Received: from localhost ([::1]:60150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgYO-0002OR-TJ for importer@patchew.org; Tue, 25 Aug 2020 17:32:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg45-0000A1-CU for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:09 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:40604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg41-00020D-SW for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:08 -0400 Received: by mail-pf1-x42d.google.com with SMTP id k18so8291036pfp.7 for ; Tue, 25 Aug 2020 14:01:04 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p+iYZfUiWvOiZ4jhf/t12sD37PNbPvTJo79LCNu2vXI=; b=io4EfYM/haayGe07qpmymqfOoSYgk0enlR6YVoFxG47PQAnAZGSUqKwUkarcHjJ0xz dO4IE0QQ4xJ/m2l9h3wL+9M4dNy+Euj8JDSNHbhJUy+eIZnCMN+77NNI4fhVN7vX3N8v LA0UGte2w2mQLDxUUEo+p3Sq5wb3n3IiDJlcHt22rXbzeveHKOyIuOWKd+/dAk3GnGPP Bv5P/AU3hCFT0cL5yj8dnCiXKrI/mz4J150+3nC7moxCEXOTbeONqovkgAvfGFSsUqFk XC4o+wZbyXnWB4FNFB0mZDBPXiSho2ZVJInJO2mCol1VT57/7wuHIG9mGSDUsOQCeH7x xgOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p+iYZfUiWvOiZ4jhf/t12sD37PNbPvTJo79LCNu2vXI=; b=QZTqCDycaroVdbWWslXcCDtUYRDGnwK5bjRTvMFIlBG4AvB/Mwo2RUIWkGU8CMEvRO DWHrwNVdn40jrCXltPtyaInTjsUqp3zfJSdjiO52RxsijYyLGh2voKNWHOUdAdIcuBN/ zWtrMRYgfUm1Qy4iWkfUsdBioq2oSKtYgCD5unAgbZ3KPJjzMsQUN7U0N7TKI31TdqER bCogYog9JXiw0LrdCylraSmioODNHJrPMfwoAnAp718N2np7WYsTQLXtJP+XuSqJ4Er9 Mokf0EeG24oapCcYbZcALrPP1on3y7+FxM64WjAQrjzZFdncrsbkqaAjlhss9p24601q zZ9g== X-Gm-Message-State: AOAM530sgp6VhaRAHL9dxKX0SZpPAc4OxdruCZPPAkjQsLq+9EXq5a5i GcSPspYxS4j2stOEUFrUPOzEkEOUjP8p8Q== X-Google-Smtp-Source: ABdhPJxsTURja4q3SnaYjQxtZ7PtjHaZufXKF6WoA8mADnjEecKQsr15HGhU8K+y6mPxFwSbsrY8oQ== X-Received: by 2002:aa7:925a:: with SMTP id 26mr5753679pfp.6.1598389263561; Tue, 25 Aug 2020 14:01:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 57/77] tcg: Add tcg_get_insn_start_param Date: Tue, 25 Aug 2020 13:59:30 -0700 Message-Id: <20200825205950.730499-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" MicroBlaze will shortly need to update a parameter in place. Add an interface to read to match that for write. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d40c925d04..15da46131b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -777,11 +777,26 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) } #endif =20 +static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) +{ + return op->args[arg]; +} + static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { op->args[arg] =3D v; } =20 +static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) +{ +#if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS + return tcg_get_insn_param(op, arg); +#else + return tcg_get_insn_param(op, arg * 2) | + (tcg_get_insn_param(op, arg * 2 + 1) << 32); +#endif +} + static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulo= ng v) { #if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391294; cv=none; d=zohomail.com; s=zohoarc; b=Zmx+W7pKuX8CCBlez+FS5klxiueWbYEo3i/GXd4ontqPVT9GNAOoS8Ufx4cqOIaUvDnW4xhaSygFiPinIm5m9MBE7vJcHzCLNUnLUz86ZAgZ6rRZpigIg6hxbMhnWaRrf6/TfGsHBz2nqptNnnkScMJkoqnsT5Kh2tFNpuNBgv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391294; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DL6mixLq6S/ykZHeP+netlYcRnE/vfVwl7yqTg4dZh0=; b=HJnhMIaRJFvO9TACMLDKVN66E46QvqXnyMURxYjid/uK9nHYuGIw1ss/+P7thhXXEMq8c3VcNqtgyI6q2etxngmAYWN7rFoHJinq6HyYG8wMAyl3NrcpiyFcZgd4Ll2a/umZJgbReJno2fPc4S/9cPATkgos4HU6EGKE3567QQM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159839129496574.35215928722812; Tue, 25 Aug 2020 14:34:54 -0700 (PDT) Received: from localhost ([::1]:39958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgaj-0005jS-Ho for importer@patchew.org; Tue, 25 Aug 2020 17:34:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg49-0000Fg-VJ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:14 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:33073) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg47-000214-JQ for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:13 -0400 Received: by mail-pg1-x52a.google.com with SMTP id o13so7690779pgf.0 for ; Tue, 25 Aug 2020 14:01:11 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DL6mixLq6S/ykZHeP+netlYcRnE/vfVwl7yqTg4dZh0=; b=YBgK5IbW7mQG8LtoiCkzu0EprDeVvBX/7TAE0q0kqTpTIM9hMuVM5w9babE/N2jiTY vTF6N3uF4ryLXBMS1mmbx2rWdVBQDU0LyqmO7t7PJcCHxIA180GXdHyjiFUn4RiVlUO8 sqwiEa6e+qtBJpbdozEbgrh7+2WyoLG3Xm0Z+y2QGwOcECikqRtSGlnZwuc2fHX7GPms 93/DQHcHjYKRfFT7zQgQXOgKJ2meV3bQBzbqE25mr/zU1gUk5Kk8vMTlpMWyyR8of8ZF ixaBKM7VoYEwu+8J1IpbnGqDO84x/78S48i4ZUxJMIJWhdWTXLnVsOY2YZ+Rii6adrwb yCMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DL6mixLq6S/ykZHeP+netlYcRnE/vfVwl7yqTg4dZh0=; b=fpahUnlOE0+hVVGm6LNWBkrUMl2PbpL15V/U/Z4whrhLeMD6fALE3rBv43U+wNb9hB wcvoEZwKTT3EK0586j5xLCc0cqqHK9uNKD0RNl6XMdpR3Jbyn3uuNo6mCAyzcMgmic/n fvKViUSzcurgFPShlTQHVjllWdMl0eNTpiGFUTz35MKC/vnmlXo4A2ZqOwcqynNAg65P QY1psA05E5vZVvvSnqXj9bZGHVvGD0t1goPUu7PLw5L2MESqYM+UFQVxZZtOToBKWYWO YtqbDBZcK48QidKijHkOSzyOgcioByJnFhYvzIkNdjtkaScrepZ5p7kROeMANeat5Wis A5/Q== X-Gm-Message-State: AOAM532FwcrA3hNhexfIdBYlfLUoE+22QMeZUHSCtk+dU6lsmzi9vAfv GKrPLr4hhpHXENltrI33CbfXAa3YR4013Q== X-Google-Smtp-Source: ABdhPJwVpoEQv2oIuHHXUEwU2Df4vWhBt3MNfhaFAmk6+m/0O0GzhbSyLwLWsjjEJXt815+gaAwu0A== X-Received: by 2002:a63:6f82:: with SMTP id k124mr7890307pgc.357.1598389268991; Tue, 25 Aug 2020 14:01:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 58/77] target/microblaze: Use cc->do_unaligned_access Date: Tue, 25 Aug 2020 13:59:31 -0700 Message-Id: <20200825205950.730499-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 10 ++++- target/microblaze/helper.h | 1 - target/microblaze/cpu.c | 1 + target/microblaze/helper.c | 28 ++++++++++++++ target/microblaze/op_helper.c | 21 ---------- target/microblaze/translate.c | 72 +++++++++++++---------------------- 6 files changed, 64 insertions(+), 69 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 83fadd36a5..63b8d93d41 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -79,10 +79,13 @@ typedef struct CPUMBState CPUMBState; =20 /* Exception State Register (ESR) Fields */ #define ESR_DIZ (1<<11) /* Zone Protection */ +#define ESR_W (1<<11) /* Unaligned word access */ #define ESR_S (1<<10) /* Store instruction */ =20 #define ESR_ESS_FSL_OFFSET 5 =20 +#define ESR_ESS_MASK (0x7f << 5) + #define ESR_EC_FSL 0 #define ESR_EC_UNALIGNED_DATA 1 #define ESR_EC_ILLEGAL_OP 2 @@ -256,9 +259,11 @@ struct CPUMBState { /* Internal flags. */ #define IMM_FLAG (1 << 0) #define BIMM_FLAG (1 << 1) -/* MSR_EE (1 << 8) */ +#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ +/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flag= s */ /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ +/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp= */ #define DRTI_FLAG (1 << 16) #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) @@ -330,6 +335,9 @@ struct MicroBlazeCPU { =20 void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index a473c1867b..3980fba797 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_3(mmu_read, i32, env, i32, i32) DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) #endif =20 -DEF_HELPER_5(memalign, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) =20 DEF_HELPER_2(get, i32, i32, i32) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1eabf5cc3f..67017ecc33 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,6 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; cc->do_interrupt =3D mb_cpu_do_interrupt; + cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 06f4322e09..0e3be251a7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -296,3 +296,31 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) } return false; } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + uint32_t esr, iflags; + + /* Recover the pc and iflags from the corresponding insn_start. */ + cpu_restore_state(cs, retaddr, true); + iflags =3D cpu->env.iflags; + + qemu_log_mask(CPU_LOG_INT, + "Unaligned access addr=3D" TARGET_FMT_lx + " pc=3D%x iflags=3D%x\n", addr, cpu->env.pc, iflags); + + esr =3D ESR_EC_UNALIGNED_DATA; + if (likely(iflags & ESR_ESS_FLAG)) { + esr |=3D iflags & ESR_ESS_MASK; + } else { + qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"= ); + } + + cpu->env.ear =3D addr; + cpu->env.esr =3D esr; + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit(cs); +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index a99c467364..4a07d0ce3c 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -365,27 +365,6 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b) return 0; } =20 -void helper_memalign(CPUMBState *env, target_ulong addr, - uint32_t dr, uint32_t wr, - uint32_t mask) -{ - if (addr & mask) { - qemu_log_mask(CPU_LOG_INT, - "unaligned access addr=3D" TARGET_FMT_lx - " mask=3D%x, wr=3D%d dr=3Dr%d\n", - addr, mask, wr, dr); - env->ear =3D addr; - env->esr =3D ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) <<= 5; - if (mask =3D=3D 3) { - env->esr |=3D 1 << 11; - } - if (!(env->msr & MSR_EE)) { - return; - } - helper_raise_exception(env, EXCP_HW_EXCP); - } -} - void helper_stackprot(CPUMBState *env, target_ulong addr) { if (addr < env->slr || addr > env->shr) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 930b8a9600..6e70873333 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -751,10 +751,22 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, in= t ra, int rb) return ret; } =20 +static void record_unaligned_ess(DisasContext *dc, int rd, + MemOp size, bool store) +{ + uint32_t iflags =3D tcg_get_insn_start_param(dc->insn_start, 1); + + iflags |=3D ESR_ESS_FLAG; + iflags |=3D rd << 5; + iflags |=3D store * ESR_S; + iflags |=3D (size =3D=3D MO_32) * ESR_W; + + tcg_set_insn_start_param(dc->insn_start, 1, iflags); +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { - TCGv_i32 v; MemOp size =3D mop & MO_SIZE; =20 /* @@ -774,34 +786,15 @@ static bool do_load(DisasContext *dc, int rd, TCGv ad= dr, MemOp mop, =20 sync_jmpstate(dc); =20 - /* - * Microblaze gives MMU faults priority over faults due to - * unaligned addresses. That's why we speculatively do the load - * into v. If the load succeeds, we verify alignment of the - * address and if that succeeds we write into the destination reg. - */ - v =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t0 =3D tcg_const_i32(0); - TCGv_i32 treg =3D tcg_const_i32(rd); - TCGv_i32 tsize =3D tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_helper_memalign(cpu_env, addr, treg, t0, tsize); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, false); + mop |=3D MO_ALIGN; } =20 - if (rd) { - tcg_gen_mov_i32(cpu_R[rd], v); - } + tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); =20 - tcg_temp_free_i32(v); tcg_temp_free(addr); return true; } @@ -931,28 +924,15 @@ static bool do_store(DisasContext *dc, int rd, TCGv a= ddr, MemOp mop, =20 sync_jmpstate(dc); =20 - tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); - - /* TODO: Convert to CPUClass::do_unaligned_access. */ - if (dc->cpu->cfg.unaligned_exceptions && size > MO_8) { - TCGv_i32 t1 =3D tcg_const_i32(1); - TCGv_i32 treg =3D tcg_const_i32(rd); - TCGv_i32 tsize =3D tcg_const_i32((1 << size) - 1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - /* FIXME: if the alignment is wrong, we should restore the value - * in memory. One possible way to achieve this is to probe - * the MMU prior to the memaccess, thay way we could put - * the alignment checks in between the probe and the mem - * access. - */ - gen_helper_memalign(cpu_env, addr, treg, t1, tsize); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(treg); - tcg_temp_free_i32(tsize); + if (size > MO_8 && + (dc->tb_flags & MSR_EE) && + dc->cpu->cfg.unaligned_exceptions) { + record_unaligned_ess(dc, rd, size, true); + mop |=3D MO_ALIGN; } =20 + tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); + tcg_temp_free(addr); return true; } --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391381; cv=none; d=zohomail.com; s=zohoarc; b=kF3tElJXREUykm3hN1s72eh7JSJM9BDlz2DllwkxV+pUQaGaLwe66sUgw9RuP4WKhTOYSVzEjBAh9LCJPfDUNYpm2pS1e8li1HiAYjgHh9ljtCNxVejLBHY0SOIgZcHdJM5Snt7Gvaq0M7104eSOP9BTbT5uSwdN1FxsphV+gDI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391381; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0IyoDEFe3ZWYDga+MAV6Bg/xEkFwuDqD20ZUdnvyl1Q=; b=Rg6eYzMdmiN9UlsSYT8gHcc8betFM11qLKwhT0tHm3waBInjWgKe9+CywSWoIMbjQwuXwQZ2YGLR6mpn7hJlWmoGbxh0UIrs4BqiBaUIxsjFtDWp3e6NGJ3i10+6zgUh0HDCdhcIuj3wkwRqgM/N83hAdPe/wu/mbcH1O8EDdM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391381453906.002598303493; Tue, 25 Aug 2020 14:36:21 -0700 (PDT) Received: from localhost ([::1]:48060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgc8-0000fX-5c for importer@patchew.org; Tue, 25 Aug 2020 17:36:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4A-0000HH-LK for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:14 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:46074) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg48-000219-KK for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:14 -0400 Received: by mail-pf1-x441.google.com with SMTP id k15so1823277pfc.12 for ; Tue, 25 Aug 2020 14:01:12 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0IyoDEFe3ZWYDga+MAV6Bg/xEkFwuDqD20ZUdnvyl1Q=; b=i1mG4tBBmW5Rvw7Ff45f/KekuzbCVOHea7q3wNIXaWEXghFSU/Qf3QCeGeJSjEq9Ds wTz63U2RYBYkjGSd/Jb3QHJMz+GZEw4Axpb1IvYmO9hN6+7HYvbJI9YsNMF70B6VWZaC nXixW9pxyULrAfoyMXWgj8yQn0CiMO7+ttqvgx+CLthK+fwh6XvUyXoPXDmXE9vCi+Zz O0PU/gIJm2+wPIv5O94bMRGsVJmSBDSDH6U68xlayedQVz48OmKZRDH9gJMaFJpB/xBs KXFhKw8yFuZZp3VTzeDu1K15/C96t1eF+fjHEQ1wx+T2hGdGxt+I7/Mz652ZsTJWA58s so5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0IyoDEFe3ZWYDga+MAV6Bg/xEkFwuDqD20ZUdnvyl1Q=; b=irimzTcjKflac/Kgz/W9GbZR/CtEWZbZOU/aYwKgSk2zRXMCFvW8sOS+QExH/4pn10 kse2RlTrXFonyLeYnFcEpYgMjA9o9xG+ZdiY4HWLJ/yisYj/qClnNEU0mivPmGg6SY++ 0hcCL3N2CHqvwCFiDIuwwFntVYBG0zppidNYcpU2MJt4wAJ7dumrX2mv5xP+ZDzDxaUC 9kGRMuSqB4ARvcMb7171alc798YpaHLnPBOPxT0IgPpcKS+znfBK3pZtuFpwfWfyGQKl AN8PH60eNRjvmRXA0agE1NfzRmnjZJtkeHH5DOZJeF5QnWeh4idVKG8u/P9aBVwAjIuK R/kA== X-Gm-Message-State: AOAM53015nXxQYoyLJQ9jDJjBTg4R+phipWln4x0xAXYS9WuuI7m9QrP 1S3hfSxAIIPOi6J4ABsDu8IteITGcg9s4w== X-Google-Smtp-Source: ABdhPJxodVQMv5bVGIs0sw8Q7Jl5NqeGZdmiMLbpNOTsDZ2nD7oEFwfPmMVIMjvWNPF/uPZ7pIzU2w== X-Received: by 2002:a05:6a00:14d0:: with SMTP id w16mr9330728pfu.39.1598389270962; Tue, 25 Aug 2020 14:01:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 59/77] target/microblaze: Replace clear_imm with tb_flags_to_set Date: Tue, 25 Aug 2020 13:59:32 -0700 Message-Id: <20200825205950.730499-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This more general update variable will be able to handle delay slots as well. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6e70873333..18009103c7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -75,7 +75,7 @@ typedef struct DisasContext { unsigned int cpustate_changed; unsigned int delayed_branch; unsigned int tb_flags; - unsigned int clear_imm; + unsigned int tb_flags_to_set; int mem_index; =20 #define JMP_NOJMP 0 @@ -535,8 +535,7 @@ static bool trans_imm(DisasContext *dc, arg_imm *arg) { dc->ext_imm =3D arg->imm << 16; tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags |=3D IMM_FLAG; - dc->clear_imm =3D 0; + dc->tb_flags_to_set =3D IMM_FLAG; return true; } =20 @@ -1680,7 +1679,8 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) (uint32_t)dc->base.pc_next); } =20 - dc->clear_imm =3D 1; + dc->tb_flags_to_set =3D 0; + ir =3D cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { old_decode(dc, ir); @@ -1692,10 +1692,13 @@ static void mb_tr_translate_insn(DisasContextBase *= dcb, CPUState *cs) dc->r0_set =3D false; } =20 - if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags &=3D ~IMM_FLAG; + /* Discard the imm global when its contents cannot be used. */ + if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) { tcg_gen_discard_i32(cpu_imm); } + + dc->tb_flags &=3D ~IMM_FLAG; + dc->tb_flags |=3D dc->tb_flags_to_set; dc->base.pc_next +=3D 4; =20 if (dc->delayed_branch && --dc->delayed_branch =3D=3D 0) { --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391491; cv=none; d=zohomail.com; s=zohoarc; b=F3sxUVkpugU32EZxstyP7PuMhRcrJsmWpOn+Ha8DASZI+FMl14OX6OBe4q9Ira6UHlGaXg4nDaxWhmlX/GrxEkrZSQb9KpH+25TlucVg1nDNw8vgnnJfjgO99GB03BHVSBSTZInLy/FOEHKJGRkYOWT6TEMRjv7sge3fgE0rp7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391491; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ifoPB2xrefiphamrfMAWhJL0YX7DJDQgoCM7PfPYN9w=; b=Q6I9sMncr+a1jHLYf3XMbgTZrL/wfWNy/MvHVYaGrMmuFrx5Vis7qSDA0huzH9HJ/siK226gQkWRZkomhNBs73s5yCCYd4hVyR8sag4lxxKyc8z/W68IQlUTznt0C3Cw3Qe/4dLYLj5rXja4cXuZiH3pmI7/LYQC2+b1tNexBzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159839149115436.082204835249854; Tue, 25 Aug 2020 14:38:11 -0700 (PDT) Received: from localhost ([::1]:56556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgdt-00046H-Rl for importer@patchew.org; Tue, 25 Aug 2020 17:38:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4B-0000Ju-Ky for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:15 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:35622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg49-00021D-N3 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:15 -0400 Received: by mail-pj1-x1042.google.com with SMTP id g6so130612pjl.0 for ; Tue, 25 Aug 2020 14:01:13 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ifoPB2xrefiphamrfMAWhJL0YX7DJDQgoCM7PfPYN9w=; b=L8+p6R/NrJWjvoevG8i0efGK/CaF+nLXFjUrd+5bGITCdM8i2ZMWHVfrMHQeHyyYrA GqRp8pcBH0lawSum/RiwvgwFLZjfjuf5a3UlovS+R8bpFiUazFH2erecDWmaxA3zuVzp cn16Q/dnA4IEaF4h4CIyCGf/udMkD/eWGwgYn66Ok5JtetdGCsAzCQLMzawHkQLquZ83 aae+zYDIqdcZfs3rFGvz0M3MfSJt31jdlXu2BT5hpPt5+W6sOGfSfTeEDdEVAVY7veD7 kbkFUjNTnbRVmuZFhpT5UVGH8gb5f2lQbwqwK3xGaz260nMk+hKrQXGjEwRzHL7gnTeM gZgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ifoPB2xrefiphamrfMAWhJL0YX7DJDQgoCM7PfPYN9w=; b=S424+0vNCVpN3F++RLaOdLpe9gZEtAPCPJZomGHAZVX4xLNj5R/twmuc0QZAjqON4T K8/vnAbvGz9J1lWxMDb7KfFN9OrhX7KzWdxAN5ByrJGQjwsCOQGjvCFX5vtC6jOboSLT IyaSiYd3rQd9KNxLt1PfAfs4bSfMWr5pr55guxbM0OxpeBFJoqTurFyxsHU+IWR6jr7t JGasIZwmB+GcB0PBjSIY8AypCbuxRPwyIRcGuGloce3oqUMiwt0CFioSQaVqMBlpkP4V f35BxAojFe0Hgeva6UwNO71gQoLyXkwnHRvoIxXPmQuMhiLaWgrp8bOYvR9DuRmFGOvM cfXg== X-Gm-Message-State: AOAM533jtoL/yEMmC+VbvtnTLhqdCw7h1b9ccClvRp0ioSCl0KIQRIYX D8hu4HiNVTQjA759Sm1BtTfk4/tV4ILL/Q== X-Google-Smtp-Source: ABdhPJxcRwetxRYTk7PAppPF4pkrJZvL1MQI+ljU4lI6tdyG5ny1/tJiuk0SG2VK5JmniLU1RfaKJQ== X-Received: by 2002:a17:90b:2394:: with SMTP id mr20mr47671pjb.56.1598389272047; Tue, 25 Aug 2020 14:01:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 60/77] target/microblaze: Replace delayed_branch with tb_flags_to_set Date: Tue, 25 Aug 2020 13:59:33 -0700 Message-Id: <20200825205950.730499-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The multi-stage counter can be replaced by clearing D_FLAG, the or'ing in tb_flags_to_set. The jump then happens when D_FLAG is finally cleared. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 18009103c7..3ba2dc1800 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -73,7 +73,6 @@ typedef struct DisasContext { uint16_t imm; =20 unsigned int cpustate_changed; - unsigned int delayed_branch; unsigned int tb_flags; unsigned int tb_flags_to_set; int mem_index; @@ -1314,10 +1313,9 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32= pc_true, TCGv_i32 pc_false) =20 static void dec_setup_dslot(DisasContext *dc) { - dc->delayed_branch =3D 2; - dc->tb_flags |=3D D_FLAG; + dc->tb_flags_to_set |=3D D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags |=3D BIMM_FLAG; + dc->tb_flags_to_set |=3D BIMM_FLAG; } } =20 @@ -1329,7 +1327,6 @@ static void dec_bcc(DisasContext *dc) cc =3D EXTRACT_FIELD(dc->ir, 21, 23); dslot =3D dc->ir & (1 << 25); =20 - dc->delayed_branch =3D 1; if (dslot) { dec_setup_dslot(dc); } @@ -1405,7 +1402,6 @@ static void dec_br(DisasContext *dc) } } =20 - dc->delayed_branch =3D 1; if (dslot) { dec_setup_dslot(dc); } @@ -1625,8 +1621,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) =20 dc->cpu =3D cpu; dc->tb_flags =3D dc->base.tb->flags; - dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); - dc->jmp =3D dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; + dc->jmp =3D dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; dc->ext_imm =3D dc->base.tb->cs_base; @@ -1697,11 +1692,11 @@ static void mb_tr_translate_insn(DisasContextBase *= dcb, CPUState *cs) tcg_gen_discard_i32(cpu_imm); } =20 - dc->tb_flags &=3D ~IMM_FLAG; + dc->tb_flags &=3D ~(IMM_FLAG | BIMM_FLAG | D_FLAG); dc->tb_flags |=3D dc->tb_flags_to_set; dc->base.pc_next +=3D 4; =20 - if (dc->delayed_branch && --dc->delayed_branch =3D=3D 0) { + if (dc->jmp !=3D JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); } @@ -1711,8 +1706,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } - /* Clear the delay slot flag. */ - dc->tb_flags &=3D ~D_FLAG; dc->base.is_jmp =3D DISAS_JUMP; } =20 --=20 2.25.1 From nobody Sat May 18 21:00:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391812; cv=none; d=zohomail.com; s=zohoarc; b=gm+J8PSFI7Bu7OQxm2vVwKAIer/sjLobomcOszirD8S6fDj6Ghry/hIacNKF2PU5HHLn770nTN9j5NRSsjRMOYGWS8fKeF6SzIc2jFWIdnRPXbHzV3W6Fl3pCohdRFXnUHaSX6X0s6AaOuUF3p5tpAwOTWhvcX3FprogJE8yzeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391812; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0+lbMujB7ENQF6DPdS7wnVUjhoKJE7Rkmv+oxgd9wrg=; b=H4lK7+9YO/KMcody7HBPBqZ3dhLe0VgbhFpzqnD+9zFu8VfBOMrTz5KBvSkVXcwRou93RPpDmVbCbjSOYFXAHwXFzE+4m4HjzzdwZeD8ojkIDO6kJws3iBRg0F2eO0E2bIlDOyoawDOTJ6rChU1IBnCoqn6JwETvfYGmaQcYsds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391812840346.67816803498295; Tue, 25 Aug 2020 14:43:32 -0700 (PDT) Received: from localhost ([::1]:48688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgj5-00044o-Ih for importer@patchew.org; Tue, 25 Aug 2020 17:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4C-0000Mm-Su for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:16 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4A-00021U-Tl for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:16 -0400 Received: by mail-pg1-x542.google.com with SMTP id h12so7675219pgm.7 for ; Tue, 25 Aug 2020 14:01:14 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0+lbMujB7ENQF6DPdS7wnVUjhoKJE7Rkmv+oxgd9wrg=; b=WCymE3jWbHXk76hlDjCJUVQXgckSWgcpPrdABXMw7zDyqOP7b2H5O9zMWMH2ou5sxd 9qYxMOH/q2VsyQywqGSPGugNgKB7981voHZxR16L26suMOfJzw72U3ZyWPGVM4OBLOjp ZkwYIPszghuKLsSJzmLLfWotazsxHN+wR8jnQ+csnSXcDqf2DPufkW4ROug4Z9QdWwm1 evkLhMrp50+O44XPGzR9UJdmC7DSOlxnuBU2o7brm/CzEVjrJyaaziHXaijW7o1LP+OJ WzWJQmq1pNzyqPEO3lV3nuCwPTvfN+le52Lx2ejtn8f104ozxKdqSQQynlMzCDVN//lL iXKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0+lbMujB7ENQF6DPdS7wnVUjhoKJE7Rkmv+oxgd9wrg=; b=reNXmVRGErl1jSRITy8Yi8hjQSxMiAPXMwH6rBdVfB1ki9THprd94WApaTgQlPXUOk QhTX3UpveAN+8tB15GvbrQgjUmZ8CrdFgVSRTvnEmbqEsUxfcgeIVJpAoOF4Pkcf78r0 wEdoF5MkXKDIdPCpemCU3atpNDoNgnOgR/qJUnWEcAgiiePmB6p35VgS33H2tSvEVhTN ZyqPDyqPmKIvidL1/04qzt8sBMTujZkzWODwsOIDqKCYs4bbjm9WhKs6M0BgNyPPo3Pl WJTtLFBCzt229V0vyEdvd/u+TXQ6eV87kkq6F72aWmkSFMVyPRwZnIFhCclKMbGi2HXz JPzw== X-Gm-Message-State: AOAM531UsInpbCEMXzEK982xLqexrXSzVOkBWgBxjYwnjhvLRI42Nyti bp5ItMwkmAAn4Mvdc1fAtr1ONdmETRLxeQ== X-Google-Smtp-Source: ABdhPJwk6KWRlM+HN1HWXL2lk1QWBzxeH+3ZnFn6qnra1WrGnQIM8nNt5L4kMp+W5zxDGoSQk0kbZQ== X-Received: by 2002:aa7:924b:: with SMTP id 11mr9274257pfp.185.1598389273161; Tue, 25 Aug 2020 14:01:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 61/77] target/microblaze: Tidy mb_cpu_dump_state Date: Tue, 25 Aug 2020 13:59:34 -0700 Message-Id: <20200825205950.730499-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Using lookup_symbol is quite slow; remove that. Decode the various bits of iflags; only show imm, btaken, btarget when they are relevant to iflags. Improve formatting. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 67 +++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3ba2dc1800..4675326083 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1810,41 +1810,56 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; + uint32_t iflags; int i; =20 - if (!env) { - return; - } - - qemu_fprintf(f, "IN: PC=3D%x %s\n", - env->pc, lookup_symbol(env->pc)); - qemu_fprintf(f, "rmsr=3D%x resr=3D%x rear=3D%" PRIx64 " " - "imm=3D%x iflags=3D%x fsr=3D%x rbtr=3D%x\n", - env->msr, env->esr, env->ear, - env->imm, env->iflags, env->fsr, env->btr); - qemu_fprintf(f, "btaken=3D%d btarget=3D%x mode=3D%s(saved=3D%s) eip=3D= %d ie=3D%d\n", - env->btaken, env->btarget, + qemu_fprintf(f, "pc=3D0x%08x msr=3D0x%05x mode=3D%s(saved=3D%s) eip=3D= %d ie=3D%d\n", + env->pc, env->msr, (env->msr & MSR_UM) ? "user" : "kernel", (env->msr & MSR_UMS) ? "user" : "kernel", (bool)(env->msr & MSR_EIP), (bool)(env->msr & MSR_IE)); - for (i =3D 0; i < 12; i++) { - qemu_fprintf(f, "rpvr%2.2d=3D%8.8x ", i, env->pvr.regs[i]); - if ((i + 1) % 4 =3D=3D 0) { - qemu_fprintf(f, "\n"); - } + + iflags =3D env->iflags; + qemu_fprintf(f, "iflags: 0x%08x", iflags); + if (iflags & IMM_FLAG) { + qemu_fprintf(f, " IMM(0x%08x)", env->imm); + } + if (iflags & BIMM_FLAG) { + qemu_fprintf(f, " BIMM"); + } + if (iflags & D_FLAG) { + qemu_fprintf(f, " D(btaken=3D%d btarget=3D0x%08x)", + env->btaken, env->btarget); + } + if (iflags & DRTI_FLAG) { + qemu_fprintf(f, " DRTI"); + } + if (iflags & DRTE_FLAG) { + qemu_fprintf(f, " DRTE"); + } + if (iflags & DRTB_FLAG) { + qemu_fprintf(f, " DRTB"); + } + if (iflags & ESR_ESS_FLAG) { + qemu_fprintf(f, " ESR_ESS(0x%04x)", iflags & ESR_ESS_MASK); + } + + qemu_fprintf(f, "\nesr=3D0x%04x fsr=3D0x%02x btr=3D0x%08x edr=3D0x%x\n" + "ear=3D0x%016" PRIx64 " slr=3D0x%x shr=3D0x%x\n", + env->esr, env->fsr, env->btr, env->edr, + env->ear, env->slr, env->shr); + + for (i =3D 0; i < 12; i++) { + qemu_fprintf(f, "rpvr%-2d=3D%08x%c", + i, env->pvr.regs[i], i % 4 =3D=3D 3 ? '\n' : ' '); } =20 - /* Registers that aren't modeled are reported as 0 */ - qemu_fprintf(f, "redr=3D%x rpid=3D0 rzpr=3D0 rtlbx=3D0 rtlbsx=3D0 " - "rtlblo=3D0 rtlbhi=3D0\n", env->edr); - qemu_fprintf(f, "slr=3D%x shr=3D%x\n", env->slr, env->shr); for (i =3D 0; i < 32; i++) { - qemu_fprintf(f, "r%2.2d=3D%8.8x ", i, env->regs[i]); - if ((i + 1) % 4 =3D=3D 0) - qemu_fprintf(f, "\n"); - } - qemu_fprintf(f, "\n\n"); + qemu_fprintf(f, "r%2.2d=3D%08x%c", + i, env->regs[i], i % 4 =3D=3D 3 ? '\n' : ' '); + } + qemu_fprintf(f, "\n"); } =20 void mb_tcg_init(void) --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390743; cv=none; d=zohomail.com; s=zohoarc; b=RKKVWVHh3Wo1ksm7wsNwtQ+gHJlUel5QfHzAaTcDrKsUeL8TVvZumiUpS9iHc0eDk+x40zxT5W+6uYg62ZVOctMFAHAhxBcaSdBXPJOZiPI8MYWiBu/aRkJpRnVyTLwrVJrZRS3Z3p9KOELMSNuG4kqdlb+yirbogBPOaLNQwIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390743; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ulBZsejW2MG0+XvkBxJ405c+w3o2ybsU7Ko1+l3VylQ=; b=EJJxELJcXkcuf3RlMP+Y+HCk1GuDW966xsyHUqyz26SwM/Bi1339AehFklM4U8Ax3ZoKvP84e3eWWPT7LIfSNXTUQsERYDY9y/HB6Qo73IPXA9seoMreUaxsVUirwcNdH7f9xZBq0pq2TK3ZgrRb2v9Ol3gtYXn25fvaSnAaZkY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390743152257.3346950482511; Tue, 25 Aug 2020 14:25:43 -0700 (PDT) Received: from localhost ([::1]:32910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgRp-00080X-SJ for importer@patchew.org; Tue, 25 Aug 2020 17:25:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4E-0000Q1-C1 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:18 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:55654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4C-00021h-3g for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:17 -0400 Received: by mail-pj1-x1044.google.com with SMTP id 2so118661pjx.5 for ; Tue, 25 Aug 2020 14:01:15 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ulBZsejW2MG0+XvkBxJ405c+w3o2ybsU7Ko1+l3VylQ=; b=ouP3GNpws10kfQdVvOrwNLcPphAdXPOKqL+5zPovlIaEbwdO2MNHWHG7o+NkDz9k55 gmKxf2I23v/uU2kYDf/Y9+IgkRsTkX6tTqZ2dktEKRP8al2bej0CeNjdkXLDkSS8G4CL goRbB00kxg7VHSbQiYJeIxOyeaeC9+Co57nZ/CgKda4kgYxJ48yrouJxbWpLV9YubiYL fKvcaLpDh8yNF9pAk5lMVMwQc98DDsdQJveb7N8l5rj6V1ef4ypFnGZApk0grxdB2e+B uK+BHu9VJyopinTtt19X+rMqk49Bubjc4ZFq3VZ0h6AmKHRxPyIE3jBG5DxPejh7/2vg cSZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ulBZsejW2MG0+XvkBxJ405c+w3o2ybsU7Ko1+l3VylQ=; b=sT93v3fCMieAtp5WhEmPZFgEAXzHUtRCfZDlCmFpnPOHL/Cv1P4Hd4Kl9OCT9VZsK8 9SwqpeadzVy3ZMZem136z3Fizkt3WyW+D6v4tk4oUlK14eRqX12FxdqwIx54x1Z2JqD8 snV86/6ikvsL2y1x6qwbaaDMzO6xxKMdy6uShNAOcz8BX5UENMTv2Lpg+ap64k90FBvv TgHnCLQ/DQw5HVg3EKD6Vl3YO/IDHwUtWQj+k44mGEsH41hPhgDJorslz5r4tX4eVIKD Z5VV/Mi8/U5AvNXGtUreUnNzBs3CCB4/AVU1NpbzRYP1gL7yzfQ0uyRu6bdOlz0gF2JP kiXA== X-Gm-Message-State: AOAM531erSUPrcWn2eSlyjTdgKVHKQuHFB3j5ZO4+qLwQU5L/LMP99Od ELZreCoMNl5nunZo/T4qVaTxPdjboSfX4A== X-Google-Smtp-Source: ABdhPJwzmYVJHTh+ZG7U+5WPLuwqasVsUl81thLd/BHqyWYQQpaxz6sy3srKwZeETHx2VNL+yehpbg== X-Received: by 2002:a17:90a:fd82:: with SMTP id cx2mr3102172pjb.20.1598389274338; Tue, 25 Aug 2020 14:01:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 62/77] target/microblaze: Try to keep imm and delay slot together Date: Tue, 25 Aug 2020 13:59:35 -0700 Message-Id: <20200825205950.730499-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If the last insn on a page is imm, or a branch with delay slot, then end a tb early if this has not begun the tb. If it has begun the tb, then we can allow the tb to span two pages as if the imm plus its consumer, or branch plus delay, or imm plus branch plus delay, are a single insn. If the insn in the delay slot faults, then the exception handler will have reset the PC to the beginning of this sequence anyway, via the stored D_FLAG and BIMM_FLAG bits. Disable all of this when single-stepping. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++++++++++++++++++----- 1 file changed, 56 insertions(+), 9 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4675326083..fcfc1ac184 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -530,11 +530,50 @@ static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCG= v_i32 inb) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idivu, use_div, true, gen_idivu) =20 +/* + * Try to keep the current instruction with the one following. + * So if this insn is the last in the TB, and is not the first + * in the TB, and we are not singlestepping, then back up and + * exit the current TB. + */ +static bool wait_for_next_tb(DisasContext *dc) +{ + if (dc->base.num_insns >=3D dc->base.max_insns + && !dc->base.singlestep_enabled) { + /* Also consider if this insn (e.g. brid) itself uses an imm. */ + int ninsns =3D (dc->tb_flags & IMM_FLAG ? 2 : 1); + + /* + * If this is not the first insn in the TB, back up and + * start again with a new TB. + */ + if (dc->base.num_insns > ninsns) { + dc->base.pc_next -=3D ninsns * 4; + dc->base.num_insns -=3D ninsns; + dc->base.is_jmp =3D DISAS_TOO_MANY; + return true; + } + + /* + * Correspondingly, if this is the first insn of the TB, + * then extend the TB as necessary to keep it with the + * next insn. Do this by *reducing* the number of insns + * processed by this TB so that icount does fail an assertion. + */ + if (dc->base.num_insns =3D=3D ninsns) { + dc->base.num_insns =3D 0; + } + } + return false; +} + static bool trans_imm(DisasContext *dc, arg_imm *arg) { - dc->ext_imm =3D arg->imm << 16; - tcg_gen_movi_i32(cpu_imm, dc->ext_imm); - dc->tb_flags_to_set =3D IMM_FLAG; + if (!wait_for_next_tb(dc)) { + dc->ext_imm =3D arg->imm << 16; + tcg_gen_movi_i32(cpu_imm, dc->ext_imm); + dc->tb_flags_to_set =3D IMM_FLAG; + } return true; } =20 @@ -1311,12 +1350,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i3= 2 pc_true, TCGv_i32 pc_false) tcg_temp_free_i32(zero); } =20 -static void dec_setup_dslot(DisasContext *dc) +static bool dec_setup_dslot(DisasContext *dc) { + if (wait_for_next_tb(dc)) { + return true; + } + dc->tb_flags_to_set |=3D D_FLAG; if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { dc->tb_flags_to_set |=3D BIMM_FLAG; } + return false; } =20 static void dec_bcc(DisasContext *dc) @@ -1327,8 +1371,8 @@ static void dec_bcc(DisasContext *dc) cc =3D EXTRACT_FIELD(dc->ir, 21, 23); dslot =3D dc->ir & (1 << 25); =20 - if (dslot) { - dec_setup_dslot(dc); + if (dslot && dec_setup_dslot(dc)) { + return; } =20 if (dc->type_b) { @@ -1402,9 +1446,10 @@ static void dec_br(DisasContext *dc) } } =20 - if (dslot) { - dec_setup_dslot(dc); + if (dslot && dec_setup_dslot(dc)) { + return; } + if (link && dc->rd) { tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } @@ -1513,7 +1558,9 @@ static void dec_rts(DisasContext *dc) return; } =20 - dec_setup_dslot(dc); + if (dec_setup_dslot(dc)) { + return; + } =20 if (i_bit) { dc->tb_flags |=3D DRTI_FLAG; --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390863; cv=none; d=zohomail.com; s=zohoarc; b=UgcEeM/nb2oRwtgVHI1InX1nd8x0RME41f5cltI+XQA4uf4eOoc49lKvk3ZGf8mbgWx8wBDN3kK7DYDKxHUm+rVnx+da+6K0O4GnSpHKqPn64CBbYiQjQUeJFYCMYuquQuluKG0n/xaDDeR3h9BSpKKCcbK2mwI64TG5vcRSvUE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390863; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i2qfh0mDAgjTBP8C+mFuEsdvxN4n1xrDbeVevJtZNBs=; b=YEeeqhOffeteTtZBaPDadiCuOVPiFLi50+qx89DWCBVh0OWtF2aTa5ACrKrxFcIUNmOKdlyPnJR4dSOZUxkAYaVkK7cZS4azpZ+Wx6Ktv+ImcE3lJNY6KfVfp2VySl7Bgi5B2OyXRkLwJpemZubDCH49njjfQyh89EMXdU9/zac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390863634727.8291417774942; Tue, 25 Aug 2020 14:27:43 -0700 (PDT) Received: from localhost ([::1]:41326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgTm-00034Z-8W for importer@patchew.org; Tue, 25 Aug 2020 17:27:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4F-0000TL-VB for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:20 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:35623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4D-00021t-Eu for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:19 -0400 Received: by mail-pj1-x1043.google.com with SMTP id g6so130728pjl.0 for ; Tue, 25 Aug 2020 14:01:16 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i2qfh0mDAgjTBP8C+mFuEsdvxN4n1xrDbeVevJtZNBs=; b=lbppmRKo0jw7ca+ubSuB969H0c5nwEluQuREo/a4Johc8+OlTKm0jUvX/pwFG8V12X I6HaWknVJUF7kJbJWpZj6cCkEeZbB7aTGFUL4zf2Qao/GtRveeIxBFYlTI1YtkFSnrU8 Y/Is/00qiHu2J2O+Pg2c4nBe+MPljPqhQzuIl1hVITRcMaq2teB9WRPx5B1BBSHHrq+/ /XYEihuLoC/YuzqIDLmP7XQmfkYKcwtuiEZ1pWLryiR/TjP0h46k5lNpwNPx9YFTlWsn alPneG/o7+7Tv+WbbOjIpTHduPXVmZCtuDR/o7opWhvaDGAQbt/YFWUIk5NT/lkCBhCy scJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i2qfh0mDAgjTBP8C+mFuEsdvxN4n1xrDbeVevJtZNBs=; b=ouaKutzX2XuZfgOnnDrpa5ns/pm0OGpqp/wIk/JToEgzBwH3Bp61QnvR0vucwd5t1k 6Mews6Auq8w3q8oiGA4ZavHacnDX+XeP5XIikAuQHxDfLHn9dax9/En5Z+cnnPawQNCC ILyNm8cG2CEVezbwCEvjCTXLojliVH4/1OYW7RPV5oUpgjYja3kyfCOtC6om5V0ZrHPc w/A6SPDo5Ch8YL9x9nTHLKHgUM/ELlh0YC2plpBsNbl2eIHtGQkEgRyJXQ298+MWCizW a+NKtJaVJC4MSjaxvIObRgdpcSdXR76tyCV8pUxjX5+5b04PQ2abUowEfOYNaIVvTGb0 Rq1w== X-Gm-Message-State: AOAM530b/EBw5hc5eoITrFFA1H/j2n188ZJuqxcm3KvCokhB9RUtNqf9 laR3XufX3dgKsaKatNGAOSNjB6FlY1Fqog== X-Google-Smtp-Source: ABdhPJz2nzuCa3ZNpzp3x34/5Idr715XEZ/JjEUaVXuoz5vLBfUajcz3sQwcvZBAPWcFwDH0rlC4Qw== X-Received: by 2002:a17:90b:1895:: with SMTP id mn21mr3150064pjb.173.1598389275473; Tue, 25 Aug 2020 14:01:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 63/77] target/microblaze: Convert brk and brki to decodetree Date: Tue, 25 Aug 2020 13:59:36 -0700 Message-Id: <20200825205950.730499-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm !=3D 0x18 is not supposed to set MSR_BIP. This fixes a bug in that imm =3D=3D 0 is the reset vector and 0x18 is the debug vector, and neither should raise a tcg exception in system mode. Introduce EXCP_SYSCALL for microblaze-linux-user. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/insns.decode | 11 ++++ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/helper.c | 10 +-- target/microblaze/translate.c | 107 ++++++++++++++++++------------- 5 files changed, 79 insertions(+), 53 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 63b8d93d41..1528749a0b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -31,7 +31,7 @@ typedef struct CPUMBState CPUMBState; =20 #define EXCP_MMU 1 #define EXCP_IRQ 2 -#define EXCP_BREAK 3 +#define EXCP_SYSCALL 3 /* user-only */ #define EXCP_HW_BREAK 4 #define EXCP_HW_EXCP 5 =20 diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 998f997adc..53da2b75aa 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -19,7 +19,9 @@ =20 &typea0 rd ra &typea rd ra rb +&typea_br rd rb &typeb rd ra imm +&typeb_br rd imm =20 # Include any IMM prefix in the value reported. %extimm 0:s16 !function=3Dtypeb_imm @@ -30,9 +32,15 @@ # Officially typea, but with rb=3D=3D0, which is not used. @typea0 ...... rd:5 ra:5 ................ &typea0 =20 +# Officially typea, but with ra as opcode. +@typea_br ...... rd:5 ..... rb:5 ........... &typea_br + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb =20 +# Officially typeb, but with ra as opcode. +@typeb_br ...... rd:5 ..... ................ &typeb_br imm=3D%e= xtimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -57,6 +65,9 @@ andi 101001 ..... ..... ................ @= typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb =20 +brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br +brki 101110 ..... 01100 ................ @typeb_br + bsrl 010001 ..... ..... ..... 000 0000 0000 @typea bsra 010001 ..... ..... ..... 010 0000 0000 @typea bsll 010001 ..... ..... ..... 100 0000 0000 @typea diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 3de99ea311..c3396a6e09 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUMBState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case EXCP_BREAK: + case EXCP_SYSCALL: /* Return address is 4 bytes after the call. */ env->regs[14] +=3D 4; env->pc =3D env->regs[14]; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 0e3be251a7..1667822fb7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -230,7 +230,6 @@ void mb_cpu_do_interrupt(CPUState *cs) //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; =20 - case EXCP_BREAK: case EXCP_HW_BREAK: assert(!(env->iflags & IMM_FLAG)); assert(!(env->iflags & D_FLAG)); @@ -242,13 +241,8 @@ void mb_cpu_do_interrupt(CPUState *cs) msr &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); msr |=3D t; msr |=3D MSR_BIP; - if (cs->exception_index =3D=3D EXCP_HW_BREAK) { - env->regs[16] =3D env->pc; - msr |=3D MSR_BIP; - env->pc =3D cpu->cfg.base_vectors + 0x18; - } else { - env->pc =3D env->btarget; - } + env->regs[16] =3D env->pc; + env->pc =3D cpu->cfg.base_vectors + 0x18; mb_cpu_write_msr(env, msr); break; default: diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fcfc1ac184..fc1c661368 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1107,6 +1107,65 @@ static bool trans_swx(DisasContext *dc, arg_typea *a= rg) return true; } =20 +static bool trans_brk(DisasContext *dc, arg_typea_br *arg) +{ + if (trap_userspace(dc, true)) { + return true; + } + tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb)); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); + tcg_gen_movi_tl(cpu_res_addr, -1); + + dc->base.is_jmp =3D DISAS_UPDATE; + return true; +} + +static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) +{ + uint32_t imm =3D arg->imm; + + if (trap_userspace(dc, imm !=3D 0x8 && imm !=3D 0x18)) { + return true; + } + tcg_gen_movi_i32(cpu_pc, imm); + if (arg->rd) { + tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next); + } + tcg_gen_movi_tl(cpu_res_addr, -1); + +#ifdef CONFIG_USER_ONLY + switch (imm) { + case 0x8: /* syscall trap */ + gen_raise_exception_sync(dc, EXCP_SYSCALL); + break; + case 0x18: /* debug trap */ + gen_raise_exception_sync(dc, EXCP_DEBUG); + break; + default: /* eliminated with trap_userspace check */ + g_assert_not_reached(); + } +#else + uint32_t msr_to_set =3D 0; + + if (imm !=3D 0x18) { + msr_to_set |=3D MSR_BIP; + } + if (imm =3D=3D 0x8 || imm =3D=3D 0x18) { + /* MSR_UM and MSR_VM are in tb_flags, so we know their value. */ + msr_to_set |=3D (dc->tb_flags & (MSR_UM | MSR_VM)) << 1; + tcg_gen_andi_i32(cpu_msr, cpu_msr, + ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); + } + tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); + dc->base.is_jmp =3D DISAS_UPDATE; +#endif + + return true; +} + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1389,6 +1448,7 @@ static void dec_bcc(DisasContext *dc) static void dec_br(DisasContext *dc) { unsigned int dslot, link, abs, mbar; + uint32_t add_pc; =20 dslot =3D dc->ir & (1 << 20); abs =3D dc->ir & (1 << 19); @@ -1431,21 +1491,6 @@ static void dec_br(DisasContext *dc) return; } =20 - if (abs && link && !dslot) { - if (dc->type_b) { - /* BRKI */ - uint32_t imm =3D dec_alu_typeb_imm(dc); - if (trap_userspace(dc, imm !=3D 8 && imm !=3D 0x18)) { - return; - } - } else { - /* BRK */ - if (trap_userspace(dc, true)) { - return; - } - } - } - if (dslot && dec_setup_dslot(dc)) { return; } @@ -1454,38 +1499,14 @@ static void dec_br(DisasContext *dc) tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); } =20 - if (abs) { - if (dc->type_b) { - uint32_t dest =3D dec_alu_typeb_imm(dc); - - dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D dest; - tcg_gen_movi_i32(cpu_btarget, dest); - if (link && !dslot) { - switch (dest) { - case 8: - case 0x18: - gen_raise_exception_sync(dc, EXCP_BREAK); - break; - case 0: - gen_raise_exception_sync(dc, EXCP_DEBUG); - break; - } - } - } else { - dc->jmp =3D JMP_INDIRECT; - tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); - if (link && !dslot) { - gen_raise_exception_sync(dc, EXCP_BREAK); - } - } - } else if (dc->type_b) { + add_pc =3D abs ? 0 : dc->base.pc_next; + if (dc->type_b) { dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + dc->jmp_pc =3D add_pc + dec_alu_typeb_imm(dc); tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); } else { dc->jmp =3D JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } tcg_gen_movi_i32(cpu_btaken, 1); } --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391888; cv=none; d=zohomail.com; s=zohoarc; b=b8Bvmtzlo7X98+vE4g8KemIlDiJI743p7t1KeCtoYm7OBNkRcOtncagz5sGtB9yR5uRsOsmsrtRWYUhAx1fz5EhWFS7MvqUgOOUe0M34ywyOJgI+ToizB9GCJJVu9Omp4JklGhQ7VPJ8SQGnPLzsPcEaX38tzX6um4QclhS3mLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391888; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=A51j8Dt7hNAriffsyYXkcUZkPE7x18U/tnvrUwFnWqG5N0eHD4temTrOsRG9VC/TTZpZQlrAAyJkud26nlT7WIYsuj8+XVR+KiqYuhg1HQBGO8fUrBy7ullnTFSpaW24+LL3tbLqCNA6yAeClETDc7im2tbjGUl+gwj3dQPhWvg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391888679628.0534686132214; Tue, 25 Aug 2020 14:44:48 -0700 (PDT) Received: from localhost ([::1]:54414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgkJ-0006Ra-Fl for importer@patchew.org; Tue, 25 Aug 2020 17:44:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4G-0000Ua-JO for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:20 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4E-000228-I5 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:20 -0400 Received: by mail-pf1-x443.google.com with SMTP id d22so8302791pfn.5 for ; Tue, 25 Aug 2020 14:01:18 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=f+bq5+bU5qJZgyq6pOlmgaDGL5Bj/lO10h+Sr2HJifNlLqLIWRY9WJoKPpTL3Or1Dd 94Xv0tcLB6XirpqoJQrx6kSoanptlvxfTsnxnn4lhRVHDM5fdUV8F5LAtN1JKGTdq3KY cJuLSB4Gn71/78StJpBkItgyAOW5+nNAfPUruv3O6nc2iIM6rX17zkbdLKbUqPfqzhwP +Foi8/KrXKlXoZMduPrPlDeXZnFAuusKSwt3OgKi8ampV61e9kQ7E2+Z47fT6knYfIDL R2mgcWmjFATe1rYSIb0MtQnXBItu3NcvyFFZRTjXTf+8ZofAoCkO4+6UDAtgqT0Xg9ag ERyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4PiB9ZbjBaKjglLtNBxW9KhOjXdbTfOtuRsASAhW4TM=; b=kLxCq+wcZwVmndRKi8m5qRQx4qfSrDLtgQDX3I8dXdyOPKiN6ZGghMN3iRx0gadCiD gL61HrQCBdOin13RYcZMcIygKXTG9aocQsbjmHYCEb2Dq5A///dFT4wlfLQgPQLP9vEk 80EdfBvZ0WhN/xP3wa+BS2RsJcO9cIWBR68tVaYSsIqBN6nRYQs9F5ofxeu93m8qZdp8 iRqi88qp0s+fBoe8rRsKpkwmZcISqtZgt2l3eMOsuQ0jlKKn4t+rQKLO3Ui9i2M7D/cZ zkUd0/qQtI5WvlktjmUjXouxLkfOMGvq7Am3nKwghExDajPqRyvblVOk2m38u4gURQKH TPrw== X-Gm-Message-State: AOAM530PkoQTT0hW5FRVTrL4dnYUGoimHlupIoqc1qI3YqxKlX6WdXf3 0dTMsUzmmjYr5YHJJeL2glNnVMyUw2stxQ== X-Google-Smtp-Source: ABdhPJyYv56oX0DI78meVCbnQ61kaz52TP0P4a9oOcchr444/VGgffcjZGqmGQsAeEXB+O7WatvUoA== X-Received: by 2002:a17:902:8504:: with SMTP id bj4mr8926772plb.231.1598389276759; Tue, 25 Aug 2020 14:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 64/77] target/microblaze: Convert mbar to decodetree Date: Tue, 25 Aug 2020 13:59:37 -0700 Message-Id: <20200825205950.730499-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split this out of the normal branch instructions, as it requires special handling. End the TB only for an instruction barrier. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 81 ++++++++++++++++++---------------- 2 files changed, 45 insertions(+), 38 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 53da2b75aa..77b073be9e 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -124,6 +124,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 = @typea lwx 110010 ..... ..... ..... 1000 000 0000 @typea lwi 111010 ..... ..... ................ @typeb =20 +mbar 101110 imm:5 00010 0000 0000 0000 0100 + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index fc1c661368..a391e80fb9 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1166,6 +1166,48 @@ static bool trans_brki(DisasContext *dc, arg_typeb_b= r *arg) return true; } =20 +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) +{ + int mbar_imm =3D arg->imm; + + /* + * Instruction access memory barrier. + * End the TB so that we recognize self-modified code immediately. + */ + if (mbar_imm & 1) { + dc->cpustate_changed =3D 1; + } + + /* Data access memory barrier. */ + if (mbar_imm & 2) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + + /* Sleep. */ + if (mbar_imm & 16) { + TCGv_i32 tmp_1; + + if (trap_userspace(dc, true)) { + /* Sleep is a privileged instruction. */ + return true; + } + + t_sync_flags(dc); + + tmp_1 =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp_1, cpu_env, + -offsetof(MicroBlazeCPU, env) + +offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp_1); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); + + gen_raise_exception(dc, EXCP_HLT); + } + return true; +} + + static void msr_read(DisasContext *dc, TCGv_i32 d) { TCGv_i32 t; @@ -1447,50 +1489,13 @@ static void dec_bcc(DisasContext *dc) =20 static void dec_br(DisasContext *dc) { - unsigned int dslot, link, abs, mbar; + unsigned int dslot, link, abs; uint32_t add_pc; =20 dslot =3D dc->ir & (1 << 20); abs =3D dc->ir & (1 << 19); link =3D dc->ir & (1 << 18); =20 - /* Memory barrier. */ - mbar =3D (dc->ir >> 16) & 31; - if (mbar =3D=3D 2 && dc->imm =3D=3D 4) { - uint16_t mbar_imm =3D dc->rd; - - /* Data access memory barrier. */ - if ((mbar_imm & 2) =3D=3D 0) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - } - - /* mbar IMM & 16 decodes to sleep. */ - if (mbar_imm & 16) { - TCGv_i32 tmp_1; - - if (trap_userspace(dc, true)) { - /* Sleep is a privileged instruction. */ - return; - } - - t_sync_flags(dc); - - tmp_1 =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp_1, cpu_env, - -offsetof(MicroBlazeCPU, env) - +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - - gen_raise_exception(dc, EXCP_HLT); - return; - } - /* Break the TB. */ - dc->cpustate_changed =3D 1; - return; - } - if (dslot && dec_setup_dslot(dc)) { return; } --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zHtJR2PgLnYmwJnfF35UuanJnJx2PjTcBTvuZ0jGjNE=; b=KiQEVfCouKax1rSSdjEQx9KrexQT9SyEycflGMaClusSis7dIMsS4J7q7LTuNgArae GaJWFpnjJ9U/jIx6WLrIM9NXzsciTOxCUztFhtTSL7MUSYAvyRqPMNoQGB0l6o9Un7cT JrpHUmq9+ZwdD+I4uOOhMR1Kl2p8BZbgmx9zvRQ9+cPQsF9+Y3usSDjXsWMyxNat67OM 4tlLaa61GzQXPP1pL5kS5c2oWemlyEoyjYIs/+Imp0rIx1RkyXHqPoNEydsUazkknNYl Ut0GEjcHSbwdcfvMnTEFic4NI/NjSDJ4WBZCuaiGUZGAU2xSQboLfjglXn+yGvqtao3m P4yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zHtJR2PgLnYmwJnfF35UuanJnJx2PjTcBTvuZ0jGjNE=; b=UnenWT+aKPB/9Dk/z7kWTUO/9cCdg919Ees7LaKtFzpo3+I1sGobYnkN4quFtpLaX7 J8G3NPa3KyJ0mXKApK6GHufCHTIK82531oshaipvG4p7cXrVr7SOwyxAdmudlXyHpg+H Vwijrt5vGRtMd/+uYEFzMcOVNN2W617Y7VqSC19tJoKdlX6+Eln1IO5ynSl8kl5TUqzI W7BWqc6vl6urg5FY3kz0SnAN6pnNmNyiH8GPbO4gDRQQmgAqoWP8N49kRimqc6p3NVbh touwCck0iKoDNM9BLe6d0hk7ZeMtiJeIOSA3oML6G1Cn2pxZcALGflUdC0s6frqtCWfy 7BJQ== X-Gm-Message-State: AOAM532lUFXy3v/3J5AY8OwTcVn4/Pm+r5xIYbCJtXsBNU6+7+hyuKLG W+TEXSGTztqeEnnjP7exbV2pJf0TG/qu/g== X-Google-Smtp-Source: ABdhPJzbM8+/IcwY4LjAadraqi9KtPrrVfpWj6/RtqiTlsRpKe16U+3RhbxJCN6lzbZKCZ0KDhFwig== X-Received: by 2002:a17:90a:644b:: with SMTP id y11mr3206329pjm.13.1598389277873; Tue, 25 Aug 2020 14:01:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 65/77] target/microblaze: Reorganize branching Date: Tue, 25 Aug 2020 13:59:38 -0700 Message-Id: <20200825205950.730499-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic not memory operation), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 4 +- target/microblaze/translate.c | 192 ++++++++++++++-------------------- 2 files changed, 79 insertions(+), 117 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1528749a0b..4298f242a6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -234,8 +234,8 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 =20 struct CPUMBState { - uint32_t btaken; - uint32_t btarget; + uint32_t bvalue; /* TCG temporary, only valid during a TB */ + uint32_t btarget; /* Full resolved branch destination */ =20 uint32_t imm; uint32_t regs[32]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a391e80fb9..6f9b20d391 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -45,7 +45,7 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr_c; static TCGv_i32 cpu_imm; -static TCGv_i32 cpu_btaken; +static TCGv_i32 cpu_bvalue; static TCGv_i32 cpu_btarget; static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; @@ -77,12 +77,11 @@ typedef struct DisasContext { unsigned int tb_flags_to_set; int mem_index; =20 -#define JMP_NOJMP 0 -#define JMP_DIRECT 1 -#define JMP_DIRECT_CC 2 -#define JMP_INDIRECT 3 - unsigned int jmp; - uint32_t jmp_pc; + /* Condition under which to jump, including NEVER and ALWAYS. */ + TCGCond jmp_cond; + + /* Immediate branch-taken destination, or -1 for indirect. */ + uint32_t jmp_dest; =20 int abort_at_next_insn; } DisasContext; @@ -106,17 +105,6 @@ static void t_sync_flags(DisasContext *dc) } } =20 -static inline void sync_jmpstate(DisasContext *dc) -{ - if (dc->jmp =3D=3D JMP_DIRECT || dc->jmp =3D=3D JMP_DIRECT_CC) { - if (dc->jmp =3D=3D JMP_DIRECT) { - tcg_gen_movi_i32(cpu_btaken, 1); - } - dc->jmp =3D JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); - } -} - static void gen_raise_exception(DisasContext *dc, uint32_t index) { TCGv_i32 tmp =3D tcg_const_i32(index); @@ -821,8 +809,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr= , MemOp mop, } } =20 - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -924,8 +910,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - sync_jmpstate(dc); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); tcg_temp_free(addr); @@ -959,8 +943,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, } } =20 - sync_jmpstate(dc); - if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cpu->cfg.unaligned_exceptions) { @@ -1062,8 +1044,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) TCGLabel *swx_fail =3D gen_new_label(); TCGv_i32 tval; =20 - sync_jmpstate(dc); - /* swx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 @@ -1413,44 +1393,6 @@ static void dec_msr(DisasContext *dc) } } =20 -static inline void eval_cc(DisasContext *dc, unsigned int cc, - TCGv_i32 d, TCGv_i32 a) -{ - static const int mb_to_tcg_cc[] =3D { - [CC_EQ] =3D TCG_COND_EQ, - [CC_NE] =3D TCG_COND_NE, - [CC_LT] =3D TCG_COND_LT, - [CC_LE] =3D TCG_COND_LE, - [CC_GE] =3D TCG_COND_GE, - [CC_GT] =3D TCG_COND_GT, - }; - - switch (cc) { - case CC_EQ: - case CC_NE: - case CC_LT: - case CC_LE: - case CC_GE: - case CC_GT: - tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); - break; - default: - cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); - break; - } -} - -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_= false) -{ - TCGv_i32 zero =3D tcg_const_i32(0); - - tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, - cpu_btaken, zero, - pc_true, pc_false); - - tcg_temp_free_i32(zero); -} - static bool dec_setup_dslot(DisasContext *dc) { if (wait_for_next_tb(dc)) { @@ -1466,8 +1408,17 @@ static bool dec_setup_dslot(DisasContext *dc) =20 static void dec_bcc(DisasContext *dc) { + static const TCGCond mb_to_tcg_cc[] =3D { + [CC_EQ] =3D TCG_COND_EQ, + [CC_NE] =3D TCG_COND_NE, + [CC_LT] =3D TCG_COND_LT, + [CC_LE] =3D TCG_COND_LE, + [CC_GE] =3D TCG_COND_GE, + [CC_GT] =3D TCG_COND_GT, + }; unsigned int cc; unsigned int dslot; + TCGv_i32 zero, next; =20 cc =3D EXTRACT_FIELD(dc->ir, 21, 23); dslot =3D dc->ir & (1 << 25); @@ -1476,15 +1427,29 @@ static void dec_bcc(DisasContext *dc) return; } =20 + dc->jmp_cond =3D mb_to_tcg_cc[cc]; + + /* Cache the condition register in cpu_bvalue across any delay slot. = */ + tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); + + /* Store the branch taken destination into btarget. */ if (dc->type_b) { - dc->jmp =3D JMP_DIRECT_CC; - dc->jmp_pc =3D dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest =3D dc->base.pc_next + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp =3D JMP_INDIRECT; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); + dc->jmp_dest =3D -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), + dc->base.pc_next); } - eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); + + /* Compute the final destination into btarget. */ + zero =3D tcg_const_i32(0); + next =3D tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, dc->ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); } =20 static void dec_br(DisasContext *dc) @@ -1506,14 +1471,13 @@ static void dec_br(DisasContext *dc) =20 add_pc =3D abs ? 0 : dc->base.pc_next; if (dc->type_b) { - dc->jmp =3D JMP_DIRECT; - dc->jmp_pc =3D add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); + dc->jmp_dest =3D add_pc + dec_alu_typeb_imm(dc); + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); } else { - dc->jmp =3D JMP_INDIRECT; + dc->jmp_dest =3D -1; tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); } - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond =3D TCG_COND_ALWAYS; } =20 static inline void do_rti(DisasContext *dc) @@ -1596,8 +1560,8 @@ static void dec_rts(DisasContext *dc) dc->tb_flags |=3D DRTE_FLAG; } =20 - dc->jmp =3D JMP_INDIRECT; - tcg_gen_movi_i32(cpu_btaken, 1); + dc->jmp_cond =3D TCG_COND_ALWAYS; + dc->jmp_dest =3D -1; tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); } =20 @@ -1694,13 +1658,14 @@ static void mb_tr_init_disas_context(DisasContextBa= se *dcb, CPUState *cs) =20 dc->cpu =3D cpu; dc->tb_flags =3D dc->base.tb->flags; - dc->jmp =3D dc->tb_flags & D_FLAG ? JMP_INDIRECT : JMP_NOJMP; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; dc->mem_index =3D cpu_mmu_index(&cpu->env, false); + dc->jmp_cond =3D dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NE= VER; + dc->jmp_dest =3D -1; =20 bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); @@ -1769,14 +1734,12 @@ static void mb_tr_translate_insn(DisasContextBase *= dcb, CPUState *cs) dc->tb_flags |=3D dc->tb_flags_to_set; dc->base.pc_next +=3D 4; =20 - if (dc->jmp !=3D JMP_NOJMP && !(dc->tb_flags & D_FLAG)) { + if (dc->jmp_cond !=3D TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) { if (dc->tb_flags & DRTI_FLAG) { do_rti(dc); - } - if (dc->tb_flags & DRTB_FLAG) { + } else if (dc->tb_flags & DRTB_FLAG) { do_rtb(dc); - } - if (dc->tb_flags & DRTE_FLAG) { + } else if (dc->tb_flags & DRTE_FLAG) { do_rte(dc); } dc->base.is_jmp =3D DISAS_JUMP; @@ -1801,19 +1764,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CP= UState *cs) } =20 t_sync_flags(dc); - if (dc->tb_flags & D_FLAG) { - sync_jmpstate(dc); - dc->jmp =3D JMP_NOJMP; - } =20 switch (dc->base.is_jmp) { case DISAS_TOO_MANY: - assert(dc->jmp =3D=3D JMP_NOJMP); gen_goto_tb(dc, 0, dc->base.pc_next); return; =20 case DISAS_UPDATE: - assert(dc->jmp =3D=3D JMP_NOJMP); if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { @@ -1822,35 +1779,41 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CP= UState *cs) return; =20 case DISAS_JUMP: - switch (dc->jmp) { - case JMP_INDIRECT: - { - TCGv_i32 tmp_pc =3D tcg_const_i32(dc->base.pc_next); - eval_cond_jmp(dc, cpu_btarget, tmp_pc); - tcg_temp_free_i32(tmp_pc); + if (dc->jmp_dest !=3D -1 && !cs->singlestep_enabled) { + /* Direct jump. */ + tcg_gen_discard_i32(cpu_btarget); =20 - if (unlikely(cs->singlestep_enabled)) { - gen_raise_exception(dc, EXCP_DEBUG); - } else { - tcg_gen_exit_tb(NULL, 0); - } - } - return; + if (dc->jmp_cond !=3D TCG_COND_ALWAYS) { + /* Conditional direct jump. */ + TCGLabel *taken =3D gen_new_label(); + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - case JMP_DIRECT_CC: - { - TCGLabel *l1 =3D gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); + /* + * Copy bvalue to a temp now, so we can discard bvalue. + * This can avoid writing bvalue to memory when the + * delay slot cannot raise an exception. + */ + tcg_gen_mov_i32(tmp, cpu_bvalue); + tcg_gen_discard_i32(cpu_bvalue); + + tcg_gen_brcondi_i32(dc->jmp_cond, tmp, 0, taken); gen_goto_tb(dc, 1, dc->base.pc_next); - gen_set_label(l1); + gen_set_label(taken); } - /* fall through */ - - case JMP_DIRECT: - gen_goto_tb(dc, 0, dc->jmp_pc); + gen_goto_tb(dc, 0, dc->jmp_dest); return; } - /* fall through */ + + /* Indirect jump (or direct jump w/ singlestep) */ + tcg_gen_mov_i32(cpu_pc, cpu_btarget); + tcg_gen_discard_i32(cpu_btarget); + + if (unlikely(cs->singlestep_enabled)) { + gen_raise_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + return; =20 default: g_assert_not_reached(); @@ -1902,8 +1865,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) qemu_fprintf(f, " BIMM"); } if (iflags & D_FLAG) { - qemu_fprintf(f, " D(btaken=3D%d btarget=3D0x%08x)", - env->btaken, env->btarget); + qemu_fprintf(f, " D(btarget=3D0x%08x)", env->btarget); } if (iflags & DRTI_FLAG) { qemu_fprintf(f, " DRTI"); @@ -1953,7 +1915,7 @@ void mb_tcg_init(void) SP(msr_c), SP(imm), SP(iflags), - SP(btaken), + SP(bvalue), SP(btarget), SP(res_val), }; --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391629; cv=none; d=zohomail.com; s=zohoarc; b=J9FiVYfuFM7vjmKKg/RcL3yxmtx36BTHKtL2dYaHJK0v884QNfYpQ9cacfEoJvatCPEbYiMoctZKEX75lvcIGMq5e6HjCGL+z+7mNudzDe5wEe9yCaldMsaZvJY6DFobE32kUlxvZM6FmTXWxJau8MkO2ssa+223vVujZ6vSU/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391629; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kCj2p6cdsHJiVaOy7fcU1XDToXHd7PgB9wDLfRyOeOo=; b=iyLDZy3wBLwPhZmiHBAYc/WrUacj+U3Brb76I1xPjhUvDlp9NIc9mko/K4JhM74Y6j FvB6t30ElGJlmryON6dyfr5f9a5XEopyPKgyg0bLoodaalqiHWt/dGdGDfN4OxRkharH BlgGu0mm35zhLxrAST9aXjbGC3W7N3DRsm20AA2HKYmg2yFCzooVveQdkaHoVCI9X2F0 I1cw2S/PHQs9koepRJ/vBQ74BbsBuj8pQt2r+FFvrmfjG8xs3/WmcnO4geEmJTM7VLZ0 8pVI1jqBeSIbkzhvmIhMTEuWvyEZxmd6vjplebwbtsc15yEhNNGCy1CFGghtpUYtEC48 hrSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kCj2p6cdsHJiVaOy7fcU1XDToXHd7PgB9wDLfRyOeOo=; b=WgoAP2hQ3l41bz9PR/zLbdY9+onD15q1KWwdpdvZMmV1pnE3jGGuRk1kOJNU10fk3S vGLBih1em7e2u9b/BnBg+OGYBIh+JKYSjSYwbSh/KLZ3dUo4ZXCw2w6/YqQGwelHXtbR X+pOHc7P7GaE6/Pb5RUrhNiND8fOXwoffqlWdVq9+vcBQ71xBVK1zB9T1KMXsVaAt6N+ 2G3FPDnJ6BxdzTo+wVhqOp+bcQjiU/SMStCOm+S+gV5lENFr8d6YIuebHq0S7AuUAj1c P1YO/rBVPVnBzb7OPKr3INU+zbORMXGsKxpCiNPUKhDl4xDuOwjxhLVoYs5bBrGhr9L1 dIng== X-Gm-Message-State: AOAM532ZO7BJmwCikYfzS1nbmr0ySpn9ooKL2x788BumXCD7hsdT3Nm1 Iu4aBp/Rj3Z9run5K/ikIX/VD2dQG8Iqtg== X-Google-Smtp-Source: ABdhPJwPCYJbW1/+LoAXnWfKCZI6Ymk1YvtMFB0pqSX6Jv9Dc74iQ1U56/OpCzYhp/n8f24R4ZzKwQ== X-Received: by 2002:aa7:9ec4:: with SMTP id r4mr9368631pfq.48.1598389279162; Tue, 25 Aug 2020 14:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Date: Tue, 25 Aug 2020 13:59:39 -0700 Message-Id: <20200825205950.730499-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When goto_tb cannot be used due to branch page crossing, or due to indirect jumping, tcg_gen_lookup_and_goto_ptr can be used instead. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6f9b20d391..5bd771671b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -152,7 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target= _ulong dest) tcg_gen_exit_tb(dc->base.tb, n); } else { tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp =3D DISAS_NORETURN; } @@ -1811,7 +1811,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUS= tate *cs) if (unlikely(cs->singlestep_enabled)) { gen_raise_exception(dc, EXCP_DEBUG); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } return; =20 --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598392031; cv=none; d=zohomail.com; s=zohoarc; b=T+5Y35QXZmNMvRea4fIEYdtov3c2qYiaK4uTEdbpgj1peeFRNXpmMNHpmHazKlRgcmgSiWwHCFs5kBV2R9E4XUVPhmXHW8UHx7/yv+o6GdDU8ZuV+EFo/zJrerOmhxrYN3VVfMP54Xhm60RORRO2lZ7X0bhWQG/NT/vFkg0Iwig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598392031; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U/xg7pKRu/7l+32EdVsp/pmb28o9isw6bULWSNvN3q8=; b=N7eSHBZhbRCfxngs1SBTrfCSUGdr+kGi0rMMlzurMmJJIlOuR3gD3oXwLBgSeho7uQfZvYqy4d2j32XZKVmZyKxQqh8wyQcr6y4hn2EP908yTbDwBxxvtRmajMmJmSihUMoPU4K5goUA5B3bf7QxOQQO8T0SkyauYyoGtXm3d3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598392031419738.4136099415172; Tue, 25 Aug 2020 14:47:11 -0700 (PDT) Received: from localhost ([::1]:34166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgmc-0001TI-54 for importer@patchew.org; Tue, 25 Aug 2020 17:47:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4K-0000d6-JX for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:24 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:40298) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4I-00022n-8y for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:24 -0400 Received: by mail-pf1-x442.google.com with SMTP id k18so8291662pfp.7 for ; Tue, 25 Aug 2020 14:01:21 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U/xg7pKRu/7l+32EdVsp/pmb28o9isw6bULWSNvN3q8=; b=zu1rPsZahCWj6U+5r+ChwJOfXGAuSalR2CrhBLfYgSh2k0/4D2kaCTwEmeOLynl26r Ix68mMc+H7B0Guu+wp8Z4W5fsI0QhfYGSp+eavVSlqYzxvRZFymK0HPnrGpzeyC1iEG/ xTt+tnU1FGMUbmbx8i5p0mSwkfBES/43c/6jy83J+PwO0IiBrHxCx95p8Oc822FZJlEn /kTbwQgnq2QqDgllCjOTTBlMN8Hox4zXiG1mlgo4u3xErWCgHNpBzLRWhW/Q6PMp9wed zKqTE0NcY8MsU3vqZcWI8icvQsjnOmH7DENdhOuXEi4YhX/CZ/yxBJvBjQ0ioUxxD3Mc t++A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U/xg7pKRu/7l+32EdVsp/pmb28o9isw6bULWSNvN3q8=; b=c096Z1v+Bs3f9XXe8K2xwGqGDSO+BROBJ6PnfcNWJCZ7oPdOZBY/BZmFTDLxx77VBo NmkjBkOYcZGUmMSPvaOI7FIQCXalbwdvQY1OxHFC6uCEUGg4tS6Cdk05w5IArV0UMXR4 H2Wma1PLkb9rNWwzBOMySxmLIFBabjq6EP5qBPReRFWly2tRxx9fywqdVT9lIVxztm31 TzX1LfTEwWhdmFWGUYx2q6a4QrfPPjUkT+AQD6nLvF7izotiQZceIbC+NB6SlHKt0Bph PSeuSW6a580v68HYJIYPTYu29bM04IjwSw7g7u3bWEXzBMqLoUX7LjGXcIXcoA34zk1+ lLlw== X-Gm-Message-State: AOAM533qpvT3v5FFmv/VH0DdlE2Ixse4PjXdVHaQ+aAf40mItr/Lqp62 IYiOvhd68ywyWtmjDsr64QZfv1sAm8tU7w== X-Google-Smtp-Source: ABdhPJy4CXL8bKZA59ZiycY/1ojngCORr7geDfuGpAtUIQd33avHdrCrglt8VSBx1Mu/fGmrUoIKuw== X-Received: by 2002:aa7:84d4:: with SMTP id x20mr9059039pfn.96.1598389280332; Tue, 25 Aug 2020 14:01:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 67/77] target/microblaze: Convert dec_br to decodetree Date: Tue, 25 Aug 2020 13:59:40 -0700 Message-Id: <20200825205950.730499-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 +++++ target/microblaze/translate.c | 98 +++++++++++++++++++--------------- 2 files changed, 68 insertions(+), 44 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 77b073be9e..94520e92dd 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -65,6 +65,20 @@ andi 101001 ..... ..... ................ = @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb =20 +br 100110 ..... 00000 ..... 000 0000 0000 @typea_br +bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br +brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br +brad 100110 ..... 11000 ..... 000 0000 0000 @typea_br +brld 100110 ..... 10100 ..... 000 0000 0000 @typea_br +brald 100110 ..... 11100 ..... 000 0000 0000 @typea_br + +bri 101110 ..... 00000 ................ @typeb_br +brai 101110 ..... 01000 ................ @typeb_br +brid 101110 ..... 10000 ................ @typeb_br +braid 101110 ..... 11000 ................ @typeb_br +brlid 101110 ..... 10100 ................ @typeb_br +bralid 101110 ..... 11100 ................ @typeb_br + brk 100110 ..... 01100 ..... 000 0000 0000 @typea_br brki 101110 ..... 01100 ................ @typeb_br =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 5bd771671b..73c956cd76 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1087,6 +1087,58 @@ static bool trans_swx(DisasContext *dc, arg_typea *a= rg) return true; } =20 +static bool setup_dslot(DisasContext *dc) +{ + if (wait_for_next_tb(dc)) { + return true; + } + + dc->tb_flags_to_set |=3D D_FLAG; + if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + dc->tb_flags_to_set |=3D BIMM_FLAG; + } + return false; +} + +static bool do_branch(DisasContext *dc, int dest_rb, int dest_imm, + bool delay, bool abs, int link) +{ + uint32_t add_pc; + + if (delay && setup_dslot(dc)) { + return true; + } + + if (link) { + tcg_gen_movi_i32(cpu_R[link], dc->base.pc_next); + } + + /* Store the branch taken destination into btarget. */ + add_pc =3D abs ? 0 : dc->base.pc_next; + if (dest_rb) { + dc->jmp_dest =3D -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], add_pc); + } else { + dc->jmp_dest =3D add_pc + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + dc->jmp_cond =3D TCG_COND_ALWAYS; + return true; +} + +#define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) = \ + static bool trans_##NAME(DisasContext *dc, arg_typea_br *arg) = \ + { return do_branch(dc, arg->rb, 0, DELAY, ABS, LINK ? arg->rd : 0); } = \ + static bool trans_##NAMEI(DisasContext *dc, arg_typeb_br *arg) = \ + { return do_branch(dc, 0, arg->imm, DELAY, ABS, LINK ? arg->rd : 0); } + +DO_BR(br, bri, false, false, false) +DO_BR(bra, brai, false, true, false) +DO_BR(brd, brid, true, false, false) +DO_BR(brad, braid, true, true, false) +DO_BR(brld, brlid, true, false, true) +DO_BR(brald, bralid, true, true, true) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1393,19 +1445,6 @@ static void dec_msr(DisasContext *dc) } } =20 -static bool dec_setup_dslot(DisasContext *dc) -{ - if (wait_for_next_tb(dc)) { - return true; - } - - dc->tb_flags_to_set |=3D D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { - dc->tb_flags_to_set |=3D BIMM_FLAG; - } - return false; -} - static void dec_bcc(DisasContext *dc) { static const TCGCond mb_to_tcg_cc[] =3D { @@ -1423,7 +1462,7 @@ static void dec_bcc(DisasContext *dc) cc =3D EXTRACT_FIELD(dc->ir, 21, 23); dslot =3D dc->ir & (1 << 25); =20 - if (dslot && dec_setup_dslot(dc)) { + if (dslot && setup_dslot(dc)) { return; } =20 @@ -1452,34 +1491,6 @@ static void dec_bcc(DisasContext *dc) tcg_temp_free_i32(next); } =20 -static void dec_br(DisasContext *dc) -{ - unsigned int dslot, link, abs; - uint32_t add_pc; - - dslot =3D dc->ir & (1 << 20); - abs =3D dc->ir & (1 << 19); - link =3D dc->ir & (1 << 18); - - if (dslot && dec_setup_dslot(dc)) { - return; - } - - if (link && dc->rd) { - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - } - - add_pc =3D abs ? 0 : dc->base.pc_next; - if (dc->type_b) { - dc->jmp_dest =3D add_pc + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest =3D -1; - tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], add_pc); - } - dc->jmp_cond =3D TCG_COND_ALWAYS; -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1548,7 +1559,7 @@ static void dec_rts(DisasContext *dc) return; } =20 - if (dec_setup_dslot(dc)) { + if (setup_dslot(dc)) { return; } =20 @@ -1612,7 +1623,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_BR, dec_br}, {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390971; cv=none; d=zohomail.com; s=zohoarc; b=Afn4/dXYiEewD+YQQ0tpZUAmOUnzrPsfk30kRI6RPRIDq1FI9MEO575LMtS+pb/2SG3vMJb4qr94lZEro9dqw/FZoDX6yUYWYemILpt8/iBfyLNmITz8HFHNhp3sGznt/Lj2ZCErXIvqwdqMUoum6g3Dz27PZBh+myHdIPz1dG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390971; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bfpqz7V+nismyYMkhAn5GwE9vkpITs4IMKYzm6EnI7g=; b=bxKr8yd+U+hGnu3lrvxmbbMQv8L8jw16XtHL/e9nWwr/yeTQDiyx4tSHiQyL22znqDWswSFM+lThUz1esEkyMMygf+rmRwncYJKgDRohOalehsDTOens7IraamX4PL4/I0AMxA4Rp6g0VdtHca4QsX3vWhRFVROO4PaugDFxm30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390971593207.58428768679926; Tue, 25 Aug 2020 14:29:31 -0700 (PDT) Received: from localhost ([::1]:49374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgVW-0006Lf-5o for importer@patchew.org; Tue, 25 Aug 2020 17:29:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4L-0000gS-VS for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:26 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4J-000232-K1 for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:25 -0400 Received: by mail-pg1-x541.google.com with SMTP id d19so7664907pgl.10 for ; Tue, 25 Aug 2020 14:01:23 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 36 +++++++++++++ target/microblaze/translate.c | 99 ++++++++++++++++++---------------- 2 files changed, 88 insertions(+), 47 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 94520e92dd..21d08289f7 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -20,8 +20,10 @@ &typea0 rd ra &typea rd ra rb &typea_br rd rb +&typea_bc ra rb &typeb rd ra imm &typeb_br rd imm +&typeb_bc ra imm =20 # Include any IMM prefix in the value reported. %extimm 0:s16 !function=3Dtypeb_imm @@ -35,12 +37,18 @@ # Officially typea, but with ra as opcode. @typea_br ...... rd:5 ..... rb:5 ........... &typea_br =20 +# Officially typea, but with rd as opcode. +@typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc + # Officially typeb, but any immediate extension is unused. @typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb =20 # Officially typeb, but with ra as opcode. @typeb_br ...... rd:5 ..... ................ &typeb_br imm=3D%e= xtimm =20 +# Officially typeb, but with rd as opcode. +@typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=3D%e= xtimm + # For convenience, extract the two imm_w/imm_s fields, then pack # them back together as "imm". Doing this makes it easiest to # match the required zero at bit 5. @@ -65,6 +73,34 @@ andi 101001 ..... ..... ................ = @typeb andn 100011 ..... ..... ..... 000 0000 0000 @typea andni 101011 ..... ..... ................ @typeb =20 +beq 100111 00000 ..... ..... 000 0000 0000 @typea_bc +bge 100111 00101 ..... ..... 000 0000 0000 @typea_bc +bgt 100111 00100 ..... ..... 000 0000 0000 @typea_bc +ble 100111 00011 ..... ..... 000 0000 0000 @typea_bc +blt 100111 00010 ..... ..... 000 0000 0000 @typea_bc +bne 100111 00001 ..... ..... 000 0000 0000 @typea_bc + +beqd 100111 10000 ..... ..... 000 0000 0000 @typea_bc +bged 100111 10101 ..... ..... 000 0000 0000 @typea_bc +bgtd 100111 10100 ..... ..... 000 0000 0000 @typea_bc +bled 100111 10011 ..... ..... 000 0000 0000 @typea_bc +bltd 100111 10010 ..... ..... 000 0000 0000 @typea_bc +bned 100111 10001 ..... ..... 000 0000 0000 @typea_bc + +beqi 101111 00000 ..... ................ @typeb_bc +bgei 101111 00101 ..... ................ @typeb_bc +bgti 101111 00100 ..... ................ @typeb_bc +blei 101111 00011 ..... ................ @typeb_bc +blti 101111 00010 ..... ................ @typeb_bc +bnei 101111 00001 ..... ................ @typeb_bc + +beqid 101111 10000 ..... ................ @typeb_bc +bgeid 101111 10101 ..... ................ @typeb_bc +bgtid 101111 10100 ..... ................ @typeb_bc +bleid 101111 10011 ..... ................ @typeb_bc +bltid 101111 10010 ..... ................ @typeb_bc +bneid 101111 10001 ..... ................ @typeb_bc + br 100110 ..... 00000 ..... 000 0000 0000 @typea_br bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 73c956cd76..f79b02e987 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1139,6 +1139,58 @@ DO_BR(brad, braid, true, true, false) DO_BR(brld, brlid, true, false, true) DO_BR(brald, bralid, true, true, true) =20 +static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm, + TCGCond cond, int ra, bool delay) +{ + TCGv_i32 zero, next; + + if (delay && setup_dslot(dc)) { + return true; + } + + dc->jmp_cond =3D cond; + + /* Cache the condition register in cpu_bvalue across any delay slot. = */ + tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra)); + + /* Store the branch taken destination into btarget. */ + if (dest_rb) { + dc->jmp_dest =3D -1; + tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next); + } else { + dc->jmp_dest =3D dc->base.pc_next + dest_imm; + tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); + } + + /* Compute the final destination into btarget. */ + zero =3D tcg_const_i32(0); + next =3D tcg_const_i32(dc->base.pc_next + (delay + 1) * 4); + tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, + reg_for_read(dc, ra), zero, + cpu_btarget, next); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(next); + + return true; +} + +#define DO_BCC(NAME, COND) \ + static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); } \ + static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg) \ + { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); } \ + static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, 0, arg->imm, COND, arg->ra, false); } \ + static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_bcc(dc, 0, arg->imm, COND, arg->ra, true); } + +DO_BCC(beq, TCG_COND_EQ) +DO_BCC(bge, TCG_COND_GE) +DO_BCC(bgt, TCG_COND_GT) +DO_BCC(ble, TCG_COND_LE) +DO_BCC(blt, TCG_COND_LT) +DO_BCC(bne, TCG_COND_NE) + static bool trans_brk(DisasContext *dc, arg_typea_br *arg) { if (trap_userspace(dc, true)) { @@ -1445,52 +1497,6 @@ static void dec_msr(DisasContext *dc) } } =20 -static void dec_bcc(DisasContext *dc) -{ - static const TCGCond mb_to_tcg_cc[] =3D { - [CC_EQ] =3D TCG_COND_EQ, - [CC_NE] =3D TCG_COND_NE, - [CC_LT] =3D TCG_COND_LT, - [CC_LE] =3D TCG_COND_LE, - [CC_GE] =3D TCG_COND_GE, - [CC_GT] =3D TCG_COND_GT, - }; - unsigned int cc; - unsigned int dslot; - TCGv_i32 zero, next; - - cc =3D EXTRACT_FIELD(dc->ir, 21, 23); - dslot =3D dc->ir & (1 << 25); - - if (dslot && setup_dslot(dc)) { - return; - } - - dc->jmp_cond =3D mb_to_tcg_cc[cc]; - - /* Cache the condition register in cpu_bvalue across any delay slot. = */ - tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]); - - /* Store the branch taken destination into btarget. */ - if (dc->type_b) { - dc->jmp_dest =3D dc->base.pc_next + dec_alu_typeb_imm(dc); - tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest); - } else { - dc->jmp_dest =3D -1; - tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb), - dc->base.pc_next); - } - - /* Compute the final destination into btarget. */ - zero =3D tcg_const_i32(0); - next =3D tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4); - tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, - reg_for_read(dc, dc->ra), zero, - cpu_btarget, next); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(next); -} - static inline void do_rti(DisasContext *dc) { TCGv_i32 t0, t1; @@ -1623,7 +1629,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_BCC, dec_bcc}, {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LiD17jdfSZ6zoYmLZKhAoxxQtSYU9ummw+8AuEiDbOo=; b=R8tZQiaLS9/YAgwtVCL2/g3j86yToLIsJ+rqSz4s2NVvAGijfAOr3EgpEkZSsDg+Zc tc0OjblT7GK99/ZaFQkL6ecNEO4jV+QnFIk7r/VxhyneRzmbNQp1OjVpYknpj6u+YbFU uJU+2pAm9bRiKbLfG9rQaciVloKr2k0WwUQ33xvZcL3Rm7DYocpWJbjhqChwHQcccXmN mbVAAxnscPBXnpU6kALbykHm0FCjrX211Orz09JG/PUUB67gToYpDGLGhTalPLe8NWBt q625uOtBDPC++jsl1WeUUav8q5ipSK/jItYB0nkoU0YXpa86z88E5sEL+SEADLM4YYAR FciA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LiD17jdfSZ6zoYmLZKhAoxxQtSYU9ummw+8AuEiDbOo=; b=V/Kh0wofEfWvVSKX5t83gKxlYvDOv7oGYZkzDfr564mf8xLAF+4vyOQ0jeBvZ80dke zz/9+O1/9/qgIyi1NCKe2P8GZgqWxzwLDxbOMT6y6kTXAWCBlTTwpMT8rQOCd7lGS5Wa nX78qKm83JC+sA2HUKrI4vJadOPvPiPFOT+jr9Z/SlSKhyBJLxGWl7AEsvZrPkfgrzBJ s8KVswQQOCquWDSsd+VodEe2PtKD/WHMPlneU3VaN+qKK5bELQlpdNMMKr+twdxGqSBj pp3uGZglzhEdQ9Hzoxt685atQu1XfXSq9PVg5861dsbZeTxqMz/pGOqzM/bQZ9S4QLMI UsSg== X-Gm-Message-State: AOAM533UoL63PJL2n0Di1WnIOkC3x06HJqUDV8bwiPowVyFOoMy2qcCr BEonSicOZEx83d9L8jVodxaobrGmWYykZQ== X-Google-Smtp-Source: ABdhPJwvBfhMZPsw/skpHFho6dPD08MWClD6suBhACS9fU261+PYBH/tuWmgZbJInbpQSjlNBnC6Ig== X-Received: by 2002:a05:6a00:2285:: with SMTP id f5mr9213748pfe.173.1598389282779; Tue, 25 Aug 2020 14:01:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 69/77] target/microblaze: Convert dec_rts to decodetree Date: Tue, 25 Aug 2020 13:59:42 -0700 Message-Id: <20200825205950.730499-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 ++++ target/microblaze/translate.c | 54 +++++++++++++++------------------- 2 files changed, 29 insertions(+), 30 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 21d08289f7..f12e85b492 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -199,6 +199,11 @@ rsubic 001011 ..... ..... ................ = @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb =20 +rtbd 101101 10010 ..... ................ @typeb_bc +rtid 101101 10001 ..... ................ @typeb_bc +rted 101101 10100 ..... ................ @typeb_bc +rtsd 101101 10000 ..... ................ @typeb_bc + sb 110100 ..... ..... ..... 0000 000 0000 @typea sbr 110100 ..... ..... ..... 0100 000 0000 @typea sbea 110100 ..... ..... ..... 0001 000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f79b02e987..22569693f7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1291,6 +1291,30 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *a= rg) return true; } =20 +static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) +{ + if (trap_userspace(dc, to_set)) { + return true; + } + if (setup_dslot(dc)) { + return true; + } + dc->tb_flags_to_set |=3D to_set; + + dc->jmp_cond =3D TCG_COND_ALWAYS; + dc->jmp_dest =3D -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm); + return true; +} + +#define DO_RTS(NAME, IFLAG) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_rts(dc, arg, IFLAG); } + +DO_RTS(rtbd, DRTB_FLAG) +DO_RTS(rtid, DRTI_FLAG) +DO_RTS(rted, DRTE_FLAG) +DO_RTS(rtsd, 0) =20 static void msr_read(DisasContext *dc, TCGv_i32 d) { @@ -1553,35 +1577,6 @@ static inline void do_rte(DisasContext *dc) dc->tb_flags &=3D ~DRTE_FLAG; } =20 -static void dec_rts(DisasContext *dc) -{ - unsigned int b_bit, i_bit, e_bit; - - i_bit =3D dc->ir & (1 << 21); - b_bit =3D dc->ir & (1 << 22); - e_bit =3D dc->ir & (1 << 23); - - if (trap_userspace(dc, i_bit || b_bit || e_bit)) { - return; - } - - if (setup_dslot(dc)) { - return; - } - - if (i_bit) { - dc->tb_flags |=3D DRTI_FLAG; - } else if (b_bit) { - dc->tb_flags |=3D DRTB_FLAG; - } else if (e_bit) { - dc->tb_flags |=3D DRTE_FLAG; - } - - dc->jmp_cond =3D TCG_COND_ALWAYS; - dc->jmp_dest =3D -1; - tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1629,7 +1624,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390710; cv=none; d=zohomail.com; s=zohoarc; b=NW7HmvbkZN5FPw7vKsmGyebokASWd99wraReg2nQh/K1PW6V5xA1LEUm0X/YCmDtgv3W7Hmsxo1nc9Ke5t5aiu2597ToSYAulhWp4G7BoON41Mwt/AbIuvUBbT4Dz+MNbc9t6EVt39tMZS8CEoBXXIzPrSTe6g4ecbSLzSTYOzo= ARC-Message-Signature: i=1; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vxCtytkH7BxiV9VxvRB9+Cp9GCqZrISTLIGoNOFV/HY=; b=MRRkThJ+jj13lgnIj+Z2+hpO/ieiSwhs+37RC4PFmMne9X2WsyDsTzrupZU7VJwx8h ORH7RGkU3ZonKxZgNelTDM6ue1oFf/QnoeZJ6u0SoeCtRHByfz9hBaVDHJM4Tb1w9b1b aj9Fl+9AiKGFgxrPaVZaJOiRtjWnxtrQmH3R2jp46v3rTYX5smG/DKPWNaPTjBFtptIk sxQZIuAI0jRhYohlU6cUgGS1+LLDaGKwGJYvxBdj/EKal97UuB/EYx9PGwdNeLMjWdzM OVNIoAaa0/qciXFGK9NDqleC9IxqRIg39L9WQIJgoQ9gXziPFhvValawt/0vEQrrFPFm fTLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vxCtytkH7BxiV9VxvRB9+Cp9GCqZrISTLIGoNOFV/HY=; b=rzfwjWrpwyG3/7Pyc6G7rSGFRaOqx9RY0CUCjJeKWCZYBpRwnwukb3SWwfvwHUgAdD 7MB/szTWZHPEyrSgpvAGFsKXRf8gF5m5XOTKmcZ629yHxm81+17RyzaKMvMw1uQ9lGrN 61wm1/s+Md9CXcys/Fb2NPnSXsd1t7UBwlV8t4+sjR0DuYZt+xS/41nwLJtkKLz4asCZ XLlEJPX4nBqpE6po2PFNFTKhx+NmJ/IN+l9SQ8XwUsCW14U2jxt2bkvlqqT1BIExDTbW yQkZNGHVg1yqsQfDbF3uFadYUmO0Kq8+ghmUX7Eh4vscbjWSiU8JcfsgGaCF7ysJjR8Z I+Zg== X-Gm-Message-State: AOAM531CLjVjDhmIjXdxbspjayOqybMLvSTuwn/5An7PPIaK6Au1X4VI pMCVL4RhVBTSdDHKcr2PC3H3M+dfx90BHw== X-Google-Smtp-Source: ABdhPJyVU0oHRJ0p9SnirYLxVfjwUnNBvM3+RWnMiTok2zhu1tDL9lqSgx+f+lIFx8qPQYMf6z5Lig== X-Received: by 2002:a17:90a:a101:: with SMTP id s1mr2843739pjp.205.1598389284668; Tue, 25 Aug 2020 14:01:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte Date: Tue, 25 Aug 2020 13:59:43 -0700 Message-Id: <20200825205950.730499-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++++++++++++++--------------------- 1 file changed, 25 insertions(+), 40 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 22569693f7..71ceabfffd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1521,59 +1521,44 @@ static void dec_msr(DisasContext *dc) } } =20 -static inline void do_rti(DisasContext *dc) +static void do_rti(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_ori_i32(t1, t1, MSR_IE); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); + tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &=3D ~DRTI_FLAG; } =20 -static inline void do_rtb(DisasContext *dc) +static void do_rtb(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_andi_i32(t1, t1, ~MSR_BIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); + + tcg_temp_free_i32(tmp); dc->tb_flags &=3D ~DRTB_FLAG; } =20 -static inline void do_rte(DisasContext *dc) +static void do_rte(DisasContext *dc) { - TCGv_i32 t0, t1; - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_mov_i32(t1, cpu_msr); - tcg_gen_ori_i32(t1, t1, MSR_EE); - tcg_gen_andi_i32(t1, t1, ~MSR_EIP); - tcg_gen_shri_i32(t0, t1, 1); - tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); + tcg_gen_shri_i32(tmp, cpu_msr, 1); + tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); + tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); + tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); =20 - tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); - tcg_gen_or_i32(t1, t1, t0); - msr_write(dc, t1); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); + tcg_temp_free_i32(tmp); dc->tb_flags &=3D ~DRTE_FLAG; } =20 --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4nKzEtDvQ/HGhwSfCseZ1hDjTvu3zAu+DRp/TAzlmzg=; b=DcvCRwslCknsxHkRwtcpZTJSq4zNwX766iDx86bRNa1/6ceKX5EzMSyZf0BAJ0IXEy 9ECtFCiM+AqWUvl9nGEPxl9sV7ppKbAquJX5wpMKDFlWKGHbuvLYZASIeTTYGIA+4OFI xRQUEZ48agKzlK2UezQfXkdNocAwCOe9iVQQmwPyzcPI3tXywgeslrPnK80sMlNDQNd6 kzMBrw8vqW0xGwNZqM5d52v30kDybN02lPAV2mpTd2at8xLbYBvM295OzUgTDnVc/lY7 nTj36jv4oM/wPHZHJz9NOciZ3Il+i9ie15PENjGTYwn21YGnGK6Vf9iQGGOrsi8K1RPw 5wrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4nKzEtDvQ/HGhwSfCseZ1hDjTvu3zAu+DRp/TAzlmzg=; b=LiuuyqeOtzhlq2kTKX8jx+xET+sKwJePdjeAYF4YyDWfPGYFunFFcppY7tUPe/C2Ki mFz9kY8MIaaXC1yobwGpgBh2k+9bpVYFyFxZBpTgpVO3bgKsko+xWPn1M5fKNcoyV0iO 9JyRemqwnkjvWOu61+HFTR66Rtsrrjh7dut6Szhm5OX1oeXbZ3ORoWhhcl5Vwb/9LPEp WQYMOQ7VXi/G6Kc9guuVDhFmy6Cp+HbSGVFA94fTYYqw9ZCnnPMPxuc1f1NAy6R9zpBu seZIO+Hjo8YD+TvssVbjgA/5Mfzj0q5zYt00rwXRbUBNBHDkqEQQtaIvyC4/YK8ByfA7 y3vQ== X-Gm-Message-State: AOAM533Oi22Ka57v33ZlMBFSMgPhJ8qiUbLYMtuccCwIQpdX4+QlUbE6 ePd1LMTHby4rgnb276IEXq67HVfGS4xzYQ== X-Google-Smtp-Source: ABdhPJw2b+rlSFs3/+lDsZHrJlMeC4RZGBwwdOv1kuC26TlstdowLw7Hrnx5+FIbRhIjNzYVlx3LJw== X-Received: by 2002:a17:90b:1108:: with SMTP id gi8mr2963573pjb.7.1598389285841; Tue, 25 Aug 2020 14:01:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 71/77] target/microblaze: Convert msrclr, msrset to decodetree Date: Tue, 25 Aug 2020 13:59:44 -0700 Message-Id: <20200825205950.730499-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Split this out of dec_msr. Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 37 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index f12e85b492..e80283cce6 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -24,6 +24,7 @@ &typeb rd ra imm &typeb_br rd imm &typeb_bc ra imm +&type_msr rd imm =20 # Include any IMM prefix in the value reported. %extimm 0:s16 !function=3Dtypeb_imm @@ -55,6 +56,8 @@ %ieimm 6:5 0:5 @typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=3D%ieimm =20 +@type_msr ...... rd:5 ...... imm:15 &type_msr + ### =20 add 000000 ..... ..... ..... 000 0000 0000 @typea @@ -176,6 +179,9 @@ lwi 111010 ..... ..... ................ = @typeb =20 mbar 101110 imm:5 00010 0000 0000 0000 0100 =20 +msrclr 100101 ..... 100010 ............... @type_msr +msrset 100101 ..... 100000 ............... @type_msr + mul 010000 ..... ..... ..... 000 0000 0000 @typea mulh 010000 ..... ..... ..... 000 0000 0001 @typea mulhu 010000 ..... ..... ..... 000 0000 0011 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 71ceabfffd..e05523bd5b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1338,16 +1338,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } =20 +static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) +{ + uint32_t imm =3D arg->imm; + + if (trap_userspace(dc, imm !=3D MSR_C)) { + return true; + } + + if (arg->rd) { + msr_read(dc, cpu_R[arg->rd]); + } + + /* + * Handle the carry bit separately. + * This is the only bit that userspace can modify. + */ + if (imm & MSR_C) { + tcg_gen_movi_i32(cpu_msr_c, set); + } + + /* + * MSR_C and MSR_CC set above. + * MSR_PVR is not writable, and is always clear. + */ + imm &=3D ~(MSR_C | MSR_CC | MSR_PVR); + + if (imm !=3D 0) { + if (set) { + tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); + } else { + tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); + } + dc->cpustate_changed =3D 1; + } + return true; +} + +static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, false); +} + +static bool trans_msrset(DisasContext *dc, arg_type_msr *arg) +{ + return do_msrclrset(dc, arg, true); +} + static void dec_msr(DisasContext *dc) { CPUState *cs =3D CPU(dc->cpu); - TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset, extended =3D false; + bool to, extended =3D false; =20 sr =3D extract32(dc->imm, 0, 14); to =3D extract32(dc->imm, 14, 1); - clrset =3D extract32(dc->imm, 15, 1) =3D=3D 0; dc->type_b =3D 1; if (to) { dc->cpustate_changed =3D 1; @@ -1361,40 +1406,6 @@ static void dec_msr(DisasContext *dc) extended =3D extract32(dc->imm, e_bit[to], 1); } =20 - /* msrclr and msrset. */ - if (clrset) { - bool clr =3D extract32(dc->ir, 16, 1); - - if (!dc->cpu->cfg.use_msr_instr) { - /* nop??? */ - return; - } - - if (trap_userspace(dc, dc->imm !=3D 4 && dc->imm !=3D 0)) { - return; - } - - if (dc->rd) - msr_read(dc, cpu_R[dc->rd]); - - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); - msr_read(dc, t0); - tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); - - if (clr) { - tcg_gen_not_i32(t1, t1); - tcg_gen_and_i32(t0, t0, t1); - } else - tcg_gen_or_i32(t0, t0, t1); - msr_write(dc, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); - dc->base.is_jmp =3D DISAS_UPDATE; - return; - } - if (trap_userspace(dc, to)) { return; } --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598390827; cv=none; d=zohomail.com; s=zohoarc; b=jCiHS9Pra/L3YBg1XMoGO81AwsyS4BOffRcNUXqObvT1+gUQER8YPkYVcbG0SR+pltXQqoJDKHTJYbz6OGL2hQ2ArUMVFli8mTuSR1agePMAY+ZPXgJ44Ps6iao7X2N4GuLTLMfeNy4gWYsZ21qq9EClqt3IgIcokM8yf49IaOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598390827; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m6fh136WeDEV1UTM3Bn7M1wdgMRKLLNiRWtU8qzbrz8=; b=J68NS+GparVlPSRNLM/jX5U4z5oMYMXNr1POSvRCJPAkloQvtKVA0cviRfYtLEaMfS8wsyMuqPDHqAam/Wh5smL+iSJ5rB/10l3IHxLjuMoi123nLfCBFgDa8MzKv/hOcRGGAxliFdOgNU8qYJZb5lgR4ZoURNMzHcjNkIVzuHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598390826939497.667302524654; Tue, 25 Aug 2020 14:27:06 -0700 (PDT) Received: from localhost ([::1]:38652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgTB-0001y5-I2 for importer@patchew.org; Tue, 25 Aug 2020 17:27:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4S-0000jj-Sm for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:35 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4P-00024g-9e for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:32 -0400 Received: by mail-pf1-x442.google.com with SMTP id m71so8311719pfd.1 for ; Tue, 25 Aug 2020 14:01:28 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m6fh136WeDEV1UTM3Bn7M1wdgMRKLLNiRWtU8qzbrz8=; b=oDega+RGE2GGEM+RjL2arhqkeqkZOTbsjRg/L69FVRHuW3GHASiiIWCPPnNdicBUUj gEdrxBCCM6woVZfIN/viYTwXkzDno4SfH+5gYvvaPGWiiW5wLWuVUviO+BiAs9J4BLve Z0RKRUO/BmWXtxWWvCvSpLRi4b0HcWmdQyLKwht6PSitZ/rF/1NnOZoNXFUE71VOyl74 b+ba5WvYkJxFePb91le6HdC1SxonoTMiVNnP76gy/nB4O51RKX4KsiC9j06e0cgv498U G9e68q+MVZEDwQiYiH8iLi33jAzZB4/4+ZKbXsICqkDE0mnjZGpqr9+ng1KrVmXV/Mw4 R+8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m6fh136WeDEV1UTM3Bn7M1wdgMRKLLNiRWtU8qzbrz8=; b=knwgvNG9Sdkx1txnAO7Cm1hy2N4ezfs+b87pzH8xk/iEZeDKeMRL28jjp+mCF/27tp sUNe2SaOyzoukZrgDDLNW709m5ca7TeprFuAM2YS07dQVMg5V0eeG4CG0iVTECzq6z7I pMjpq2+sRvT8Mw+oRdsdVvFM72XkWvZgDTG4CxM76FNkXgFv1eWIJJZ6eh6ZlWc7KooB /LdmgPbypljVD9VCxpxpe9rUgJp94i8BkmDRkm/gl0hsevu7AVYABqwe+uHm+DlI/i1I OrEMPbujjp8NjzdQXvfuR2ITR7r9QvNRBAIjOXG0vGJjpbB/Wc45aaCfk3qX37mG+AV+ 7kZg== X-Gm-Message-State: AOAM533VhqTMd4NvMnqDVOM/5H5B501sOAFNZ2aOfNuldDZC4Rf2s8/M 2IkiaKIHbMSrzMtuunfTZq6PU5gdeokM9g== X-Google-Smtp-Source: ABdhPJxC2zZYgQKA4g+d/dXgn/Gp9p7dURq4zbNf2u9PgNZKb4Hyao8eKprFmLziDX2XgMZ3VsHrHQ== X-Received: by 2002:a63:df01:: with SMTP id u1mr7427865pgg.401.1598389287208; Tue, 25 Aug 2020 14:01:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 72/77] target/microblaze: Convert dec_msr to decodetree Date: Tue, 25 Aug 2020 13:59:45 -0700 Message-Id: <20200825205950.730499-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 + target/microblaze/translate.c | 270 +++++++++++++++++---------------- 2 files changed, 139 insertions(+), 134 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index e80283cce6..48c60082e0 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -179,6 +179,9 @@ lwi 111010 ..... ..... ................ = @typeb =20 mbar 101110 imm:5 00010 0000 0000 0000 0100 =20 +mfs 100101 rd:5 0 e:1 000 10 rs:14 +mts 100101 0 e:1 000 ra:5 11 rs:14 + msrclr 100101 ..... 100010 ............... @type_msr msrset 100101 ..... 100000 ............... @type_msr =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e05523bd5b..e9e4a0e1db 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1327,6 +1327,7 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) tcg_temp_free_i32(t); } =20 +#ifndef CONFIG_USER_ONLY static void msr_write(DisasContext *dc, TCGv_i32 v) { dc->cpustate_changed =3D 1; @@ -1337,6 +1338,7 @@ static void msr_write(DisasContext *dc, TCGv_i32 v) /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clea= r. */ tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); } +#endif =20 static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) { @@ -1385,151 +1387,152 @@ static bool trans_msrset(DisasContext *dc, arg_ty= pe_msr *arg) return do_msrclrset(dc, arg, true); } =20 -static void dec_msr(DisasContext *dc) +static bool trans_mts(DisasContext *dc, arg_mts *arg) { - CPUState *cs =3D CPU(dc->cpu); - unsigned int sr, rn; - bool to, extended =3D false; - - sr =3D extract32(dc->imm, 0, 14); - to =3D extract32(dc->imm, 14, 1); - dc->type_b =3D 1; - if (to) { - dc->cpustate_changed =3D 1; + if (trap_userspace(dc, true)) { + return true; } =20 - /* Extended MSRs are only available if addr_size > 32. */ - if (dc->cpu->cfg.addr_size > 32) { - /* The E-bit is encoded differently for To/From MSR. */ - static const unsigned int e_bit[] =3D { 19, 24 }; - - extended =3D extract32(dc->imm, e_bit[to], 1); +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + if (arg->e && arg->rs !=3D 0x1003) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mts reg 0x%x\n", arg->rs); + return true; } =20 - if (trap_userspace(dc, to)) { - return; - } + TCGv_i32 src =3D reg_for_read(dc, arg->ra); + switch (arg->rs) { + case SR_MSR: + msr_write(dc, src); + break; + case SR_FSR: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); + break; + case 0x800: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); + break; =20 -#if !defined(CONFIG_USER_ONLY) - /* Catch read/writes to the mmu block. */ - if ((sr & ~0xff) =3D=3D 0x1000) { - TCGv_i32 tmp_ext =3D tcg_const_i32(extended); - TCGv_i32 tmp_sr; + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext =3D tcg_const_i32(arg->e); + TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7); =20 - sr &=3D 7; - tmp_sr =3D tcg_const_i32(sr); - if (to) { - gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); - } else { - gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); + gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); } - tcg_temp_free_i32(tmp_sr); - tcg_temp_free_i32(tmp_ext); - return; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); + return true; } + dc->cpustate_changed =3D 1; + return true; +#endif +} + +static bool trans_mfs(DisasContext *dc, arg_mfs *arg) +{ + TCGv_i32 dest =3D reg_for_write(dc, arg->rd); + + if (arg->e) { + switch (arg->rs) { + case SR_EAR: + { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrh_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + return true; +#ifndef CONFIG_USER_ONLY + case 0x1003: /* TLBLO */ + /* Handled below. */ + break; +#endif + case 0x2006 ... 0x2009: + /* High bits of PVR6-9 not implemented. */ + tcg_gen_movi_i32(dest, 0); + return true; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid extended mfs reg 0x%x\n", arg->rs); + return true; + } + } + + switch (arg->rs) { + case SR_PC: + tcg_gen_movi_i32(dest, dc->base.pc_next); + break; + case SR_MSR: + msr_read(dc, dest); + break; + case SR_EAR: + { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_extrl_i64_i32(dest, t64); + tcg_temp_free_i64(t64); + } + break; + case SR_ESR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); + break; + case SR_FSR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); + break; + case SR_BTR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); + break; + case SR_EDR: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); + break; + case 0x800: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); + break; + case 0x802: + tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); + break; + +#ifndef CONFIG_USER_ONLY + case 0x1000: /* PID */ + case 0x1001: /* ZPR */ + case 0x1002: /* TLBX */ + case 0x1003: /* TLBLO */ + case 0x1004: /* TLBHI */ + case 0x1005: /* TLBSX */ + { + TCGv_i32 tmp_ext =3D tcg_const_i32(arg->e); + TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7); + + gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); + tcg_temp_free_i32(tmp_reg); + tcg_temp_free_i32(tmp_ext); + } + break; #endif =20 - if (to) { - switch (sr) { - case SR_PC: - break; - case SR_MSR: - msr_write(dc, cpu_R[dc->ra]); - break; - case SR_EAR: - { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); - tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)= ); - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_st_i32(cpu_R[dc->ra], - cpu_env, offsetof(CPUMBState, shr)); - break; - default: - cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); - break; - } - } else { - switch (sr) { - case SR_PC: - tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); - break; - case SR_MSR: - msr_read(dc, cpu_R[dc->rd]); - break; - case SR_EAR: - { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)= ); - if (extended) { - tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); - } else { - tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); - } - tcg_temp_free_i64(t64); - } - break; - case SR_ESR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, esr)); - break; - case SR_FSR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, fsr)); - break; - case SR_BTR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, btr)); - break; - case SR_EDR: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, edr)); - break; - case 0x800: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, slr)); - break; - case 0x802: - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, shr)); - break; - case 0x2000 ... 0x200c: - rn =3D sr & 0xf; - tcg_gen_ld_i32(cpu_R[dc->rd], - cpu_env, offsetof(CPUMBState, pvr.regs[rn])); - break; - default: - cpu_abort(cs, "unknown mfs reg %x\n", sr); - break; - } - } - - if (dc->rd =3D=3D 0) { - tcg_gen_movi_i32(cpu_R[0], 0); + case 0x2000 ... 0x200c: + tcg_gen_ld_i32(dest, cpu_env, + offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000])); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs); + break; } + return true; } =20 static void do_rti(DisasContext *dc) @@ -1620,7 +1623,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 ++++ target/microblaze/translate.c | 64 ++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 15 deletions(-) diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index 48c60082e0..79d32c826c 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -156,6 +156,9 @@ flt 010110 ..... ..... ----- 0101 000 0000 = @typea0 fint 010110 ..... ..... ----- 0110 000 0000 @typea0 fsqrt 010110 ..... ..... 00000 0111 000 0000 @typea0 =20 +get 011011 rd:5 00000 0 ctrl:5 000000 imm:4 +getd 010011 rd:5 00000 rb:5 0 ctrl:5 00000 + idiv 010010 ..... ..... ..... 000 0000 0000 @typea idivu 010010 ..... ..... ..... 000 0000 0010 @typea =20 @@ -198,6 +201,9 @@ pcmpbf 100000 ..... ..... ..... 100 0000 0000 = @typea pcmpeq 100010 ..... ..... ..... 100 0000 0000 @typea pcmpne 100011 ..... ..... ..... 100 0000 0000 @typea =20 +put 011011 00000 ra:5 1 ctrl:5 000000 imm:4 +putd 010011 00000 ra:5 rb:5 1 ctrl:5 00000 + rsub 000001 ..... ..... ..... 000 0000 0000 @typea rsubc 000011 ..... ..... ..... 000 0000 0000 @typea rsubk 000101 ..... ..... ..... 000 0000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e9e4a0e1db..0a05b49f8e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1587,33 +1587,68 @@ static void dec_null(DisasContext *dc) } =20 /* Insns connected to FSL or AXI stream attached devices. */ -static void dec_stream(DisasContext *dc) +static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { TCGv_i32 t_id, t_ctrl; - int ctrl; =20 if (trap_userspace(dc, true)) { - return; + return true; } =20 t_id =3D tcg_temp_new_i32(); - if (dc->type_b) { - tcg_gen_movi_i32(t_id, dc->imm & 0xf); - ctrl =3D dc->imm >> 10; + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); } else { - tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); - ctrl =3D dc->imm >> 5; + tcg_gen_movi_i32(t_id, imm); } =20 t_ctrl =3D tcg_const_i32(ctrl); - - if (dc->rd =3D=3D 0) { - gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); - } else { - gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); - } + gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl); tcg_temp_free_i32(t_id); tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_get(DisasContext *dc, arg_get *arg) +{ + return do_get(dc, arg->rd, 0, arg->imm, arg->ctrl); +} + +static bool trans_getd(DisasContext *dc, arg_getd *arg) +{ + return do_get(dc, arg->rd, arg->rb, 0, arg->ctrl); +} + +static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl) +{ + TCGv_i32 t_id, t_ctrl; + + if (trap_userspace(dc, true)) { + return true; + } + + t_id =3D tcg_temp_new_i32(); + if (rb) { + tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); + } else { + tcg_gen_movi_i32(t_id, imm); + } + + t_ctrl =3D tcg_const_i32(ctrl); + gen_helper_get(t_id, t_ctrl, reg_for_read(dc, ra)); + tcg_temp_free_i32(t_id); + tcg_temp_free_i32(t_ctrl); + return true; +} + +static bool trans_put(DisasContext *dc, arg_put *arg) +{ + return do_put(dc, arg->ra, 0, arg->imm, arg->ctrl); +} + +static bool trans_putd(DisasContext *dc, arg_putd *arg) +{ + return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } =20 static struct decoder_info { @@ -1623,7 +1658,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] =3D { - {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} }; =20 --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Om47t/eP4gknkyo+HoA7eqvwr7+ry/2ZpY7FF2j9M9k=; b=wbt2pVqfzcx/yEJcPfUr7wXoUuRwRp65tJVp3Bh5YpOzdox+btB1XquC3/EvxOwlDX NR6Nia4p0VVUh7kqAkEBOyt8mS50lvx3uJUp/BNQeLVM4GD/LdyVQcfrir9InBjMBr77 RK+s0MUFnnMzrQOK9f5kNlL/qGz+2UkaXfb6qHRvInbvxkDU3hAGumYx733y65XaXont l0IuDwAbCnFm6xwI9ubgjCmZ3GBEFYt0SmWOZCFE8w9YmDZZ7V6XxpXy0589hm7ra6Ab WHAPaMa1ZpehVIQjcbVqdbCqKd7tRiyKvmbuyJMX5CSG6CIYGSqiMzHzWr/RYIIUYcDx x5mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Om47t/eP4gknkyo+HoA7eqvwr7+ry/2ZpY7FF2j9M9k=; b=HipgzBC+KkS2bf3E/yAmIv+BevX6hBv9sK6f8OcxJFPq0YyVOntcLThTPmlK5IgsjK eBDdFQ14uPx6D7NtyVNosvv5UDVa8hmCfCWT8VY1vOvHumEK7tDzlbIkBhxBoNSjIVGI HVf8I9zDomHArog9qcSZ0evptEFQn7d0AlHn+H8/g5nfzu+qR3AyEp4f/iU5sZ9xj8Ot N/9VxAp78pvC4+FLBCU1NcCTzoutf6B8Q0DbglsxsvGK7y9+Nb8zAH1S3TYzXFI1I7za t3r4qMdmwovT+kGT6w5QtpRgPsO2WyFrWAplEBVUqkmNDip3Bm4dvX0rNI0DmWvrvYLB /cew== X-Gm-Message-State: AOAM532FP1zhtuLMPDh0f00rUugFF3WKzoa6feM8C2Drgf9tJ3rYH2Dl BVDyNt/zD4xSzf1zRO6xHZFXLYer30qxFw== X-Google-Smtp-Source: ABdhPJyIRT+9d7HpW7VwkIYLYss18PiEGqQLj302nZZFwgTvwwaIq1e5/6FfSE4BzonYkojxmg+xzA== X-Received: by 2002:a62:5543:: with SMTP id j64mr1768353pfb.45.1598389289343; Tue, 25 Aug 2020 14:01:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 74/77] target/microblaze: Remove last of old decoder Date: Tue, 25 Aug 2020 13:59:47 -0700 Message-Id: <20200825205950.730499-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 75 +---------------------------------- 1 file changed, 2 insertions(+), 73 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0a05b49f8e..2df22e8c2a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -65,13 +65,7 @@ typedef struct DisasContext { bool r0_set; =20 /* Decoder. */ - int type_b; - uint32_t ir; uint32_t ext_imm; - uint8_t opcode; - uint8_t rd, ra, rb; - uint16_t imm; - unsigned int cpustate_changed; unsigned int tb_flags; unsigned int tb_flags_to_set; @@ -184,21 +178,6 @@ static bool trap_userspace(DisasContext *dc, bool cond) return cond_user; } =20 -static int32_t dec_alu_typeb_imm(DisasContext *dc) -{ - tcg_debug_assert(dc->type_b); - return typeb_imm(dc, (int16_t)dc->imm); -} - -static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) -{ - if (dc->type_b) { - tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); - return &cpu_imm; - } - return &cpu_R[dc->rb]; -} - static TCGv_i32 reg_for_read(DisasContext *dc, int reg) { if (likely(reg !=3D 0)) { @@ -1094,7 +1073,7 @@ static bool setup_dslot(DisasContext *dc) } =20 dc->tb_flags_to_set |=3D D_FLAG; - if (dc->type_b && (dc->tb_flags & IMM_FLAG)) { + if (dc->tb_flags & IMM_FLAG) { dc->tb_flags_to_set |=3D BIMM_FLAG; } return false; @@ -1576,16 +1555,6 @@ static void do_rte(DisasContext *dc) dc->tb_flags &=3D ~DRTE_FLAG; } =20 -static void dec_null(DisasContext *dc) -{ - if (trap_illegal(dc, true)) { - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=3D%x opc=3D%x\n", - (uint32_t)dc->base.pc_next, dc->opcode); - dc->abort_at_next_insn =3D 1; -} - /* Insns connected to FSL or AXI stream attached devices. */ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl) { @@ -1651,46 +1620,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *a= rg) return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl); } =20 -static struct decoder_info { - struct { - uint32_t bits; - uint32_t mask; - }; - void (*dec)(DisasContext *dc); -} decinfo[] =3D { - {{0, 0}, dec_null} -}; - -static void old_decode(DisasContext *dc, uint32_t ir) -{ - int i; - - dc->ir =3D ir; - - if (ir =3D=3D 0) { - trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); - /* Don't decode nop/zero instructions any further. */ - return; - } - - /* bit 2 seems to indicate insn type. */ - dc->type_b =3D ir & (1 << 29); - - dc->opcode =3D EXTRACT_FIELD(ir, 26, 31); - dc->rd =3D EXTRACT_FIELD(ir, 21, 25); - dc->ra =3D EXTRACT_FIELD(ir, 16, 20); - dc->rb =3D EXTRACT_FIELD(ir, 11, 15); - dc->imm =3D EXTRACT_FIELD(ir, 0, 15); - - /* Large switch for all insns. */ - for (i =3D 0; i < ARRAY_SIZE(decinfo); i++) { - if ((dc->opcode & decinfo[i].mask) =3D=3D decinfo[i].bits) { - decinfo[i].dec(dc); - break; - } - } -} - static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); @@ -1757,7 +1686,7 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 ir =3D cpu_ldl_code(env, dc->base.pc_next); if (!decode(dc, ir)) { - old_decode(dc, ir); + trap_illegal(dc, true); } =20 if (dc->r0) { --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598392206; cv=none; d=zohomail.com; s=zohoarc; b=SBpmLdlyxACZtmV+y73mhLnY2aghADGR5rxOsC5qGuRpeZNxo9hSakNPdoBgTuMrzmHtq4xaO2CgbwGJs6QOqi2LM7y4d4uZ2mqsqtr5C6DacWsN+FWCiDV28Da1Q3MUywbnackuCaiuTT25fojWDYyXF6RvJ3pfCFdNZ+9nSJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598392206; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XYFF+nRDeDk80M21qSEoaFQq0JFdLsE3apwlxbKB9OI=; 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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XYFF+nRDeDk80M21qSEoaFQq0JFdLsE3apwlxbKB9OI=; b=Gz82VMtPCylrr8JFVL1kGAtjMTu69kceqQ4FTzs2dJP3TU6qcK7Im7ifVq3yorhbvu 31ckriXBTjR37pcZicbjrdPk16p5KdoRI8wi3F4TVdQ7zo8paYt+SDKNAso/tiX8Mm3z 2N87IZXOdai+oavqYjD0Ejj3afyS65kb7o/QWmzz4SKq7kNy0KrKUoznXUZjhOPRKX5R zfBpzz41BP/PsRMPYPj8IjCVfsfHvO7U9DtczzDuczJ/eUVKS7DTx8qCoIa2oLXBOqtK 9LA/9rjZpEGdZAKGephIjdyJcBihrjHaBllfItLSWTTgte6tEbNLIJybcGOOQ0KFV7/2 qkkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XYFF+nRDeDk80M21qSEoaFQq0JFdLsE3apwlxbKB9OI=; b=ZVW2wVdldodynm+xAPcSS672fgRDS1LNX1Rjgf5kadh6FxppGm/DIxTkHJxLt8Up+r KAKBTsmmL5rhLYcVNWzBCvRBFl920GeOAArVOdC6qS9E1mhQOAfka/rvvFlSapF6XxTl Y/32uAxbes7s43OFIzOX2Cp7u7LCq8kUxo/xAUvmeUOlAs8hQWo77SavhvTilE+4MCrW pdFFBkFpOQMFKMWuloYaQThgX3O6KmFJjl7IumxAicE9IBjixX5/V1iA7CI+uRSiBhxA 7TB1suEhDijy1z/Kr3kvdbL0RpvFDisK4wc2YT3Tw3vrScn4D4TE+N1kZJnmDBd/FSr6 OWXQ== X-Gm-Message-State: AOAM533PinB90C8qMPltSaLooWD0rYNjBmbN7MQsp+mBPBSNw7yRoREf p3JpxybBsJHOEJTg72EJWgkkLsyKa4d68A== X-Google-Smtp-Source: ABdhPJwken8sRhLjmqROkJlkkNI2rwlNWIQir6xjuse2SKvOH4i0WqHDZvreqS1L/HK/h6ShLL0low== X-Received: by 2002:aa7:9467:: with SMTP id t7mr9245560pfq.64.1598389290523; Tue, 25 Aug 2020 14:01:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 75/77] target/microblaze: Remove cpu_R[0] Date: Tue, 25 Aug 2020 13:59:48 -0700 Message-Id: <20200825205950.730499-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Do not initialize cpu_R[0], as this should be totally unused. The cpu_for_read and cpu_for_write functions use a local temp. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2df22e8c2a..c8eb68ce4b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1875,7 +1875,13 @@ void mb_tcg_init(void) static const struct { TCGv_i32 *var; int ofs; char name[8]; } i32s[] =3D { - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), + /* + * Note that r0 is handled specially in reg_for_read + * and reg_for_write. Nothing should touch cpu_R[0]. + * Leave that element NULL, which will assert quickly + * inside the tcg generator functions. + */ + R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598391793; cv=none; d=zohomail.com; s=zohoarc; b=JUogOA5HwzFY4rbXaLuZjXgzKbHcgEaYtnkuTCNA8FYwY+T5oq3sDUJDAhs2yj3V/iJ61pxI7QdLYn/JdgsGNIJLbLCZ1+b8LNzGwIfm6OMbVGJN+PlCNg07vtsRmUx435p0/wwf9HP9dsbFUU1O5AWxz+/ORrDW4i49Y/D8HTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598391793; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=HtQXZIojZWeawOBI5aAD/tNYHKfwmwfWUEVHyyUIR6TnNmpi9bnxbOVTN0r4UDZwJ3FTfy8CIrlzEGUMlMQhN+DIMju6Bg/4QPwkbRTMi2IdYo9dpsrzMBDKp0umnIEFLsQVhNfrXSLEUWRdhdZm2qw2w7Dc3fJc3Drs+/MJzQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598391793584533.7740687752745; Tue, 25 Aug 2020 14:43:13 -0700 (PDT) Received: from localhost ([::1]:47294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgim-0003Vi-9i for importer@patchew.org; Tue, 25 Aug 2020 17:43:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4a-0000mK-9x for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:40 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:44061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4U-00025G-DD for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:38 -0400 Received: by mail-pf1-x441.google.com with SMTP id p11so5119538pfn.11 for ; Tue, 25 Aug 2020 14:01:33 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=D4ZrkdnaxpNIEXYGaEYEQO2PUhsKUhwAPDSR1eUtbNKdlXq3cYhDWDjB03coFV45Ry fyI7EkdqoqK6xUU+Q5KSU//B0Xk+IH5oWKr+zJNXyA96k0bU2QtU0hVxQMR62/X9VDe/ S5AiiHfBzlgvim8oDvTDmgXWzKZlJzlLaa8vM2UFw3EPR5Yk5/lNcx2PYYeu05ZAwd1S ENF+QdsMzAPB8zWMnFzyn/KL9q1dEzabasYoI69bgNwKe9SXiLohYWLvCmEC3Q08N+YK Lm3K5xyp2M8LHsT4bjrjM+7y8y86IzLQWK1JksaTPa8QcnX6Z/+fwjO64JDBGvbZ3EpG WwfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/v81xo2Oa10INQECM2V7ceku/8UgY141rA25N+r+rLA=; b=j3NLPs7TSbs3KY2p3EuI7j4Pu0CmFhp2vxLYMJ5Dyo4g4n07MvryrGGGqJgwuR4e6y DdTjaxv4zN2jeC+wWl2RN6ZSdfYC9JTCdtnzdo4VFgdey20WSgLsk5iTHqgs0a7JgtdH c6vecGe8zTx6ZWpVGMM3F4NHtOufxnEUETvxB+Cig4pwvor/NbAj3NeHn2BUdp16ObJI dLxZPH3hggl8QipX8OzDN/3s1h050khpFQGk+Q++na+7hiGSnhOpx19Qe6quck3lb15n ZqoxmiJGR+yih8fwhEuWZhGB9EZEPT+7leU8//cCJek2hkxWvch7jBCa90LmjoRSX0Te J22w== X-Gm-Message-State: AOAM531hT0VvyWed7uqvSK6l26A9qSy2i+TCMzyGeIJpEZoO+caZeWLL 6SGUHrDmthGUlUs++4r65JY+ARwXfNp+9Q== X-Google-Smtp-Source: ABdhPJyEypa2GPtIaZR15xxg3c45j3PzdwH6MHCIdh4Tby8ITk/T1vH8gACo6S6y5hoRZi/W5DsT5g== X-Received: by 2002:aa7:9552:: with SMTP id w18mr9378716pfq.150.1598389291895; Tue, 25 Aug 2020 14:01:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 76/77] target/microblaze: Add flags markup to some helpers Date: Tue, 25 Aug 2020 13:59:49 -0700 Message-Id: <20200825205950.730499-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The mmu_read, mmu_write, get, and put helpers do not touch the general registers, or any of the other variables managed by tcg. Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index 3980fba797..f740835fcb 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -21,11 +21,11 @@ DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i= 32, i32) =20 DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_3(mmu_read, i32, env, i32, i32) -DEF_HELPER_4(mmu_write, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32) #endif =20 DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl) =20 -DEF_HELPER_2(get, i32, i32, i32) -DEF_HELPER_3(put, void, i32, i32, i32) +DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32) +DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32) --=20 2.25.1 From nobody Sat May 18 21:00:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598392302; cv=none; d=zohomail.com; s=zohoarc; b=aaU3fZKUnU2a8td1K/HrEWgGJRlZSSOTAo7+crMDKbpTkIzHWnv3mOri2JwLy9WWXeQ5SKlISUwzHVfVWn7EU+rVBOQxlJHUGzug1TIICRFubwKY97hDHPTm2aSNR7JpzvwXKCw+6eZ8pgpB+mmVrSKlJtcunaAEJulg10b8q70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598392302; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eRFId6Ea30idq3xTokmsUXGS84tzittdNxqSsVZitX8=; b=StxQH8q25FCa8Ohd8sK5BiUUXffjmHvfyeZkILkU7yvXTzJ11l+ucULMZMd1YWiUtT1TPE+z3F4fLrneK5RymVeWKHe9q2Aj06a4c1aaG1hSVg/7Zdd72xPZfirNE3Fr4FgDgilP7xDB6O17FyS4SC4GjoXMZz1kMSSo+zF5o2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598392302801770.0912540432496; Tue, 25 Aug 2020 14:51:42 -0700 (PDT) Received: from localhost ([::1]:49128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kAgqz-0007vx-I2 for importer@patchew.org; Tue, 25 Aug 2020 17:51:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kAg4d-0000oY-1S for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:43 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42065) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kAg4W-00025R-6L for qemu-devel@nongnu.org; Tue, 25 Aug 2020 17:01:42 -0400 Received: by mail-pg1-x541.google.com with SMTP id g1so3880065pgm.9 for ; Tue, 25 Aug 2020 14:01:34 -0700 (PDT) Received: from localhost.localdomain (h216-228-167-147.bendor.dedicated.static.tds.net. [216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:01:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eRFId6Ea30idq3xTokmsUXGS84tzittdNxqSsVZitX8=; b=hdRjDgcno0OirncUMcHJAnRPkR3YeSHpTh2F09VLXqs55CknCdga0pBvuecQGQe9Y4 gwSmjYMMSBKGlMXXVK6LGR6w2eK6KYN0yFXVEmxgqZ6oEr6h/CvqxTuU0FQHa72c0H/F JRLSEE7tB5FEDkZ6UY4iJaRDxJC7+s5zb4tsGPktqJ0B2YCbWuxCG9h8Ykb3dd+560E0 lW+x1zDodctOGvPjNLwToN7Y/BZ/aKif2FHL6KNH12dr3Jq7S3yj97Y9SKSdvM2Py3gF AEAg9X89o+uOo4aUjQ3LkgrSlGyy+gJwQK1fs8J+V/2i3hqpYS77jrTb9rvPOB5OuH1O WZlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eRFId6Ea30idq3xTokmsUXGS84tzittdNxqSsVZitX8=; b=HlZy5KnWjEbSL+heyuHJaW7XEAGa74C8Oa8pzZXf95TGzY/hXmJsDFTL5l07wcJWoj o7KY8fWvX0RlaidFwqvWQP1m2izGlQkZdbclE3m8nYuGnNDZ6NJL0dd0PLL2NJGX6yOM qKmp6Oe4dg7+kOWaQErNRxotrnARtq2tyUedqhHp4knsxwv8X5exAUQ6b2K+oQdgsdXg 7GrO5e91sc4DF9FRBeIiyhG0V6UB9/lYC8wH3PRTxUOvZMYleXdkSq5zOjEFdfL/Vu/W CNScD5fPx1UJRSALeGpOrLzzX12RRiJZgkgmQgpzeMZOQy6cl4MBjcH4INBRlb2Rzi8t 06fg== X-Gm-Message-State: AOAM5328yqZVcNp9miVFth93Eshah2yxEeCcZaUK4dbrj7RjZdIStQex fqWQy0IFyqPyv1ZNjYvPtkNtUESYSZ8S/Q== X-Google-Smtp-Source: ABdhPJx/GjAr1juaBrwEGhxlqKkSB23AfC5R8fiJyPoyNFVF3XbVkBc3zu5qu/4jIoO4t7WjJsZWhQ== X-Received: by 2002:a63:5459:: with SMTP id e25mr5423045pgm.155.1598389293373; Tue, 25 Aug 2020 14:01:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 77/77] target/microblaze: Reduce linux-user address space to 32-bit Date: Tue, 25 Aug 2020 13:59:50 -0700 Message-Id: <20200825205950.730499-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 15 +++++++++++++++ target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/translate.c | 28 +++++++++++++++++++++++++++- 4 files changed, 45 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 4abbc62d50..4d8297fa94 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -8,9 +8,24 @@ #ifndef MICROBLAZE_CPU_PARAM_H #define MICROBLAZE_CPU_PARAM_H 1 =20 +/* + * While system mode can address up to 64 bits of address space, + * this is done via the lea/sea instructions, which are system-only + * (as they also bypass the mmu). + * + * We can improve the user-only experience by only exposing 32 bits + * of address space. + */ +#ifdef CONFIG_USER_ONLY +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 4298f242a6..d11b6fa995 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint32_t pc; uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ - uint64_t ear; + target_ulong ear; uint32_t esr; uint32_t fsr; uint32_t btr; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 1667822fb7..48547385b0 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -303,8 +303,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr add= r, iflags =3D cpu->env.iflags; =20 qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=3D" TARGET_FMT_lx - " pc=3D%x iflags=3D%x\n", addr, cpu->env.pc, iflags); + "Unaligned access addr=3D" TARGET_FMT_lx " pc=3D%x iflag= s=3D%x\n", + (target_ulong)addr, cpu->env.pc, iflags); =20 esr =3D ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c8eb68ce4b..f6e16b7f5a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -729,6 +729,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, i= nt ra, int imm) return ret; } =20 +#ifndef CONFIG_USER_ONLY static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size =3D dc->cpu->cfg.addr_size; @@ -754,6 +755,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int = ra, int rb) } return ret; } +#endif =20 static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) @@ -818,8 +820,12 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *a= rg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_lbui(DisasContext *dc, arg_typeb *arg) @@ -845,8 +851,12 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *a= rg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_lhui(DisasContext *dc, arg_typeb *arg) @@ -872,8 +882,12 @@ static bool trans_lwea(DisasContext *dc, arg_typea *ar= g) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_lwi(DisasContext *dc, arg_typeb *arg) @@ -952,8 +966,12 @@ static bool trans_sbea(DisasContext *dc, arg_typea *ar= g) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_sbi(DisasContext *dc, arg_typeb *arg) @@ -979,8 +997,12 @@ static bool trans_shea(DisasContext *dc, arg_typea *ar= g) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_shi(DisasContext *dc, arg_typeb *arg) @@ -1006,8 +1028,12 @@ static bool trans_swea(DisasContext *dc, arg_typea *= arg) if (trap_userspace(dc, true)) { return true; } +#ifdef CONFIG_USER_ONLY + return true; +#else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); +#endif } =20 static bool trans_swi(DisasContext *dc, arg_typeb *arg) @@ -1851,7 +1877,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) } =20 qemu_fprintf(f, "\nesr=3D0x%04x fsr=3D0x%02x btr=3D0x%08x edr=3D0x%x\n" - "ear=3D0x%016" PRIx64 " slr=3D0x%x shr=3D0x%x\n", + "ear=3D0x" TARGET_FMT_lx " slr=3D0x%x shr=3D0x%x\n", env->esr, env->fsr, env->btr, env->edr, env->ear, env->slr, env->shr); =20 --=20 2.25.1