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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b14sm24499091wrj.93.2020.08.24.07.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 07:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pd01uxw/z+OGFpmWpo0tpfZAh/qZHgIvhk5c35++C1s=; b=I+SE297L0XUSzXiduKOfJSXy6OtZVdpqbwk6m9A8fBTwIo18wOfcSqEZ4CemjrbMHy samsrqj+kROvIeDPhtu5/6ncpxVN8lITAh4Iz17UBhMejGf2oz7LEvCp7nwwmhLK5Hyl ZA8+SBGgHsjXj1jGr8CmBloRzLJqjI9uTNKXDbNm5GsiqCFLLNwgMK7htFC54JV9nTXJ GCWBWO3ods+bVe1TpFseDEFoBE+Cv4bmO1p6dlfx3TpNb+06Dt0sEPWPTZ2wjyXmP1Ny NnyI5SsweE06+Wuvau2is8waQPCRqgcR21EjMEixuf/BY8h4O3iq804eGUqiGdX4s6H/ r/IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pd01uxw/z+OGFpmWpo0tpfZAh/qZHgIvhk5c35++C1s=; b=g6ZE1PbvPoh+sX66D9oj6klUugROq7ePEXXUaB7irNKUde7p07thxATBPHsL3F4uMw jesjrmxI3p/N7kOcoDntGs/VoD8FdFZVZF67856pXlxAR5ynbraYiBZzozd5goFRWyMk HF7BfeSeohZezUYuK16xOubNYnKYMRGjIClkxM6Mhso6xipVZFHLLgUsTaswmbaOCcPh 4cYjaaPZYp3TIbI7hvX0oYegQ2p1yJdOX41XethgPCcFeEJ/GbuhjMXDxGEi+c/FZC2u KZtGA7PnNWLp+kdAJjKIfmI79zbfrUIA0Y9BCwPmL+6mEyQr5+7SA7bVAcY2EB18DTsH WfTQ== X-Gm-Message-State: AOAM531F8cFGRlzTWtbYrdkRuGnjbYi3ilT1gcz2R3xRIE4AEQbVWLZC HafVdwa2EaeeecJHWJY/y6VUYQ== X-Google-Smtp-Source: ABdhPJyGprRtOB+3xH7ptABh0mOi9uA82xHm09a3/UeUepp/CDFj+EJqQW7o+kVCAC3CBConTY4Ejw== X-Received: by 2002:adf:f847:: with SMTP id d7mr5813070wrq.328.1598279400140; Mon, 24 Aug 2020 07:30:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/22] target/arm: Enable FP16 in '-cpu max' Date: Mon, 24 Aug 2020 15:29:34 +0100 Message-Id: <20200824142934.20850-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824142934.20850-1-peter.maydell@linaro.org> References: <20200824142934.20850-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Set the MVFR1 ID register FPHP and SIMDHP fields to indicate that our "-cpu max" has v8.2-FP16. TODO: this patch needs to go at the end of the series. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 10 ++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b382fcd60e..c179e0752da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2143,7 +2143,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dd696183dfb..3c2b3d95993 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -704,12 +704,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ cpu->isar.id_dfr0 =3D u; =20 - /* - * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, - * so do not set MVFR1.FPHP. Strictly speaking this is not legal, - * but it is also not legal to enable SVE without support for FP16, - * and enabling SVE in system mode is more useful in the short ter= m. - */ + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D u; =20 #ifdef CONFIG_USER_ONLY /* For usermode -cpu max we can use a larger and more efficient DCZ --=20 2.20.1