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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the fp16 version of the VFP VRINT* insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.h | 2 + target/arm/vfp-uncond.decode | 6 ++- target/arm/vfp.decode | 3 ++ target/arm/vfp_helper.c | 21 ++++++++ target/arm/translate-vfp.c.inc | 98 +++++++++++++++++++++++++++++++--- 5 files changed, 122 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index eefd1ac2a72..d1315e0ef3e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -242,8 +242,10 @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_3(ror_cc, i32, env, i32, i32) =20 +DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) =20 diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 8ba7b1703e0..9615544623a 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -60,10 +60,12 @@ VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... = @vfp_dnm_s VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 +VRINT 1111 1110 1.11 10 rm:2 .... 1001 01.0 .... \ + vm=3D%vm_sp vd=3D%vd_sp sz=3D1 VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ - vm=3D%vm_sp vd=3D%vd_sp dp=3D0 + vm=3D%vm_sp vd=3D%vd_sp sz=3D2 VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ - vm=3D%vm_dp vd=3D%vd_dp dp=3D1 + vm=3D%vm_dp vd=3D%vd_dp sz=3D3 =20 # VCVT float to int with specified rounding mode; Vd is always single-prec= ision VCVT 1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \ diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index a8f1137be1e..9a79e99f1b0 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -195,12 +195,15 @@ VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 ..= .. \ VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp =20 +VRINTR_hp ---- 1110 1.11 0110 .... 1001 01.0 .... @vfp_dm_ss VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd =20 +VRINTZ_hp ---- 1110 1.11 0110 .... 1001 11.0 .... @vfp_dm_ss VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd =20 +VRINTX_hp ---- 1110 1.11 0111 .... 1001 01.0 .... @vfp_dm_ss VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd =20 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index c88ace3c566..5b8b4219615 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1018,6 +1018,11 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, = float64 c, void *fpstp) } =20 /* ARMv8 round to integral */ +float32 HELPER(rinth_exact)(float32 x, void *fp_status) +{ + return float16_round_to_int(x, fp_status); +} + float32 HELPER(rints_exact)(float32 x, void *fp_status) { return float32_round_to_int(x, fp_status); @@ -1028,6 +1033,22 @@ float64 HELPER(rintd_exact)(float64 x, void *fp_stat= us) return float64_round_to_int(x, fp_status); } =20 +float32 HELPER(rinth)(float32 x, void *fp_status) +{ + int old_flags =3D get_float_exception_flags(fp_status), new_flags; + float32 ret; + + ret =3D float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags =3D get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_stat= us); + } + + return ret; +} + float32 HELPER(rints)(float32 x, void *fp_status) { int old_flags =3D get_float_exception_flags(fp_status), new_flags; diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 869b67b2b93..7ce044fa896 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -341,7 +341,7 @@ static const uint8_t fp_decode_rm[] =3D { static bool trans_VRINT(DisasContext *s, arg_VRINT *a) { uint32_t rd, rm; - bool dp =3D a->dp; + int sz =3D a->sz; TCGv_ptr fpst; TCGv_i32 tcg_rmode; int rounding =3D fp_decode_rm[a->rm]; @@ -350,12 +350,16 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + if (sz =3D=3D 3 && !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (sz =3D=3D 1 && !dc_isar_feature(aa32_fp16_arith, s)) { return false; } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && + if (sz =3D=3D 3 && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vd) & 0x10)) { return false; } @@ -367,12 +371,16 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + if (sz =3D=3D 1) { + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + } else { + fpst =3D fpstatus_ptr(FPST_FPCR); + } =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 - if (dp) { + if (sz =3D=3D 3) { TCGv_i64 tcg_op; TCGv_i64 tcg_res; tcg_op =3D tcg_temp_new_i64(); @@ -388,7 +396,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) tcg_op =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); neon_load_reg32(tcg_op, rm); - gen_helper_rints(tcg_res, tcg_op, fpst); + if (sz =3D=3D 1) { + gen_helper_rinth(tcg_res, tcg_op, fpst); + } else { + gen_helper_rints(tcg_res, tcg_op, fpst); + } neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_op); tcg_temp_free_i32(tcg_res); @@ -2638,6 +2650,29 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return true; } =20 +static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + gen_helper_rinth(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) { TCGv_ptr fpst; @@ -2693,6 +2728,34 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return true; } =20 +static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + TCGv_i32 tcg_rmode; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + tcg_rmode =3D tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_rinth(tmp, tmp, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_i32(tmp); + return true; +} + static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) { TCGv_ptr fpst; @@ -2758,6 +2821,29 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return true; } =20 +static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); + gen_helper_rinth_exact(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) { TCGv_ptr fpst; --=20 2.20.1