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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+IRaKpLNT6dm56V52rlALT3BSN1ENhS7a0LI65DSjGE=; b=nBHVx29WhIEO1OSStttvJRrCnhk7+qtGwwPE7b0SisUnQiZdTkSAVKBBnC4AvGh59V n8NlCAVrE5iLzfgJSMegu3WKn8qd/tbUhZfDg7S3kKpdcSAvQPlZ7YDrNG2vs+/2ZW9S 2yosbs2rfs9Yx0eGS2gfg2ZIOI9BvT/KnckYktKrBZGvt7/iyfsWosJJSBPwa67CXaTj Hza4ZBl0Wi2XEn8hF+HrLQjV8+mkx3nidORJbROgrv9ELEeUPos1pT/ZySVpwpXATdtq tPSgjgnGmrwDVyQsy6nFp/itbRIsdcIab9t6CIH8EvUi/3YSSL/9uWSEiIQQ0sLnptCS z13A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+IRaKpLNT6dm56V52rlALT3BSN1ENhS7a0LI65DSjGE=; b=F7Lk29YQXmXyzgt49uoDZNOi74DYviK9amGhHKcgW1A2NSv5y78V2QtlTIKySBsZ+i 9X1ybmm/EW7o0N9y+KtuO+pExa0gw2EDaGQeTnHMfIFtZHrhQdsVcma8DELz5WmZ0m4t za5Nc8mZj+urzH4FPwt0lORyH3vBJquSWX6hHPoV+/66s1j2iGTMkMYi1AEJYCdHHA2m +VU4v1c8RSxDd5uvtlEm1dh7TLT8+hlSaCm1sTfxejTiYquRMxl9Rkouz2Md9n2TAKZ4 zLMFsfLaWEeZF8ChyYr1ghf8+Wq3Pe9JDGgghOchHdvEV3WlvZ2QQbxri8BCbizZWrkD tYHQ== X-Gm-Message-State: AOAM532CtlzeNdTAIZpuXVCn5yZ3I4cIQdmQPWpiK9j4c8Hp/Gm79pQU ZlaawnecsdHWnJNWNq33meFJIrJacoq2RHJS X-Google-Smtp-Source: ABdhPJzqJeuMWBSgOXTlsRpdhF4GkAIiAbPwN1pqc6q1b/EuIeyrBkDr1Yu5jt0cbq/ti51UpG8RRQ== X-Received: by 2002:adf:b1ca:: with SMTP id r10mr5338101wra.150.1598262503282; Mon, 24 Aug 2020 02:48:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation Date: Mon, 24 Aug 2020 10:47:52 +0100 Message-Id: <20200824094811.15439-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-8-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 4 +++ include/hw/arm/smmu-common.h | 3 +- hw/arm/smmu-common.c | 25 +++++++++++--- hw/arm/smmuv3.c | 64 +++++++++++++++++++++++------------- hw/arm/trace-events | 4 +-- 5 files changed, 69 insertions(+), 31 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 4112394129e..5babf72f7d5 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -298,6 +298,8 @@ enum { /* Command completion notification */ }; =20 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) +#define CMD_NUM(x) extract32((x)->word[0], 12 , 5) +#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) #define CMD_SSV(x) extract32((x)->word[0], 11, 1) #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) @@ -310,6 +312,8 @@ enum { /* Command completion notification */ #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16) #define CMD_RESP(x) extract32((x)->word[2], 11, 2) #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1) +#define CMD_TTL(x) extract32((x)->word[2], 8 , 2) +#define CMD_TG(x) extract32((x)->word[2], 10, 2) #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5) #define CMD_ADDR(x) ({ \ uint64_t high =3D (uint64_t)(x)->word[3]; \ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ece62c36523..4f6acf634cf 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -168,7 +168,8 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t= iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 2922deec6fc..8d89a86699a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -143,15 +143,30 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { return false; } - return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || + ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +inline void +smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl) { - SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; + if (ttl && (num_pages =3D=3D 1)) { + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 - trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); + g_hash_table_remove(s->iotlb, &key); + } else { + /* if tg is not set we use 4KB range invalidation */ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + + SMMUIOTLBPageInvInfo info =3D { + .asid =3D asid, .iova =3D iova, + .mask =3D (num_pages * 1 << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_asid_iova, + &info); + } } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e4a2cea7adc..89ab11fc36a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -785,42 +785,49 @@ epilogue: * @n: notifier to be called * @asid: address space ID or negative value if we don't care * @iova: iova + * @tg: translation granule (if communicated through range invalidation) + * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, - dma_addr_t iova) + int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; - SMMUTransTableInfo *tt; - SMMUTransCfg *cfg; IOMMUTLBEntry entry; + uint8_t granule =3D tg; =20 - cfg =3D smmuv3_get_config(sdev, &event); - if (!cfg) { - return; - } + if (!tg) { + SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; + SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &event); + SMMUTransTableInfo *tt; =20 - if (asid >=3D 0 && cfg->asid !=3D asid) { - return; - } + if (!cfg) { + return; + } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { - return; + if (asid >=3D 0 && cfg->asid !=3D asid) { + return; + } + + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; } =20 entry.target_as =3D &address_space_memory; entry.iova =3D iova; - entry.addr_mask =3D (1 << tt->granule_sz) - 1; + entry.addr_mask =3D num_pages * (1 << granule) - 1; entry.perm =3D IOMMU_NONE; =20 memory_region_notify_one(n, &entry); } =20 -/* invalidate an asid/iova tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova) +/* invalidate an asid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -828,28 +835,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova) IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, + tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova); + smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); } } } =20 static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) { + uint8_t scale =3D 0, num =3D 0, ttl =3D 0; dma_addr_t addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); uint16_t vmid =3D CMD_VMID(cmd); bool leaf =3D CMD_LEAF(cmd); + uint8_t tg =3D CMD_TG(cmd); + hwaddr num_pages =3D 1; int asid =3D -1; =20 + if (tg) { + scale =3D CMD_SCALE(cmd); + num =3D CMD_NUM(cmd); + ttl =3D CMD_TTL(cmd); + num_pages =3D (num + 1) * (1 << (scale)); + } + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); } - trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr); - smmu_iotlb_inv_iova(s, asid, addr); + trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf= ); + smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); } =20 static int smmuv3_cmdq_consume(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c219fe9e828..3d905e0f7d0 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start= =3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid =3D%d asid =3D%d addr=3D0x%"PR= Ix64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) = "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.20.1