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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nnYvgpj+yfRsy7MXb9YbrfpjgfASX8TYRFoNG96nT04=; b=aPZt7m8JkaQvwbTXMevz23ilxf0f13elevH6ENQ0HyhGa4QSrpjGH3rs3/hmTvBnoP peHdLzndhRCsOHq6jw0mhL3Rku0X+K74hT538BkqZIzcSIWHIKv7hG60O1bQLEBpPm7/ k9YOmsHXHrx/WxHDagNlI2UvWkF54wGtMsxy3mL+swUyKIcKsCovGKhU82f1Bfc3+lkt wKmSOccLxYcktp8JHLJi/6OuNgcWKieLUWpCd00opCcyJcPIcmvBXZcpuIJnTLB3zwJO pIbOU9spdoDPb6XIlT+iqAbETejpaLkHo9rj0WHAjEvupyz3Ig4YqR6AaPixFak/sKgJ mKtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nnYvgpj+yfRsy7MXb9YbrfpjgfASX8TYRFoNG96nT04=; b=YIH8s0q8X9zkMaEaW8abB1MXh5QJxtjrpv+9h6BfGzWjj/1sORIuTOMVumd9YVbtUX vinOJpq6n+C+mZTLsSuFzEVlv4TDo2ZDmpCmiYd+91rVf17seCZ8xS0IOgyc+/Zue4To 8aC3cnCawv0MG+JwcWlH4Aa9eo8sIlYF6ZpHbyemkJbkL3W8/OwCLVrngqKO9prdAIpi qw+dwiSQdiKeUErc2/O4s9gkqKQqtyMuC7c4Px2LhmItSjnxeoykpUvvTpeLpjlZey2F 3QMFqMH9H7igagtj8cfE+IV+ce++MpsCo0hZeLOoZv0a+bPka/YwVCii8sBCf38ibqMz PG2w== X-Gm-Message-State: AOAM531AvDCABfynlkuJBFEdycnKTR+m3LvL6FfRYv57UcuugyE1XC3r DLKPjK5SIr4SNYk37Y7QDX7POJWHBaXsu6vB X-Google-Smtp-Source: ABdhPJxHGG/Y4o7bQF12Sih+oJWcyZ97XuTtHHhmNWVQEHJoyrVPoQFjtCwWqPo6T/eOHyfTMcenSA== X-Received: by 2002:a5d:6806:: with SMTP id w6mr3775560wru.395.1598262494827; Mon, 24 Aug 2020 02:48:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Date: Mon, 24 Aug 2020 10:47:45 +0100 Message-Id: <20200824094811.15439-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The 'Cortex-A9MPCore internal peripheral' block can only be used with Cortex A5 and A9 cores. As we don't model the A5 yet, simply check the machine cpu core is a Cortex A9. If not return an error. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20200709152337.15533-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/cpu/a9mpcore.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 351295e5187..ec186d49abd 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#include "cpu.h" =20 #define A9_GIC_NUM_PRIORITY_BITS 5 =20 @@ -52,8 +53,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **= errp) *wdtbusdev; int i; bool has_el3; + CPUState *cpu0; Object *cpuobj; =20 + cpu0 =3D qemu_get_cpu(0); + cpuobj =3D OBJECT(cpu0); + if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9")= )) { + /* We might allow Cortex-A5 once we model it */ + error_setg(errp, + "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"= ); + return; + } + scudev =3D DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -70,7 +81,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **e= rrp) /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - cpuobj =3D OBJECT(qemu_get_cpu(0)); has_el3 =3D object_property_find(cpuobj, "has_el3", NULL) && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); --=20 2.20.1