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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Add the support for AIDR register. It currently advertises SMMU V3.0 spec. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-10-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index ef093eaff50..bd34a4f3300 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -64,6 +64,7 @@ REG32(IDR5, 0x14) #define SMMU_IDR5_OAS 4 =20 REG32(IIDR, 0x18) +REG32(AIDR, 0x1c) REG32(CR0, 0x20) FIELD(CR0, SMMU_ENABLE, 0, 1) FIELD(CR0, EVENTQEN, 2, 1) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 36b2f452539..68d7a963e0f 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -41,6 +41,7 @@ typedef struct SMMUv3State { =20 uint32_t idr[6]; uint32_t iidr; + uint32_t aidr; uint32_t cr[3]; uint32_t cr0ack; uint32_t statusr; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 89ab11fc36a..718f28462ea 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1251,6 +1251,9 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr = offset, case A_IIDR: *data =3D s->iidr; return MEMTX_OK; + case A_AIDR: + *data =3D s->aidr; + return MEMTX_OK; case A_CR0: *data =3D s->cr[0]; return MEMTX_OK; --=20 2.20.1