From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262562; cv=none; d=zohomail.com; s=zohoarc; b=bvg8o9pRJjGvV3jAQKHp23ObJrZkzPjP4hrXNzVSgApVV3LPKGKohXiyXhNceXop34LQODt94UrOfLBx17xPl8h2eH0jUWkYz9YdHLTRmWJBCVU1u+rJibIlJmclGXXhstvrYx80+e6iqlqnD6ANfJrjDBjEZH2I1UuxenbK53k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262562; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nnYvgpj+yfRsy7MXb9YbrfpjgfASX8TYRFoNG96nT04=; b=YZZDRuh8IfG/j9FLDOtnNCnkS37OrTlwefrgovzbot8y7vx72Szzj/T/wnjwjmXJyuUGYpxcyof5dGdEOdbzBG+2veCbOIoUHA6G1Ea/vkZJOkCfem8EDHnJ0wDTMTBoq2WABUwHWmGbznPYIWwZVtIHlnQUQBfIhL/UHz0rC1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262562509738.5831696863031; Mon, 24 Aug 2020 02:49:22 -0700 (PDT) Received: from localhost ([::1]:59992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA96O-00067I-1u for importer@patchew.org; Mon, 24 Aug 2020 05:49:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95O-0004Qj-6L for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:18 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:41393) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95M-0004lj-IG for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:17 -0400 Received: by mail-wr1-x42c.google.com with SMTP id p17so2325966wrj.8 for ; Mon, 24 Aug 2020 02:48:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nnYvgpj+yfRsy7MXb9YbrfpjgfASX8TYRFoNG96nT04=; b=aPZt7m8JkaQvwbTXMevz23ilxf0f13elevH6ENQ0HyhGa4QSrpjGH3rs3/hmTvBnoP peHdLzndhRCsOHq6jw0mhL3Rku0X+K74hT538BkqZIzcSIWHIKv7hG60O1bQLEBpPm7/ k9YOmsHXHrx/WxHDagNlI2UvWkF54wGtMsxy3mL+swUyKIcKsCovGKhU82f1Bfc3+lkt wKmSOccLxYcktp8JHLJi/6OuNgcWKieLUWpCd00opCcyJcPIcmvBXZcpuIJnTLB3zwJO pIbOU9spdoDPb6XIlT+iqAbETejpaLkHo9rj0WHAjEvupyz3Ig4YqR6AaPixFak/sKgJ mKtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nnYvgpj+yfRsy7MXb9YbrfpjgfASX8TYRFoNG96nT04=; b=YIH8s0q8X9zkMaEaW8abB1MXh5QJxtjrpv+9h6BfGzWjj/1sORIuTOMVumd9YVbtUX vinOJpq6n+C+mZTLsSuFzEVlv4TDo2ZDmpCmiYd+91rVf17seCZ8xS0IOgyc+/Zue4To 8aC3cnCawv0MG+JwcWlH4Aa9eo8sIlYF6ZpHbyemkJbkL3W8/OwCLVrngqKO9prdAIpi qw+dwiSQdiKeUErc2/O4s9gkqKQqtyMuC7c4Px2LhmItSjnxeoykpUvvTpeLpjlZey2F 3QMFqMH9H7igagtj8cfE+IV+ce++MpsCo0hZeLOoZv0a+bPka/YwVCii8sBCf38ibqMz PG2w== X-Gm-Message-State: AOAM531AvDCABfynlkuJBFEdycnKTR+m3LvL6FfRYv57UcuugyE1XC3r DLKPjK5SIr4SNYk37Y7QDX7POJWHBaXsu6vB X-Google-Smtp-Source: ABdhPJxHGG/Y4o7bQF12Sih+oJWcyZ97XuTtHHhmNWVQEHJoyrVPoQFjtCwWqPo6T/eOHyfTMcenSA== X-Received: by 2002:a5d:6806:: with SMTP id w6mr3775560wru.395.1598262494827; Mon, 24 Aug 2020 02:48:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Date: Mon, 24 Aug 2020 10:47:45 +0100 Message-Id: <20200824094811.15439-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The 'Cortex-A9MPCore internal peripheral' block can only be used with Cortex A5 and A9 cores. As we don't model the A5 yet, simply check the machine cpu core is a Cortex A9. If not return an error. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20200709152337.15533-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/cpu/a9mpcore.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 351295e5187..ec186d49abd 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#include "cpu.h" =20 #define A9_GIC_NUM_PRIORITY_BITS 5 =20 @@ -52,8 +53,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **= errp) *wdtbusdev; int i; bool has_el3; + CPUState *cpu0; Object *cpuobj; =20 + cpu0 =3D qemu_get_cpu(0); + cpuobj =3D OBJECT(cpu0); + if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9")= )) { + /* We might allow Cortex-A5 once we model it */ + error_setg(errp, + "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"= ); + return; + } + scudev =3D DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -70,7 +81,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **e= rrp) /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - cpuobj =3D OBJECT(qemu_get_cpu(0)); has_el3 =3D object_property_find(cpuobj, "has_el3", NULL) && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262566; cv=none; d=zohomail.com; s=zohoarc; b=A+XVN2hZIBQsJSocXDLHPTPcpKmCeaOKJJmF7Yp3ZwoPkh2lvtarjbO1r5t4KjgPoVt7sc8LjmeziKFiICg/ryF56njVCFsaaUrNR8w4OBmxQZVahNdsrFJRfX4RMpIGSyd+25PAufkpPgEMoH+6/szKZYWioNdi8aPDt6jzbgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262566; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d76Q5LBvtJQn3pY+eXI6scN5N0T9wemtRcn+yfENPBU=; b=cyZe1EMeiPVr5Y1Md//wMGhrcTgIuN3iOFaM9cQtM+j/uQjQ2DJ8tw4ZtBQyKzfNZt5gPxndV3aJGCeXmNvnqIGdDDH2OBNGg4MZaxnKHzF+pU7nDHXpnm8VzBgw4/vl3u5PnZeAALxkuTUzah9uOLpIA9Ceyt2QYMZcew2j91c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262566126685.4222804663664; Mon, 24 Aug 2020 02:49:26 -0700 (PDT) Received: from localhost ([::1]:60198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA96S-0006CF-Rt for importer@patchew.org; Mon, 24 Aug 2020 05:49:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95P-0004R4-3S for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:19 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:34029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95N-0004ln-GI for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:18 -0400 Received: by mail-wr1-x42e.google.com with SMTP id f7so8030100wrw.1 for ; Mon, 24 Aug 2020 02:48:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=d76Q5LBvtJQn3pY+eXI6scN5N0T9wemtRcn+yfENPBU=; b=pmRdiGpVTUV8Fs7xfolkkHIzyaxRfwQ4lq1jAbGUBH1WY8+nIsIbSlfOLVw5xSS+Kq MTjHNSi1igJQ2k5njpMkC6A7BGE91nnyCjkro6F+Z2rYN2d5Kbm9YoULA5z9ucYgbRtX dTUMWm9goVk6dbV1qbIMT5UAessNmlfh6CJ9AaXvays566EaiqZpZbMfDoBJI3+1112Z lYsEvw7jibRZsjJHo4VKvOFTDhIgq+6fnZ5pHYsmE047dnBaaUwQfJLLdF7HHd1a9ir8 JKBxJCkF6h1YybFDj/HhSujd6dS7vfJ3rrqjVoKyZkWSEqbGc0Cyu9ZmwMbBIKFfZkk6 MeaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d76Q5LBvtJQn3pY+eXI6scN5N0T9wemtRcn+yfENPBU=; b=G0NVXXh7OX9DKQBVSpyyKooI7FrUYWKUUZNudcs2R6x/YCNDemOsy+uUyfSVeW71i0 j1n2glmijiYZG55RFcGvaNvUUcr02u6Z/uiX83yltcLmn4TNxlo2+cXGYIRIFBkgJ82e dLLjf+5EZnmDVA/aHbHMvURyyD7++qHUiFLj1k8V4wwM8qB1LL4Ss0Axa/lm2oobnfVh Ay7bDIbiTnOkQqtmWRShH+FvxyECcMmsdBOhYAmsdpSgLvrJniv8FOuU6WvNmANM4jaM fB0BmUWRwodJ3A67Y6CPKF1jeiMYjQbtU5uVBoHnpUyOPrEFVuL7kMsNEhjK+NRRB/7j aB3g== X-Gm-Message-State: AOAM530aDWGmTgZ50yfANZxAHXwBzpTbbF2EGkZDX7HJjjbLCMwY8E0q 0SGsiRm6zwLdW2sXbmUSc62T9jw1EeRHHR5D X-Google-Smtp-Source: ABdhPJwL5cnKfXGwkhIGo0t4qfcqZqF1pvR5RWIZChOz/ADhyRu30HvwR40mf5wI62y+PZIvKpdwpA== X-Received: by 2002:adf:ec10:: with SMTP id x16mr4847820wrn.74.1598262495937; Mon, 24 Aug 2020 02:48:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/27] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Date: Mon, 24 Aug 2020 10:47:46 +0100 Message-Id: <20200824094811.15439-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Page and block PTE decoding can share some code. Let's first handle table PTE and factorize some code shared by page and block PTEs. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-2-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 48 ++++++++++++++++---------------------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e13a5f4a7cb..a3f9e473985 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -186,7 +186,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); - uint64_t pte; + uint64_t pte, gpa; dma_addr_t pte_addr =3D baseaddr + offset * sizeof(pte); uint8_t ap; =20 @@ -199,56 +199,42 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { trace_smmu_ptw_invalid_pte(stage, level, baseaddr, pte_addr, offset, pte); - info->type =3D SMMU_PTW_ERR_TRANSLATION; - goto error; + break; } =20 - if (is_page_pte(pte, level)) { - uint64_t gpa =3D get_page_pte_address(pte, granule_sz); + if (is_table_pte(pte, level)) { + ap =3D PTE_APTABLE(pte); =20 - ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + baseaddr =3D get_table_pte_address(pte, granule_sz); + level++; + continue; + } else if (is_page_pte(pte, level)) { + gpa =3D get_page_pte_address(pte, granule_sz); trace_smmu_ptw_page_pte(stage, level, iova, baseaddr, pte_addr, pte, gpa); - return 0; - } - if (is_block_pte(pte, level)) { + } else { uint64_t block_size; - hwaddr gpa =3D get_block_pte_address(pte, level, granule_sz, - &block_size); - - ap =3D PTE_AP(pte); - if (is_permission_fault(ap, perm)) { - info->type =3D SMMU_PTW_ERR_PERMISSION; - goto error; - } =20 + gpa =3D get_block_pte_address(pte, level, granule_sz, + &block_size); trace_smmu_ptw_block_pte(stage, level, baseaddr, pte_addr, pte, iova, gpa, block_size >> 20); - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); - return 0; } - - /* table pte */ - ap =3D PTE_APTABLE(pte); - + ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - baseaddr =3D get_table_pte_address(pte, granule_sz); - level++; - } =20 + tlbe->translated_addr =3D gpa + (iova & mask); + tlbe->perm =3D PTE_AP_TO_PERM(ap); + return 0; + } info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262648; cv=none; d=zohomail.com; s=zohoarc; b=Dgoj0/+DNiTke6AAOFPtuiJogPjhadu3V3VxYvSDbN2aEOjd3IIOwWy+Ct3KcOvPskOb/FxxuQIsx0UL5iOEqLICnZdzVGlGGWLUkPoyg/vIazZxsd5jUTbH4HGCVDxIuKPL7XaIqyKu9IXA7x1A7iVr/BkoKoGDlQTZ4jSNq3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262648; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eLG591HhmYEyBGzCCdtTUbFXHHvlRfQlo+J7D04QrlU=; b=eejaRYV8RgrANP/OTYAxxXwB+kMIG2qi9hr3gQKtEVLj6qMNRjUZiTLaqQ6J4G3u36fBTBI0g72fduxRdrPRcGop0AaaZvG1s2cNO9Jv9uVkw0Bd9uAy3zL+9/MZJAqYFtXVVL2nSkjnYkrHRwzHxJ5WY/nvOOkCb8hF9NqIQDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262648160867.7470084874473; Mon, 24 Aug 2020 02:50:48 -0700 (PDT) Received: from localhost ([::1]:40240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA97m-0001Ax-SY for importer@patchew.org; Mon, 24 Aug 2020 05:50:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95R-0004X9-R0 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:21 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:41986) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95P-0004m9-S0 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:21 -0400 Received: by mail-wr1-x433.google.com with SMTP id d16so7985425wrq.9 for ; Mon, 24 Aug 2020 02:48:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eLG591HhmYEyBGzCCdtTUbFXHHvlRfQlo+J7D04QrlU=; b=aVwvcF2n5I9Zo5ti7sg3Mwu9kazQ8pFzIQ+Qe4nO72gKukKHE25KHObir0J2wANV3Y X2w4VDemo276gZy66Zm0NiMtaeeZ7sULVWM/s5rfzbCf8iBpEFLOtd3ORjmCI6GVA3Sy GUUNcFhFXGMa0Ei0cgmiqER8USeFb9cNGEjkfsXxPD+RjbNH6z4On2r2HOedlWgA38mp xiGBUl4xnGvVVvx0SGYqch4SKIi2mr64gI4l7IHuuXt8Yo0V5XlxLIGhyLeM/gjvuSKV wz0FBp7H4DyKfmLASb0TXa3Kfxp/wJAI0J3ZcnVmG0+mLgDIgHO/cUc1wrmWvxy0gI5F 6jhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLG591HhmYEyBGzCCdtTUbFXHHvlRfQlo+J7D04QrlU=; b=WB3j6isNnb2cmntd8wA/nRPs2dUQf+CJPexZY4N1BhjpJ/d2+bdjUBk1Xy5w4tbUJc Ef3+hl2LMaA/D/EN5ln/uu2IqA/c9qUZ+4Bfu2MBwEWAltGMfMzyhqhYnPmnzoM/sRbo jtu7f9FWn1AR/Mh9BzuuW13SQwtbCpOW6MAexM5tuK9KjkWdjEwTuBDCucynTuc5UIiS eyaL4+akwlOdT4zOrvUgdSbvvMx5eh/npLL98O8ig3pWqGhLmcaHoJDgH70Zifus1SGR TdTjuOM+Lu0OnOGzez9aWwmMh8KhVxKtXBQqeqpz5JkLb3CxI1RUQAWBrSaTBGrpXuYN 7m/g== X-Gm-Message-State: AOAM531j3yN4AWJ5ksIHqz9JyqLovxfoI/Lgr9OkB1JoKnKGUPqbTgBJ qhk4We4boO8GVmGQfiK4mGsqt2B7iXeOYuM3 X-Google-Smtp-Source: ABdhPJy+fOWDWMSYceNcG4odV4DrQg3eKfGQyvCFzjBijW8mZcKwow84+ZLBiZMcHpuRwzVxvOT3rw== X-Received: by 2002:adf:dfc8:: with SMTP id q8mr4798510wrn.231.1598262497036; Mon, 24 Aug 2020 02:48:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/27] hw/arm/smmu-common: Add IOTLB helpers Date: Mon, 24 Aug 2020 10:47:47 +0100 Message-Id: <20200824094811.15439-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Add two helpers: one to lookup for a given IOTLB entry and one to insert a new entry. We also move the tracing there. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-3-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 2 ++ hw/arm/smmu-common.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 26 ++------------------------ hw/arm/trace-events | 5 +++-- 4 files changed, 43 insertions(+), 26 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ca4a4b1ad1e..1dceec5cb1f 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index a3f9e473985..f3aa581f807 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,6 +32,42 @@ =20 /* IOTLB Management */ =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) +{ + SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + + if (entry) { + cfg->iotlb_hits++; + trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + } else { + cfg->iotlb_misses++; + trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)= ); + } + return entry; +} + +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +{ + SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + + if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { + smmu_iotlb_inv_all(bs); + } + + key->asid =3D cfg->asid; + key->iova =3D entry->iova; + trace_smmu_iotlb_insert(cfg->asid, entry->iova); + g_hash_table_insert(bs->iotlb, key, entry); +} + inline void smmu_iotlb_inv_all(SMMUState *s) { trace_smmu_iotlb_inv_all(); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 57a79df55b5..cd2a2e7e148 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -636,7 +636,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; - SMMUIOTLBKey key, *new_key; =20 qemu_mutex_lock(&s->mutex); =20 @@ -675,16 +674,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - key.asid =3D cfg->asid; - key.iova =3D aligned_addr; - - cached_entry =3D g_hash_table_lookup(bs->iotlb, &key); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - cfg->iotlb_hits++; - trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { @@ -698,16 +689,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, goto epilogue; } =20 - cfg->iotlb_misses++; - trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); - - if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { - smmu_iotlb_inv_all(bs); - } - cached_entry =3D g_new0(IOMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { @@ -753,10 +734,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, } status =3D SMMU_TRANS_ERROR; } else { - new_key =3D g_new0(SMMUIOTLBKey, 1); - new_key->asid =3D cfg->asid; - new_key->iova =3D aligned_addr; - g_hash_table_insert(bs->iotlb, new_key, cached_entry); + smmu_iotlb_insert(bs, cfg, cached_entry); status =3D SMMU_TRANS_SUCCESS; } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6f..b808a1bfc19 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" +smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr,= bool leaf) "vmid =3D%d a smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" -smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t = miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d mi= ss=3D%d hit rate=3D%d" -smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d = miss=3D%d hit rate=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Introduce the smmu_get_iotlb_key() helper and the SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and smmu_iotlb_key_hash in the IOTLB related code section. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-4-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmu-internal.h | 1 + include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 66 ++++++++++++++++++++---------------- 3 files changed, 38 insertions(+), 30 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 7794d6d3947..3104f768cd2 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -96,4 +96,5 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 +#define SMMU_IOTLB_ASID(key) ((key).asid) #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 1dceec5cb1f..5f9f3535d2a 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -155,6 +155,7 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index f3aa581f807..7dc8541e8b4 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,10 +32,42 @@ =20 /* IOTLB Management */ =20 +static guint smmu_iotlb_key_hash(gconstpointer v) +{ + SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; + uint32_t a, b, c; + + /* Jenkins hash */ + a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); + a +=3D key->asid; + b +=3D extract64(key->iova, 0, 32); + c +=3D extract64(key->iova, 32, 32); + + __jhash_mix(a, b, c); + __jhash_final(a, b, c); + + return c; +} + +static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) +{ + const SMMUIOTLBKey *k1 =3D v1; + const SMMUIOTLBKey *k2 =3D v2; + + return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); +} + +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +{ + SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + + return key; +} + IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova) { - SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { @@ -62,8 +94,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, = IOMMUTLBEntry *entry) smmu_iotlb_inv_all(bs); } =20 - key->asid =3D cfg->asid; - key->iova =3D entry->iova; + *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); trace_smmu_iotlb_insert(cfg->asid, entry->iova); g_hash_table_insert(bs->iotlb, key, entry); } @@ -80,12 +111,12 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, uint16_t asid =3D *(uint16_t *)user_data; SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; =20 - return iotlb_key->asid =3D=3D asid; + return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova); =20 trace_smmu_iotlb_inv_iova(asid, iova); g_hash_table_remove(s->iotlb, &key); @@ -383,31 +414,6 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_= t sid) return NULL; } =20 -static guint smmu_iotlb_key_hash(gconstpointer v) -{ - SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; - uint32_t a, b, c; - - /* Jenkins hash */ - a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid; - b +=3D extract64(key->iova, 0, 32); - c +=3D extract64(key->iova, 32, 32); - - __jhash_mix(a, b, c); - __jhash_final(a, b, c); - - return c; -} - -static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) -{ - const SMMUIOTLBKey *k1 =3D v1; - const SMMUIOTLBKey *k2 =3D v2; - - return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); -} - /* Unmap the whole notifier's range */ static void smmu_unmap_notifier_range(IOMMUNotifier *n) { --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ArZ9QTqgUbPNGgXjOyzB+bi/eiKHbQx9hP7lHvaD3Rw=; b=M8Rzbdvf7HyCHjYUge4XdjczQ78OMpfRjAY0j/Surf2BvGX6EoR5rO3TdpKfZnkWOR qkDPVBhGxqHo1rqobVZ+8gV1CMcTeqT4jFxhUYUYMCMigbBvWRPcT2FcpDFcYTNkFJ5Y 0BUdqN0k2wrKJevRjmQcLzb9D64ABNrr2Meu2xvUNMKxVExaa2YnPDILih27fY+HvtC0 ZYTILYy/zQGgHy5us2Cy1fUqxtO10y0gI3Xu+nJNiFDa9xTBVR2GZEsJIAJPrGk24eg4 F8dz5TfI3w8DUAUWQ3LiNzke8lHZhrgLbPmcJ+T8I2lavOmAoYCOV6NH7F3HnctzOQuQ XAAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ArZ9QTqgUbPNGgXjOyzB+bi/eiKHbQx9hP7lHvaD3Rw=; b=HM/LjxtXn47cCFg3LxSPrU1KyxGwYNqJd433XKBlF+uaQ7w6iAL4pFwpcLLwXdSTkO mWD5uV45EllXj3YPbFP5w7Jzml8SBlz7953id4yG3zJt+kEaLj87Q4SdKF2lKIHZSk8Z +03euRGzOhv6WACcJHFiQ9hhTvMqZWx6KnZkdOIjAJMirTBKNbDne7V2UVOKvikefdKK vNrWCxlzY92yFgAsWVI5MEVbKzSFEPnUhIaijbexYe5/XT7WhdlefvnD71KUI0CrUUTQ lF17qmmqTULDR5mKNvvy2U/06v+VU7J7wxG3l9nuDpo/rQEn5abrImwNjY+rw28jsimY P5Jg== X-Gm-Message-State: AOAM531hbXun5qcn4sinyxFTxSikQNZq1SF0lu+WalQsg1gndX9fvP9v TZ6zj0Vsm9c142HU7E6K2GsXdBzRLJOdrdfA X-Google-Smtp-Source: ABdhPJwdkbKS8UjtZ5KQm4LOsibRDTkiJjgKziYGZ2K356MMjmyzk9S+V5KaOG8xscmYUVNK6uZuxw== X-Received: by 2002:a7b:c251:: with SMTP id b17mr4757858wmj.148.1598262499255; Mon, 24 Aug 2020 02:48:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/27] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Date: Mon, 24 Aug 2020 10:47:49 +0100 Message-Id: <20200824094811.15439-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-5-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 12 +++++++++--- hw/arm/smmu-common.c | 32 +++++++++++++++++--------------- hw/arm/smmuv3.c | 10 +++++----- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 5f9f3535d2a..79c2c6486ad 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -52,6 +52,12 @@ typedef struct SMMUTransTableInfo { uint8_t granule_sz; /* granule page shift */ } SMMUTransTableInfo; =20 +typedef struct SMMUTLBEntry { + IOMMUTLBEntry entry; + uint8_t level; + uint8_t granule; +} SMMUTLBEntry; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as @@ -140,7 +146,7 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) * pair, according to @cfg translation config */ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); =20 /** * select_tt - compute which translation table shall be used according to @@ -153,8 +159,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 7dc8541e8b4..398e958bb44 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -64,11 +64,11 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t= iova) return key; } =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - hwaddr iova) +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) { SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); - IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { cfg->iotlb_hits++; @@ -86,7 +86,7 @@ IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTrans= Cfg *cfg, return entry; } =20 -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); =20 @@ -94,9 +94,9 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, = IOMMUTLBEntry *entry) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); - trace_smmu_iotlb_insert(cfg->asid, entry->iova); - g_hash_table_insert(bs->iotlb, key, entry); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + g_hash_table_insert(bs->iotlb, key, new); } =20 inline void smmu_iotlb_inv_all(SMMUState *s) @@ -216,7 +216,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * @cfg: translation config * @iova: iova to translate * @perm: access type - * @tlbe: IOMMUTLBEntry (out) + * @tlbe: SMMUTLBEntry (out) * @info: handle to an error info * * Return 0 on success, < 0 on error. In case of error, @info is filled @@ -226,7 +226,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) */ static int smmu_ptw_64(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -246,8 +246,8 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->iova =3D iova; - tlbe->addr_mask =3D (1 << granule_sz) - 1; + tlbe->entry.iova =3D iova; + tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; =20 while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); @@ -298,14 +298,16 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); + tlbe->level =3D level; + tlbe->granule =3D granule_sz; return 0; } info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: - tlbe->perm =3D IOMMU_NONE; + tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } =20 @@ -321,7 +323,7 @@ error: * return 0 on success */ inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags p= erm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { if (!cfg->aa64) { /* diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cd2a2e7e148..db74d27add5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -626,7 +626,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, SMMUTranslationStatus status; SMMUState *bs =3D ARM_SMMU(s); uint64_t page_mask, aligned_addr; - IOMMUTLBEntry *cached_entry =3D NULL; + SMMUTLBEntry *cached_entry =3D NULL; SMMUTransTableInfo *tt; SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { @@ -676,7 +676,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, =20 cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { + if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { event.type =3D SMMU_EVT_F_PERMISSION; @@ -689,7 +689,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, goto epilogue; } =20 - cached_entry =3D g_new0(IOMMUTLBEntry, 1); + cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { g_free(cached_entry); @@ -743,9 +743,9 @@ epilogue: switch (status) { case SMMU_TRANS_SUCCESS: entry.perm =3D flag; - entry.translated_addr =3D cached_entry->translated_addr + + entry.translated_addr =3D cached_entry->entry.translated_addr + (addr & page_mask); - entry.addr_mask =3D cached_entry->addr_mask; + entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); break; --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ygr0uj6t9xPd8aCefwuAXcYRZVoEMDhVPJTRyZnGj00=; b=SSnA6cr11UTftlh7zaBK1WJbFKwuAFKOKrhIHSetDs+Ed+rT8fqp681VQrLhyLAlxa HNu+Lsu7fBnVhmuPtXVTsQzVgjAaLxB2kHbuEmX9InmMTBNUcs2SWtzIpqVjdJHaKjKS dBM5TbW4KaZOuo+byKKoUeizbbOqarMFe7tyhB6QTQcBFku0dnAtzE0by8QOLyFxKwM0 qIPmTZLWZMwSxatuOZpZa/0sjnRzN/0v+056VCvDrPzweoR9SLuCfbSYQs04gas37BBT 3DH1OSv0CyYQim4VaoeagS4KoeYkkHMfmh8CgFqqtMepldMAaXUGnm+j9oaog7c9aMdi hQLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ygr0uj6t9xPd8aCefwuAXcYRZVoEMDhVPJTRyZnGj00=; b=dYUho7VNHSUSbbNmsbp6Nm1ORHzB1MJ9XKIwROlLdemjd34AjsP4k+nQc87eLHbMXF xaudbGJ91U4sCZQ4G9rUL5sYdcWSrPJzBhgndhzqWvbJMhKJTucgvfTwGtbw3ecophWb rUCK5ja7/CUoRAmsaOVssEAtIDFYn12Ygi41ElncvMArQVSFl0+tGTFgANrrfgoAmG1F nmIiOyEekdRq1lU3jPa/1uOcNDhFrzN1EANIh9zsFpo4OsFrUnFZrXB68sdi79q/LrvG fPTHeefhN6bI2xMtla+GpMwphhjkhH6Ep4f0tX/D49Q38++ZKfND2BRYRXmZ/ltbbVIA BVJQ== X-Gm-Message-State: AOAM5316xxHeYkJggeqHvZlbaFZ07K6rJ2ZLFsZboQF88JhKvLrhFy/J ufDFvKANwZYXZ64rPmJtKkf1+BUOICCZXAdk X-Google-Smtp-Source: ABdhPJxMNKT8kDLR7WoegoQcCNkjDDPFHeQo5j+WC898cos1HSUSJDPQCTN9nO6IcnmMyH6BJid4PQ== X-Received: by 2002:a7b:c2e1:: with SMTP id e1mr961789wmk.27.1598262500754; Mon, 24 Aug 2020 02:48:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/27] hw/arm/smmu-common: Manage IOTLB block entries Date: Mon, 24 Aug 2020 10:47:50 +0100 Message-Id: <20200824094811.15439-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consumes IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or page start address and size). Also the level/tg of the entry is encoded in the key. In subsequent patches we will enable range invalidation. This latter is able to provide the level/tg of the entry. Encoding the level/tg directly in the key will allow to invalidate using g_hash_table_remove() when num_pages equals to 1. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-6-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmu-internal.h | 7 ++++ include/hw/arm/smmu-common.h | 10 ++++-- hw/arm/smmu-common.c | 67 ++++++++++++++++++++++++++---------- hw/arm/smmuv3.c | 6 ++-- hw/arm/trace-events | 2 +- 5 files changed, 67 insertions(+), 25 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 3104f768cd2..55147f29be4 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -97,4 +97,11 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, } =20 #define SMMU_IOTLB_ASID(key) ((key).asid) + +typedef struct SMMUIOTLBPageInvInfo { + int asid; + uint64_t iova; + uint64_t mask; +} SMMUIOTLBPageInvInfo; + #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 79c2c6486ad..ece62c36523 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -97,6 +97,8 @@ typedef struct SMMUPciBus { typedef struct SMMUIOTLBKey { uint64_t iova; uint16_t asid; + uint8_t tg; + uint8_t level; } SMMUIOTLBKey; =20 typedef struct SMMUState { @@ -159,12 +161,14 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 398e958bb44..2922deec6fc 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -39,7 +39,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 /* Jenkins hash */ a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid; + a +=3D key->asid + key->level + key->tg; b +=3D extract64(key->iova, 0, 32); c +=3D extract64(key->iova, 32, 32); =20 @@ -51,24 +51,41 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) { - const SMMUIOTLBKey *k1 =3D v1; - const SMMUIOTLBKey *k2 =3D v2; + SMMUIOTLBKey *k1 =3D (SMMUIOTLBKey *)v1, *k2 =3D (SMMUIOTLBKey *)v2; =20 - return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); + return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova) && + (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg); } =20 -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova, .tg =3D tg, .lev= el =3D level}; =20 return key; } =20 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - hwaddr iova) + SMMUTransTableInfo *tt, hwaddr iova) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); - SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + uint8_t tg =3D (tt->granule_sz - 10) / 2; + uint8_t inputsize =3D 64 - tt->tsz; + uint8_t stride =3D tt->granule_sz - 3; + uint8_t level =3D 4 - (inputsize - 4) / stride; + SMMUTLBEntry *entry =3D NULL; + + while (level <=3D 3) { + uint64_t subpage_size =3D 1ULL << level_shift(level, tt->granule_s= z); + uint64_t mask =3D subpage_size - 1; + SMMUIOTLBKey key; + + key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + entry =3D g_hash_table_lookup(bs->iotlb, &key); + if (entry) { + break; + } + level++; + } =20 if (entry) { cfg->iotlb_hits++; @@ -89,13 +106,14 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTra= nsCfg *cfg, void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + uint8_t tg =3D (new->granule - 10) / 2; =20 if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -114,12 +132,26 @@ static gboolean smmu_hash_remove_by_asid(gpointer key= , gpointer value, return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) +static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, + gpointer user_data) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova); + SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; + IOMMUTLBEntry *entry =3D &iter->entry; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; + SMMUIOTLBKey iotlb_key =3D *(SMMUIOTLBKey *)key; + + if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { + return false; + } + return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; +} + +inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +{ + SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; =20 trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_remove(s->iotlb, &key); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) @@ -246,9 +278,6 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->entry.iova =3D iova; - tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; - while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; @@ -298,7 +327,9 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.translated_addr =3D gpa; + tlbe->entry.iova =3D iova & ~mask; + tlbe->entry.addr_mask =3D mask; tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); tlbe->level =3D level; tlbe->granule =3D granule_sz; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index db74d27add5..b717bde8320 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -674,7 +674,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; @@ -744,7 +744,7 @@ epilogue: case SMMU_TRANS_SUCCESS: entry.perm =3D flag; entry.translated_addr =3D cached_entry->entry.translated_addr + - (addr & page_mask); + (addr & cached_entry->entry.addr_mask); entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); @@ -972,7 +972,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_all(bs); + smmu_iotlb_inv_iova(bs, -1, addr); break; } case SMMU_CMD_TLBI_NH_VA: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index b808a1bfc19..f74d3e920f1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -16,7 +16,7 @@ smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB = invalidate asid=3D%d addr smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 +smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a single IOVA invalidation. Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA command. At the moment it is only used for tracing. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-7-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 36 +++++++++++++++++------------------- hw/arm/trace-events | 3 +-- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b717bde8320..e4a2cea7adc 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -836,6 +836,22 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, in= t asid, dma_addr_t iova) } } =20 +static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +{ + dma_addr_t addr =3D CMD_ADDR(cmd); + uint8_t type =3D CMD_TYPE(cmd); + uint16_t vmid =3D CMD_VMID(cmd); + bool leaf =3D CMD_LEAF(cmd); + int asid =3D -1; + + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { + asid =3D CMD_ASID(cmd); + } + trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); + smmuv3_inv_notifiers_iova(s, asid, addr); + smmu_iotlb_inv_iova(s, asid, addr); +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -966,27 +982,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) smmu_iotlb_inv_all(bs); break; case SMMU_CMD_TLBI_NH_VAA: - { - dma_addr_t addr =3D CMD_ADDR(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); - smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_iova(bs, -1, addr); - break; - } case SMMU_CMD_TLBI_NH_VA: - { - uint16_t asid =3D CMD_ASID(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - dma_addr_t addr =3D CMD_ADDR(&cmd); - bool leaf =3D CMD_LEAF(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(bs, asid, addr); - smmu_iotlb_inv_iova(bs, asid, addr); + smmuv3_s1_range_inval(bs, &cmd); break; - } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f74d3e920f1..c219fe9e828 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,8 +45,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0= x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid= =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" -smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262740; cv=none; d=zohomail.com; s=zohoarc; b=euEIbRuFmqoG+ym/nj7UOtooHIkUahCtv7buJ8zdm9WXbPGM9Mdb955vC+ahBTIo3fJDsT7/+uS+w6DUmwbdNIuKvFAK/X4TfIzrIMawk+32auCp2LjdWTZ/cJPn+5sRfgnDM++pOay+6XatUiKpN4vWfBF8pzQhMXlaGrejrYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262740; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+IRaKpLNT6dm56V52rlALT3BSN1ENhS7a0LI65DSjGE=; b=ZKky6u3aP3SVZkzv0m2XlqlqwCZ5tUhJjuBdLKOx4+qwBzxDWmmb6/WMaiI/bGiafIXpfNj9aad9TDClfstM2a+mOGIUvzfJ5PTn+kwNXzeS5aDCtWyEwpOzF44+6XaFFkMWrBn01LZRGctbmFhFTdkQj009EwrlOb3zS9p4TSs= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+IRaKpLNT6dm56V52rlALT3BSN1ENhS7a0LI65DSjGE=; b=nBHVx29WhIEO1OSStttvJRrCnhk7+qtGwwPE7b0SisUnQiZdTkSAVKBBnC4AvGh59V n8NlCAVrE5iLzfgJSMegu3WKn8qd/tbUhZfDg7S3kKpdcSAvQPlZ7YDrNG2vs+/2ZW9S 2yosbs2rfs9Yx0eGS2gfg2ZIOI9BvT/KnckYktKrBZGvt7/iyfsWosJJSBPwa67CXaTj Hza4ZBl0Wi2XEn8hF+HrLQjV8+mkx3nidORJbROgrv9ELEeUPos1pT/ZySVpwpXATdtq tPSgjgnGmrwDVyQsy6nFp/itbRIsdcIab9t6CIH8EvUi/3YSSL/9uWSEiIQQ0sLnptCS z13A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+IRaKpLNT6dm56V52rlALT3BSN1ENhS7a0LI65DSjGE=; b=F7Lk29YQXmXyzgt49uoDZNOi74DYviK9amGhHKcgW1A2NSv5y78V2QtlTIKySBsZ+i 9X1ybmm/EW7o0N9y+KtuO+pExa0gw2EDaGQeTnHMfIFtZHrhQdsVcma8DELz5WmZ0m4t za5Nc8mZj+urzH4FPwt0lORyH3vBJquSWX6hHPoV+/66s1j2iGTMkMYi1AEJYCdHHA2m +VU4v1c8RSxDd5uvtlEm1dh7TLT8+hlSaCm1sTfxejTiYquRMxl9Rkouz2Md9n2TAKZ4 zLMFsfLaWEeZF8ChyYr1ghf8+Wq3Pe9JDGgghOchHdvEV3WlvZ2QQbxri8BCbizZWrkD tYHQ== X-Gm-Message-State: AOAM532CtlzeNdTAIZpuXVCn5yZ3I4cIQdmQPWpiK9j4c8Hp/Gm79pQU ZlaawnecsdHWnJNWNq33meFJIrJacoq2RHJS X-Google-Smtp-Source: ABdhPJzqJeuMWBSgOXTlsRpdhF4GkAIiAbPwN1pqc6q1b/EuIeyrBkDr1Yu5jt0cbq/ti51UpG8RRQ== X-Received: by 2002:adf:b1ca:: with SMTP id r10mr5338101wra.150.1598262503282; Mon, 24 Aug 2020 02:48:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation Date: Mon, 24 Aug 2020 10:47:52 +0100 Message-Id: <20200824094811.15439-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-8-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 4 +++ include/hw/arm/smmu-common.h | 3 +- hw/arm/smmu-common.c | 25 +++++++++++--- hw/arm/smmuv3.c | 64 +++++++++++++++++++++++------------- hw/arm/trace-events | 4 +-- 5 files changed, 69 insertions(+), 31 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 4112394129e..5babf72f7d5 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -298,6 +298,8 @@ enum { /* Command completion notification */ }; =20 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) +#define CMD_NUM(x) extract32((x)->word[0], 12 , 5) +#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) #define CMD_SSV(x) extract32((x)->word[0], 11, 1) #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) @@ -310,6 +312,8 @@ enum { /* Command completion notification */ #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16) #define CMD_RESP(x) extract32((x)->word[2], 11, 2) #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1) +#define CMD_TTL(x) extract32((x)->word[2], 8 , 2) +#define CMD_TG(x) extract32((x)->word[2], 10, 2) #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5) #define CMD_ADDR(x) ({ \ uint64_t high =3D (uint64_t)(x)->word[3]; \ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ece62c36523..4f6acf634cf 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -168,7 +168,8 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t= iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 2922deec6fc..8d89a86699a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -143,15 +143,30 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { return false; } - return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || + ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +inline void +smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl) { - SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; + if (ttl && (num_pages =3D=3D 1)) { + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 - trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); + g_hash_table_remove(s->iotlb, &key); + } else { + /* if tg is not set we use 4KB range invalidation */ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + + SMMUIOTLBPageInvInfo info =3D { + .asid =3D asid, .iova =3D iova, + .mask =3D (num_pages * 1 << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_asid_iova, + &info); + } } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e4a2cea7adc..89ab11fc36a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -785,42 +785,49 @@ epilogue: * @n: notifier to be called * @asid: address space ID or negative value if we don't care * @iova: iova + * @tg: translation granule (if communicated through range invalidation) + * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, - dma_addr_t iova) + int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; - SMMUTransTableInfo *tt; - SMMUTransCfg *cfg; IOMMUTLBEntry entry; + uint8_t granule =3D tg; =20 - cfg =3D smmuv3_get_config(sdev, &event); - if (!cfg) { - return; - } + if (!tg) { + SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; + SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &event); + SMMUTransTableInfo *tt; =20 - if (asid >=3D 0 && cfg->asid !=3D asid) { - return; - } + if (!cfg) { + return; + } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { - return; + if (asid >=3D 0 && cfg->asid !=3D asid) { + return; + } + + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; } =20 entry.target_as =3D &address_space_memory; entry.iova =3D iova; - entry.addr_mask =3D (1 << tt->granule_sz) - 1; + entry.addr_mask =3D num_pages * (1 << granule) - 1; entry.perm =3D IOMMU_NONE; =20 memory_region_notify_one(n, &entry); } =20 -/* invalidate an asid/iova tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova) +/* invalidate an asid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -828,28 +835,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova) IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, + tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova); + smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); } } } =20 static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) { + uint8_t scale =3D 0, num =3D 0, ttl =3D 0; dma_addr_t addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); uint16_t vmid =3D CMD_VMID(cmd); bool leaf =3D CMD_LEAF(cmd); + uint8_t tg =3D CMD_TG(cmd); + hwaddr num_pages =3D 1; int asid =3D -1; =20 + if (tg) { + scale =3D CMD_SCALE(cmd); + num =3D CMD_NUM(cmd); + ttl =3D CMD_TTL(cmd); + num_pages =3D (num + 1) * (1 << (scale)); + } + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); } - trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr); - smmu_iotlb_inv_iova(s, asid, addr); + trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf= ); + smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); } =20 static int smmuv3_cmdq_consume(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c219fe9e828..3d905e0f7d0 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start= =3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid =3D%d asid =3D%d addr=3D0x%"PR= Ix64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) = "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=apEmOXm4AQqmayGyw572zskFnVNsfChXfz8USNcN8vs=; b=dve8epIUfMeiNe1rf+TGWWGzxvIwkaB+f9e1jikEu8IGtNxpNWW6dc3tGXIkOPr2dw vgxpiYzDlSjUXRftVO/9Iq4k4Auh8dhtEsKGOlarMUdLE5KXdFxm3XcgtmofPShKXi6s 0QUKn1hBSypr4Y6zK41W0O5cmYT3wA2jyWFwPnvJW2C+cDlY6TNacrokQDz+4gY6/ADR XXwlR99lKWWijHITCJxPRtPWkR8oY0C5QZbbd8h2HO1N7xDmBPfJt4ktHR3OiyfJSA6L ZGub/NL2PrhzyQs4otIrfni2MvN0I05Jp6LuT0gSndLt4iE+0NY7ezfzH5igN69+F7qF ZNEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apEmOXm4AQqmayGyw572zskFnVNsfChXfz8USNcN8vs=; b=nSjfjrR1BXu3OqHUlkJixX5Mm8PJFzxFQt66Cn3cjk6/XjBHgR1Dqe8695wsD1Wv7A FF4rROsPCKoxuE63zKhHM4YHxhsud1Mmfi7mNK4CnttigDV1NX0Q+iIKAWkt7J5chxI3 bfOP+9E72QdgOIzxVlwcUIC4+gN4GtjGY5dyGiZFk8XE1wVfHIlBb7TJEiRA6i0UZL8/ cDqZcp8fEE4zqbV8c92oRFNiDb04KklmeEpFd/HseFtPb2Fswd4BFJ0VzpzPtlj+O6KV g76yJ8aEfdm0bAuxTjttO3sX8IzpRGFz1Mo/JJoFWGd2OW4oHCzyLO2t7mEaPqZNXVmD OysQ== X-Gm-Message-State: AOAM532+x38f6+jektcU2pgcfnPI0+3YzdWMKWefR4HwdQKx43/smvlh 1YO9izG6oLjZSkNdfwajD34D5tKq566OqFsj X-Google-Smtp-Source: ABdhPJxu62EuD6hDwXGTiVyy8g5O1En38Etfpqr7YzEg2xHZUW7JQYtvuvo3kwlcl/JWQTurbQ+vzg== X-Received: by 2002:a1c:f30f:: with SMTP id q15mr4886402wmq.60.1598262504540; Mon, 24 Aug 2020 02:48:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/27] hw/arm/smmuv3: Fix IIDR offset Date: Mon, 24 Aug 2020 10:47:53 +0100 Message-Id: <20200824094811.15439-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger The SMMU IIDR register is at 0x018 offset. Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton") Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-9-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 5babf72f7d5..ef093eaff50 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -63,7 +63,7 @@ REG32(IDR5, 0x14) =20 #define SMMU_IDR5_OAS 4 =20 -REG32(IIDR, 0x1c) +REG32(IIDR, 0x18) REG32(CR0, 0x20) FIELD(CR0, SMMU_ENABLE, 0, 1) FIELD(CR0, EVENTQEN, 2, 1) --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262940; cv=none; d=zohomail.com; s=zohoarc; b=CiY+qZH+iG2LiUKbllaiui4zzgdh2M++cSoQMzxjO2OgLb7Jsc4yBjml0EpnjvFQmVLW0Qeg8t4wJ+PQ5na9rQJyIx0LgO+OlZoz7bocvtXvsesRoQoCTuY6aI8tRWU9MOTnYr3sJoHpzs/kqfStQ89ySiTH6vS/we34A99un+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262940; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pJN8+LcfVLeFiNPeCoxtXt7wzipaKiTYfFygqw+Wy9M=; b=Z5p52TMYnMX1GVUvftCvS7GYn6BiowhcH1fkFY1vkOrItmqIjwu8xlbnvNLK7l5h6g5b9anfCOiSoKdnrsawbU5ZE4f8iu0dkuRWayqA0onz4n+p3FB895CydwKkcWxJ+CKBUk4lhR/GvcTqPzoz6EGLh2l+tEIk6kVXysh+EKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262940407208.32461762218566; Mon, 24 Aug 2020 02:55:40 -0700 (PDT) Received: from localhost ([::1]:37106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9CV-0002sQ-26 for importer@patchew.org; Mon, 24 Aug 2020 05:55:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95Y-0004rN-SN for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:28 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:37880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95X-0004nG-4q for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:28 -0400 Received: by mail-wr1-x42a.google.com with SMTP id y3so7988249wrl.4 for ; Mon, 24 Aug 2020 02:48:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pJN8+LcfVLeFiNPeCoxtXt7wzipaKiTYfFygqw+Wy9M=; b=bqIFDoLY6ff7Tn9hEEB5b03CIQOA+hdM5kmN5qt083tFZRWOhHFpiTF/Z+xxbPkLl9 Eioq0wzsBawH+hF5DyXp6n/uOLEAoFWefZCXC81nCS6MeNZx7dFvs+uo9z7w5RaEredW CcawJoUNXwRQclpAQUE18oGY0VDcID1kHJ9NxLBuOUCtbem1NY+nB5uL5l84EMja3piy Z57FbO05SR7kC09IblrOPJTthJrn9Z21lE1moHNd9DHRfrP7AkmQfJbKmIof5j9WPTAI cjNkFaW8BehckhfK+IN8datMBZazuwDgnRjAJOyYSJ8JDOR4b/nUt8BKz2DhOrImKlOF Z3UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pJN8+LcfVLeFiNPeCoxtXt7wzipaKiTYfFygqw+Wy9M=; b=PoTuSK/TtzOqY49VSILgXtVq5AiI4kGv7JqQNNRQISFcO2taBptChZs4J3irxRCmKM 7mFvalL/rg67tguFDd+lhgFXcCqrb/MTu/CAeByUOYgBhzKMuqcIyZpFgmPjE/ndCvQp sNkTrtRUpBlOjVwjSk2DIsErzMP1UVuUvzfvUH76uARAZyQ5tSeC88wfF7iPKyMgiU7S m9xVAe7xadRuBRiVDD53B4fcksMPJAUJHYOzTng7H66sUtSgfK4zDd6dqdP+HLSn73x0 IuexYUE2SlPTq5wjJ75k5AuEScy0Lf1eHGu5mcH+ehMUH/aU10H5zIp5JarFHFFdtqb2 q4xA== X-Gm-Message-State: AOAM533gG+Nu/k5Yuvfo2LyunLCkAqFZJnCTsXgy9CHRSRWcpWtGYmMd SPvDBMPkc7PrBr+qnvaXzMKTyzohYoY1CezY X-Google-Smtp-Source: ABdhPJyByLPjwubt6ZfXK9r5DOUUjTFiHvB1LijTzr7kqm3v/rIvbC91g9eGqScUvHFm5ytgZL5fGw== X-Received: by 2002:adf:ec10:: with SMTP id x16mr4848405wrn.74.1598262505544; Mon, 24 Aug 2020 02:48:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support Date: Mon, 24 Aug 2020 10:47:54 +0100 Message-Id: <20200824094811.15439-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Add the support for AIDR register. It currently advertises SMMU V3.0 spec. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-10-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index ef093eaff50..bd34a4f3300 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -64,6 +64,7 @@ REG32(IDR5, 0x14) #define SMMU_IDR5_OAS 4 =20 REG32(IIDR, 0x18) +REG32(AIDR, 0x1c) REG32(CR0, 0x20) FIELD(CR0, SMMU_ENABLE, 0, 1) FIELD(CR0, EVENTQEN, 2, 1) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 36b2f452539..68d7a963e0f 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -41,6 +41,7 @@ typedef struct SMMUv3State { =20 uint32_t idr[6]; uint32_t iidr; + uint32_t aidr; uint32_t cr[3]; uint32_t cr0ack; uint32_t statusr; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 89ab11fc36a..718f28462ea 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1251,6 +1251,9 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr = offset, case A_IIDR: *data =3D s->iidr; return MEMTX_OK; + case A_AIDR: + *data =3D s->aidr; + return MEMTX_OK; case A_CR0: *data =3D s->cr[0]; return MEMTX_OK; --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263031; cv=none; d=zohomail.com; s=zohoarc; b=kIvgoCW9lRXOBYuePIrvn9wyzqbbOgJSxcoOuITTQEPBXdk5rilnF7EN0b1PnK2GkGNQBCTRvWS07Cxh7sEPRbM9MDE4bbCAOQ/PsaefR/Q3eqUizYFuxZg+ffknY1pYuf0UMrfcBUxhqhHCq1z2HfmakECyH9dilLpfSMpXWYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263031; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6kPWsc9hK5bWcqLb2sRsR3vabCpYIdyWe54DMmHZ/ow=; b=WCNgNPJ/KVanmphQjZG1nzQmkB32zIedLeB2vABWeEnBxiwg7xrV2qiTA4r5bk5AaswwqMwZZ6ApGpsSX5l2XSNv2DS9RgZQbMY1gvSv4nvzNiYTnl05fe37g+q2T5AQClzttOGSwQgm0syjYWllBpBbltj4W0RWlOtJou4I4bA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263031936379.08011231687783; Mon, 24 Aug 2020 02:57:11 -0700 (PDT) Received: from localhost ([::1]:44304 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9Dy-0005qV-Nv for importer@patchew.org; Mon, 24 Aug 2020 05:57:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95a-0004ur-26 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:30 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:34037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95Y-0004nO-1r for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:29 -0400 Received: by mail-wr1-x435.google.com with SMTP id f7so8030633wrw.1 for ; Mon, 24 Aug 2020 02:48:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6kPWsc9hK5bWcqLb2sRsR3vabCpYIdyWe54DMmHZ/ow=; b=PnYaNqnzqSE4MqGBwRowlNMbxvyRyxRfEFCpEHYKlK5xaWaXC7AwTYyDqgLG+RzduN 80dxp0Y3HGOfnA2oY0L04FuTl/1Khx30SJOeaRYjxmL1phbBOkUod6zni5U1rtRpJp5U k/G7fxnsSFhFWr9bDkrE6e7CQPu9MKWsjNkaxhu16aCp/mF4FaN8JGBU6nxKgJ97Uecg LZ9h2EzMJSb33kgjWka+xBYFq3QRIeqSgM2PpayMrxCQziSVM+4fH+U6gITKQYATJhY/ 8L1WQE5bxTtUHBCvOPE8PwInxhfoJEeryHTQfVLq7LZ2O+yu9G+Dl4Rtqr8jqd6AD8h9 yL/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6kPWsc9hK5bWcqLb2sRsR3vabCpYIdyWe54DMmHZ/ow=; b=UrZ5dkOuwVmW3DYSYav7g3aZLW+sFSakQ4sRGKhlDicS9SUamtH70SGvFz/sguqtEy WhhiEUkpv9wAmBPuXs0LMd382An5RMIUFmSvXS5NgF6KK3D8oPBKp+bjKM+Bbc/1NRXt Qr5EmFb5jatrRv2tru7CfmHD4QUmatf0s5KrVmppc843qKz4COFC9Fv+JI/WSvrPKB+H mno+AYYqA/X0OqSL3J9jznc7mHwDwSVcPfdVAfbEY0eTaklNvEnIJ0wwTsrkCgAPntAv 438A39eBgpzmIcuxFzdr5nMPAwBYxoelS2Rwr/2fGfYvMxbetCYVquUiY4XEVzxDTxD1 xnqA== X-Gm-Message-State: AOAM531y/FABMesMXsSMZD393kVryY0FB6hMGy1jhXECYg2FQpFranDS 5QF18ksUz5n8jD5pOEVqWAjaQnzCd8q7ujov X-Google-Smtp-Source: ABdhPJzd9wWcGWTlAF7Mu5m2EMhL7xFpJOn7U/s2Mqv1MDcGQdiPqBE6bXH/B45zhmibMoJtsoX90g== X-Received: by 2002:adf:edc6:: with SMTP id v6mr4955796wro.221.1598262506471; Mon, 24 Aug 2020 02:48:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support Date: Mon, 24 Aug 2020 10:47:55 +0100 Message-Id: <20200824094811.15439-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger HAD is a mandatory features with SMMUv3.1 if S1P is set, which is our case. Other 3.1 mandatory features come with S2P which we don't have. So let's support HAD and advertise SMMUv3.1 support in AIDR. HAD support allows the CD to disable hierarchical attributes, ie. if the HAD0/1 bit is set, the APTable field of table descriptors walked through TTB0/1 is ignored. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-11-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 2 ++ include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 2 +- hw/arm/smmuv3.c | 6 +++++- hw/arm/trace-events | 2 +- 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index bd34a4f3300..9ae7d97fafd 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -54,6 +54,7 @@ REG32(IDR1, 0x4) =20 REG32(IDR2, 0x8) REG32(IDR3, 0xc) + FIELD(IDR3, HAD, 2, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); @@ -578,6 +579,7 @@ static inline int pa_range(STE *ste) lo =3D (x)->word[(sel) * 2 + 2] & ~0xfULL; \ hi | lo; \ }) +#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1) =20 #define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) #define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 4f6acf634cf..880dccd7c04 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -50,6 +50,7 @@ typedef struct SMMUTransTableInfo { uint64_t ttb; /* TT base address */ uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ uint8_t granule_sz; /* granule page shift */ + bool had; /* hierarchical attribute disable */ } SMMUTransTableInfo; =20 typedef struct SMMUTLBEntry { diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8d89a86699a..3838db13952 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -316,7 +316,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (is_table_pte(pte, level)) { ap =3D PTE_APTABLE(pte); =20 - if (is_permission_fault(ap, perm)) { + if (is_permission_fault(ap, perm) && !tt->had) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 718f28462ea..b262f0e4a74 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, HAD, 1); + /* 4K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); @@ -270,6 +272,7 @@ static void smmuv3_init_regs(SMMUv3State *s) =20 s->features =3D 0; s->sid_split =3D 0; + s->aidr =3D 0x1; } =20 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, @@ -506,7 +509,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEve= ntInfo *event) if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) { goto bad_cd; } - trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz); + tt->had =3D CD_HAD(cd, i); + trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt-= >had); } =20 event->record_trans_faults =3D CD_R(cd); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3d905e0f7d0..c8a4d80f6bd 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -39,7 +39,7 @@ smmuv3_translate_abort(const char *n, uint16_t sid, uint6= 4_t addr, bool is_write smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint6= 4_t translated, int perm) "%s sid=3D%d iova=3D0x%"PRIx64" translated=3D0x%"= PRIx64" perm=3D0x%x" smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=3D%d" -smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= ) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d" +smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= , bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d" smmuv3_cmdq_cfgi_ste(int streamid) "streamid =3D%d" smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=C4FDGofxkhp2CW5sAZODmLDNNvMWWKgKI6wWO5BMgFQ=; b=sx5Ic1jEALy0P6us1DgVxG37lwqFttI+T7kib9lgHCKBtkyVf6G9vROR9jPSybEEXF Ln0FuUiIIYwZoqeEQSlYQD73Y++xTqxA8SpMzAQdcFNLzYuM3ZWk4r+Hp0ZNIa6zFvDl 4YAGKgvYOgGfuLcgmj8yQhSWODmtJTPZUBF88yHLWyswyPpULiLwQzOmDhOVOOJTmjIO V3X6RE0+5x3kBdQuBnVzlNrv0ldcrRUIhb3X7pSWf5xE1p6oMlPGNUUB5dlzyAHgTr1D TIiCRzKZ8zGfrc82MjTvrZnsUeVPY9JtWPgQdAAsHGOuigGIEEYoqPoiHSyaKR39IAsd 3lXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C4FDGofxkhp2CW5sAZODmLDNNvMWWKgKI6wWO5BMgFQ=; b=b3gJwHyHZA/KCTnpLsQ/IZ7VrkY9h3M7AqMDWIX57SaTePIbm5p5XCqGKPhzWlFoxm y65fdAEn6rbAZxDJaJS5Tgqn8KO5HWKlf3P0yi0xSoNakIWwV0TubDacO6GB30LwyINR NYTuN8quUWHf5GIT71s5+fwZBfSzmL4r9/tmlhRJ6LedATWafmlnyuw/NssQhwV8nkS2 f1RS7c98jVh8NbjNWJheSAD34/owbO5BpqiFUrUu/wOR/yw7STY/DNNz26ITvrMMiAPu ovD5av/1QVTJcVwArsUUDpxdyA3gdSL+eECGky0UprqwwpoVrxtjxHT+wvEzn+VCVOhc yVcQ== X-Gm-Message-State: AOAM531aV5/WTSIdUNYx5LcUtAUZuLf5h91UPBVuxiMw4WEMozoVLFc7 1Fj8K3D7c/Ocxu78AAmsIW13e43e3pgoyLdr X-Google-Smtp-Source: ABdhPJwhGDeXHfcAoZchRXHfXzpmADT9ZbKrd7kYZYeVhdlkVyZmSbpFTi9GzTlCM/vG/9Rl2tJHWw== X-Received: by 2002:a5d:5704:: with SMTP id a4mr4914066wrv.318.1598262507630; Mon, 24 Aug 2020 02:48:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation Date: Mon, 24 Aug 2020 10:47:56 +0100 Message-Id: <20200824094811.15439-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Eric Auger Expose the RIL bit so that the guest driver uses range invalidation. Although RIL is a 3.2 features, We let the AIDR advertise SMMUv3.1 support as v3.x implementation is allowed to implement features from v3.(x+1). Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20200728150815.11446-12-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 9ae7d97fafd..fa3c088972e 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -55,6 +55,7 @@ REG32(IDR1, 0x4) REG32(IDR2, 0x8) REG32(IDR3, 0xc) FIELD(IDR3, HAD, 2, 1); + FIELD(IDR3, RIL, 10, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b262f0e4a74..0122700e725 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -254,6 +254,7 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, HAD, 1); =20 /* 4K and 64K granule support */ --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262651; cv=none; d=zohomail.com; s=zohoarc; b=L90ew1Szada7A14dVgOAlfb53TDE085rRxVzGQ8UxHG/bAliCngc/Gsa4t0BNr/ZzoO23aZValg07IEmi3Hc8qP4waHYnRM/AJgB5r1tgNws0U4HrMGM1cTd5oHX05a3OGkVu2a00h0nOfo3K4dpSvBSvyuBDgcdnM8cmhEMMg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262651; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nj/jVd48Yy5aWXuxg27tOObzp4JLkxMOKbL7+qjvNT8=; b=fI5T6x90JCS5tuQ5ry5eaDGM+bHpIqvAS3kz/nNwiu9DNbhkdSHYaXzcP2mRAHzwt36M5D5/jaxFRfJKSeU9T4KR1ZXF3fGCmWK9J9MZpToCOQ7oywh5kSVOl6NFlmsIJHSaXUNXfxbF9g/mrV+uJezhh6k8/10x+LEmmG1lGSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262651742303.99136348377806; Mon, 24 Aug 2020 02:50:51 -0700 (PDT) Received: from localhost ([::1]:40596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA97q-0001JU-DA for importer@patchew.org; Mon, 24 Aug 2020 05:50:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95e-00056J-1Q for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:34 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:35030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95a-0004nl-Jk for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:33 -0400 Received: by mail-wr1-x444.google.com with SMTP id b17so7217696wru.2 for ; Mon, 24 Aug 2020 02:48:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nj/jVd48Yy5aWXuxg27tOObzp4JLkxMOKbL7+qjvNT8=; b=Lw8I+PcTCJaQxUJUkvIA9teZ8/4b2LgVodn6EnSF8HXKsDIGI/BlCXfbYo1HzdRp1T 0U6pKr05xyv8gopfs8geB4lty81gkgdJDjwmNo4qeeFtzTiJUuh0kkXaobuu4v/pWtr5 lkUUtKQ48xn77vLaXqg0fuO2EGZsdsiO6LpncALVq6fKr4hOXBgBAsSXHCXnFnf227wF 98tyb5kobzT6QhnkiXxTM9avymz+UsH2033PPLymyN4qPC7Eb7s6Is5zknCkaa05yu0k 8UAjX6v6d8tyVBUPOaW5GzoNEdYwVooP401zYLF1i2tyDBQs0eU/4jJrJQoPuDlulP+w fb6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nj/jVd48Yy5aWXuxg27tOObzp4JLkxMOKbL7+qjvNT8=; b=G1s02of+Mk6FHz88fiB3Y/+4uAcYawvyAw1W349Nikhr2pfJCOjRBPl568v2k+hS0U XEtPpvbSbimn8EbaLWLjPnvgg3IZ0PluGJTI3rsLFh8KSg2O/nY1g5w9J12tqM5V9hxE byuMAaOKX2YKeO2AhtwCjDODBGg1r5REau4/VnII87Mz8/q5/o9FtQoWsUqMhe9dXV5x oA81kMsB5R9I5k/Os4X1PjBP3uw8hdbG+md5V143OBIVNZX0x8F5bDzrXVYwHOn2Z5rN 74TSVwuC49YjMm7EEQzfahGUF1lmcOXM970nWy5JFCz/41sHFLP/rJhWxU1WJedIVMOM Oavg== X-Gm-Message-State: AOAM531qaDBOSU1SguOzi4dex/n3fnrYoZUutFONukbpJBnLuGhLiNtN E4QMNXClSvhjjufGuS+mX6tSY7k+YOUw9s/m X-Google-Smtp-Source: ABdhPJzAEFMZBW5DdSBcAaK3tYEUt88dsoORNFgCz6cajvAYK2J9c8p16vCsTk9//YUZxay2vU+3Mg== X-Received: by 2002:adf:f007:: with SMTP id j7mr4745958wro.195.1598262508816; Mon, 24 Aug 2020 02:48:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/27] docs/system/arm: Document the Xilinx Versal Virt board Date: Mon, 24 Aug 2020 10:47:57 +0100 Message-Id: <20200824094811.15439-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Document the Xilinx Versal Virt board. Signed-off-by: Edgar E. Iglesias Message-id: 20200803164749.301971-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/xlnx-versal-virt.rst | 176 +++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 3 +- 3 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 docs/system/arm/xlnx-versal-virt.rst diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-ve= rsal-virt.rst new file mode 100644 index 00000000000..2602d0f9953 --- /dev/null +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -0,0 +1,176 @@ +Xilinx Versal Virt (``xlnx-versal-virt``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Xilinx Versal is a family of heterogeneous multi-core SoCs +(System on Chip) that combine traditional hardened CPUs and I/O +peripherals in a Processing System (PS) with runtime programmable +FPGA logic (PL) and an Artificial Intelligence Engine (AIE). + +More details here: +https://www.xilinx.com/products/silicon-devices/acap/versal.html + +The family of Versal SoCs share a single architecture but come in +different parts with different speed grades, amounts of PL and +other differences. + +The Xilinx Versal Virt board in QEMU is a model of a virtual board +(does not exist in reality) with a virtual Versal SoC without I/O +limitations. Currently, we support the following cores and devices: + +Implemented CPU cores: + +- 2 ACPUs (ARM Cortex-A72) + +Implemented devices: + +- Interrupt controller (ARM GICv3) +- 2 UARTs (ARM PL011) +- An RTC (Versal built-in) +- 2 GEMs (Cadence MACB Ethernet MACs) +- 8 ADMA (Xilinx zDMA) channels +- 2 SD Controllers +- OCM (256KB of On Chip Memory) +- DDR memory + +QEMU does not yet model any other devices, including the PL and the AI Eng= ine. + +Other differences between the hardware and the QEMU model: + +- QEMU allows the amount of DDR memory provided to be specified with the + ``-m`` argument. If a DTB is provided on the command line then QEMU will + edit it to include suitable entries describing the Versal DDR memory ran= ges. + +- QEMU provides 8 virtio-mmio virtio transports; these start at + address ``0xa0000000`` and have IRQs from 111 and upwards. + +Running +""""""" +If the user provides an Operating System to be loaded, we expect users +to use the ``-kernel`` command line option. + +Users can load firmware or boot-loaders with the ``-device loader`` option= s. + +When loading an OS, QEMU generates a DTB and selects an appropriate address +where it gets loaded. This DTB will be passed to the kernel in register x0. + +If there's no ``-kernel`` option, we generate a DTB and place it at 0x1000 +for boot-loaders or firmware to pick it up. + +If users want to provide their own DTB, they can use the ``-dtb`` option. +These DTBs will have their memory nodes modified to match QEMU's +selected ram_size option before they get passed to the kernel or FW. + +When loading an OS, we turn on QEMU's PSCI implementation with SMC +as the PSCI conduit. When there's no ``-kernel`` option, we assume the user +provides EL3 firmware to handle PSCI. + +A few examples: + +Direct Linux boot of a generic ARM64 upstream Linux kernel: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \ + -serial mon:stdio -display none \ + -kernel arch/arm64/boot/Image \ + -nic user -nic user \ + -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0 \ + -drive if=3Dnone,index=3D0,file=3Dhd0.qcow2,id=3Dhd0,snapshot \ + -drive file=3Dqemu_sd.qcow2,if=3Dsd,index=3D0,snapshot \ + -device virtio-blk-device,drive=3Dhd0 -append root=3D/dev/vda + +Direct Linux boot of PetaLinux 2019.2: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \ + -serial mon:stdio -display none \ + -kernel petalinux-v2019.2/Image \ + -append "rdinit=3D/sbin/init console=3DttyAMA0,115200n8 earlycon=3Dp= l011,mmio,0xFF000000,115200n8" \ + -net nic,model=3Dcadence_gem,netdev=3Dnet0 -netdev user,id=3Dnet0 \ + -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ + -object rng-random,filename=3D/dev/urandom,id=3Drng0 + +Boot PetaLinux 2019.2 via ARM Trusted Firmware (2018.3 because the 2019.2 +version of ATF tries to configure the CCI which we don't model) and U-boot: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \ + -serial stdio -display none \ + -device loader,file=3Dpetalinux-v2018.3/bl31.elf,cpu-num=3D0 \ + -device loader,file=3Dpetalinux-v2019.2/u-boot.elf \ + -device loader,addr=3D0x20000000,file=3Dpetalinux-v2019.2/Image \ + -nic user -nic user \ + -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ + -object rng-random,filename=3D/dev/urandom,id=3Drng0 + +Run the following at the U-Boot prompt: + +.. code-block:: bash + + Versal> + fdt addr $fdtcontroladdr + fdt move $fdtcontroladdr 0x40000000 + fdt set /timer clock-frequency <0x3dfd240> + setenv bootargs "rdinit=3D/sbin/init maxcpus=3D1 console=3DttyAMA0,11520= 0n8 earlycon=3Dpl011,mmio,0xFF000000,115200n8" + booti 20000000 - 40000000 + fdt addr $fdtcontroladdr + +Boot Linux as DOM0 on Xen via U-Boot: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \ + -serial stdio -display none \ + -device loader,file=3Dpetalinux-v2019.2/u-boot.elf,cpu-num=3D0 \ + -device loader,addr=3D0x30000000,file=3Dlinux/2018-04-24/xen \ + -device loader,addr=3D0x40000000,file=3Dpetalinux-v2019.2/Image \ + -nic user -nic user \ + -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ + -object rng-random,filename=3D/dev/urandom,id=3Drng0 + +Run the following at the U-Boot prompt: + +.. code-block:: bash + + Versal> + fdt addr $fdtcontroladdr + fdt move $fdtcontroladdr 0x20000000 + fdt set /timer clock-frequency <0x3dfd240> + fdt set /chosen xen,xen-bootargs "console=3Ddtuart dtuart=3D/uart@ff0000= 00 dom0_mem=3D640M bootscrub=3D0 maxcpus=3D1 timer_slop=3D0" + fdt set /chosen xen,dom0-bootargs "rdinit=3D/sbin/init clk_ignore_unused= console=3Dhvc0 maxcpus=3D1" + fdt mknode /chosen dom0 + fdt set /chosen/dom0 compatible "xen,multiboot-module" + fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> + booti 30000000 - 20000000 + +Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \ + -serial stdio -display none \ + -device loader,file=3Dpetalinux-v2018.3/bl31.elf,cpu-num=3D0 \ + -device loader,file=3Dpetalinux-v2019.2/u-boot.elf \ + -device loader,addr=3D0x30000000,file=3Dlinux/2018-04-24/xen \ + -device loader,addr=3D0x40000000,file=3Dpetalinux-v2019.2/Image \ + -nic user -nic user \ + -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ + -object rng-random,filename=3D/dev/urandom,id=3Drng0 + +Run the following at the U-Boot prompt: + +.. code-block:: bash + + Versal> + fdt addr $fdtcontroladdr + fdt move $fdtcontroladdr 0x20000000 + fdt set /timer clock-frequency <0x3dfd240> + fdt set /chosen xen,xen-bootargs "console=3Ddtuart dtuart=3D/uart@ff0000= 00 dom0_mem=3D640M bootscrub=3D0 maxcpus=3D1 timer_slop=3D0" + fdt set /chosen xen,dom0-bootargs "rdinit=3D/sbin/init clk_ignore_unused= console=3Dhvc0 maxcpus=3D1" + fdt mknode /chosen dom0 + fdt set /chosen/dom0 compatible "xen,multiboot-module" + fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> + booti 30000000 - 20000000 + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 4c5b0e4aab8..afdb37e7384 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -93,6 +93,7 @@ undocumented; you can get a complete list by running arm/sx1 arm/stellaris arm/virt + arm/xlnx-versal-virt =20 Arm CPU features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/MAINTAINERS b/MAINTAINERS index 0886eb3d2b5..5a22c8be429 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -894,7 +894,7 @@ F: hw/misc/zynq* F: include/hw/misc/zynq* X: hw/ssi/xilinx_* =20 -Xilinx ZynqMP +Xilinx ZynqMP and Versal M: Alistair Francis M: Edgar E. Iglesias M: Peter Maydell @@ -905,6 +905,7 @@ F: include/hw/*/xlnx*.h F: include/hw/ssi/xilinx_spips.h F: hw/display/dpcd.c F: include/hw/display/dpcd.h +F: docs/system/arm/xlnx-versal-virt.rst =20 ARM ACPI Subsystem M: Shannon Zhao --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262939; cv=none; d=zohomail.com; s=zohoarc; b=WYXvInpGesmWG5EN8/q4ja6riFMpv5twFAlKYyoVdEhOLzuK3uQTcoPCjNf1SHzOXwXEITvymTCg/JNgjSnZUQH8Bra718S/4BaFSBYE2DgmPRIIsZQWMvKlDVMMdYypOPHNAQtM0XhCYOeEOOMmDXE2ViT6RcFDlN+2wy6P4ls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262939; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ENPtwkyypi5he8g9f/1mEPuk6rEdLo6yuawroe2Xk4k=; b=XBMeyPtzRek+9tMcDTEt2D9IdkxcBOy1yQSxiXlYy9OXrRwiiY+gezHV8P89faNvGyY9Kf0lPyOiIDaGQRSeUrJVQXCbTQShlXvmCYjFePH6N/GS8uf67TIuttgIVLYlBUWhOC8S9BD5SL6j10NUGNunh20evh4h3NinxVw195E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262939769711.3782313681301; Mon, 24 Aug 2020 02:55:39 -0700 (PDT) Received: from localhost ([::1]:37036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9CU-0002pw-CU for importer@patchew.org; Mon, 24 Aug 2020 05:55:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95f-0005A4-9N for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:35 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:56226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95c-0004o5-6e for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:34 -0400 Received: by mail-wm1-x341.google.com with SMTP id a65so4085549wme.5 for ; Mon, 24 Aug 2020 02:48:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ENPtwkyypi5he8g9f/1mEPuk6rEdLo6yuawroe2Xk4k=; b=xbn2VoBYCVxWm5yx1MMTM96JTInDji+JjG8grJOLkMWlv4g0hnGONfupP9DeVW1bIN yxjVFdAwzotzGONnekQWwXVXRox6uuVMVaLSp+6Wu48TfXGt1ikgYJIu3ud1NGKBWpZS emJRSbU8lVXdXXwtdz38ZOZtKp19fbSLRHsEV74Zr5GAZpxiRATgKE18cUpv83KktOZv ybbM2a0XR4fPU5kViJgVPfctHYN1mohHRDDGmtos6CBr3J3X065fzaWtmGeQ76eB5INA xW2os708+Wnp2WbsAq0/Zia6DFuA6eTtsl96A62zhbdV+RIXkSxvIRHuYIvdPYNi+sdT DsuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ENPtwkyypi5he8g9f/1mEPuk6rEdLo6yuawroe2Xk4k=; b=dakbNIa3tm0gIimITZz9EFAnedR9pHuZGh8tvOgHHqvFS/LzK7yPrRbGiUGe0pOYh+ zKeK378IZY8swIDm9NwSWKEmvc34HCZrJS81QwfpIj/XXkSqy8rjwiiWH6fNXF3t2VOi jxhhvHJemiVtOg4VicevSZTiNYAqikE61ykiNWq+RxIPdCtXMaRHB3gdJfkUBxXo/MQW UwadGMjWlCm2vnnhMDFUvD1BcDsiqfkjja/P9kBSxRTqG4zm06wdXf276nLICU135KoT gjoVzgdydVjJTI4U6Q3ghW16g0GVg0dtiAfhuOuJM9OrYmpW9E3xw8Mr4mjUJTGoIROJ 7JJQ== X-Gm-Message-State: AOAM531vhHCS2DZmJq7a8bk5McdkOhxd87oz2AIFvWwGKbvl1/1MjbPS gi0mQHXc4m6sJUl+I6uSBJr4bw9Vp5c+pDIa X-Google-Smtp-Source: ABdhPJzlQtpYTjfhrEad08FmCjj7F5AeaNYurLTSpGbILNUSW10oGEcGihVnpTDN4Dp7f41RD5dPjw== X-Received: by 2002:a1c:4c06:: with SMTP id z6mr4819145wmf.21.1598262510480; Mon, 24 Aug 2020 02:48:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/27] target/arm: Pull handling of XScale insns out of disas_coproc_insn() Date: Mon, 24 Aug 2020 10:47:58 +0100 Message-Id: <20200824094811.15439-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" At the moment we check for XScale/iwMMXt insns inside disas_coproc_insn(): for CPUs with ARM_FEATURE_XSCALE all copro insns with cp 0 or 1 are handled specially. This works, but is an odd place for this check, because disas_coproc_insn() is called from both the Arm and Thumb decoders but the XScale case never applies for Thumb (all the XScale CPUs were ARMv5, which has only Thumb1, not Thumb2 with the 32-bit coprocessor insn encodings). It also makes it awkward to convert the real copro access insns to decodetree. Move the identification of XScale out to its own function which is only called from disas_arm_insn(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-2-peter.maydell@linaro.org --- target/arm/translate.c | 44 ++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 556588d92fe..99663236aa9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4551,20 +4551,6 @@ static int disas_coproc_insn(DisasContext *s, uint32= _t insn) =20 cpnum =3D (insn >> 8) & 0xf; =20 - /* First check for coprocessor space used for XScale/iwMMXt insns */ - if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { - if (extract32(s->c15_cpar, cpnum, 1) =3D=3D 0) { - return 1; - } - if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { - return disas_iwmmxt_insn(s, insn); - } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { - return disas_dsp_insn(s, insn); - } - return 1; - } - - /* Otherwise treat as a generic register access */ is64 =3D (insn & (1 << 25)) =3D=3D 0; if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { /* cdp */ @@ -4823,6 +4809,23 @@ static int disas_coproc_insn(DisasContext *s, uint32= _t insn) return 1; } =20 +/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ +static void disas_xscale_insn(DisasContext *s, uint32_t insn) +{ + int cpnum =3D (insn >> 8) & 0xf; + + if (extract32(s->c15_cpar, cpnum, 1) =3D=3D 0) { + unallocated_encoding(s); + } else if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { + if (disas_iwmmxt_insn(s, insn)) { + unallocated_encoding(s); + } + } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { + if (disas_dsp_insn(s, insn)) { + unallocated_encoding(s); + } + } +} =20 /* Store a 64-bit value to a register pair. Clobbers val. */ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 = val) @@ -8270,15 +8273,26 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0xc: case 0xd: case 0xe: - if (((insn >> 8) & 0xe) =3D=3D 10) { + { + /* First check for coprocessor space used for XScale/iwMMXt insns = */ + int cpnum =3D (insn >> 8) & 0xf; + + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { + disas_xscale_insn(s, insn); + break; + } + + if ((cpnum & 0xe) =3D=3D 10) { /* VFP, but failed disas_vfp. */ goto illegal_op; } + if (disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } break; + } default: illegal_op: unallocated_encoding(s); --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262740; cv=none; d=zohomail.com; s=zohoarc; b=USpYaQB3NprWN9xyCQgT741L/vGNanY3vlpbtJ5kr/2zo0OPmA3x3ky321pZadHIzMrNHYPsoLNZktf5FBxRNE5IjoNzHBx9tivNdPxklICZciVYS9yovAkV6iPbnfZ/up/tSiIU9la2Q6Rfo7XgZAQ/u0n8ADhhDz1CWyh5b34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262740; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ers+2j+PuXTXZBmM5L2AbHjg4xxB43Gsae3bEhiWv7U=; b=Qpve/rjU81IrCIPvVTdzxoHBFi9SV7vDoQ0cuxR7AI0BbwYyAtp4UE4FP7Ise2XGWvWG/hp5DXiV4d/di/N/agvesc35IFGddK8rzc5QCoIMtV8xFgJF8pQxjZcygBgvlEPyEisLhEhdW0b9bElpRqi3D21dXs+5l63O0qkeo68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262740628968.4919010849195; Mon, 24 Aug 2020 02:52:20 -0700 (PDT) Received: from localhost ([::1]:48826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA99H-0004ch-C6 for importer@patchew.org; Mon, 24 Aug 2020 05:52:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95f-0005Ae-GJ for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:35 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95d-0004oE-L2 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:35 -0400 Received: by mail-wm1-x344.google.com with SMTP id u18so7678332wmc.3 for ; Mon, 24 Aug 2020 02:48:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ers+2j+PuXTXZBmM5L2AbHjg4xxB43Gsae3bEhiWv7U=; b=GwOThDNJxE+MXtMBO/W6ShAW7d3zawWWujDY2vR7uiL8IICRgU4v4ViRwjgI9Gdz88 olB7u5KMEQ2o+9C4yuBt1xsJLpIv59Dy36WMqdhUkjsO4hw1renXLamuWTUfVKGbUkvM 7SRAB2xAYr71hG5x8OuxJzCBDhGYVvLgGTIb3qsGXLW0soUIQ+67jqnl1jwihV1IUrUs /w5SVxbuBZjXWtQlv2Mu5o/QhMQONNdC9dOL86zvG3qev8KVQzjoE2podWUZpFmAdzhr 4fc8AV3JszUHa4SKuGUIHKT9U3DsG8Q1QC7F9AHkLgRi0uYtJQQv9JbFvXHkWEkppM7V czYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ers+2j+PuXTXZBmM5L2AbHjg4xxB43Gsae3bEhiWv7U=; b=oQ/CQl1DcEmCahz1JwOJsMPkOYwFZIY1JZznN6oM9HUJO357antgX8nE/A008heLGt ryPB65TnKrK9RwCiN3XD5sZ4ifonMdbtaPS1Dp44nlyAurNTQtDoYZpdOyF9FT47AwBF hzgL8rHPyW5+kRz+Oe9OkQ8z9Nrs1v9VTMo/OfG/hlssktTh+zwbwyUcrAA7CnP4d531 8tt42WIEih7x7toCq3g7pPrvBjrNZCUJpSRIv3CK+jlh0JPgDrE7GFDHMZeVlGYXMiUb HMaSyDKUGbFMLZGkX8AQ7t8Q0QRQo9da/3SC6KJd4DPhtCfrEzIM8b9nRoLdATZFyOYj HE7w== X-Gm-Message-State: AOAM5318AtwF5rC7nGD3ZYDWwp5ZgsA22gDwHOzjZiig5Co4NJOq8qUW K88bpgq79G/StZhxoiqr8cwkWRppkTPMb9Zc X-Google-Smtp-Source: ABdhPJyCLH2nsnVGVsTlixf7UT7qUUaAESanCIIAEzEKQqmu8wlrgUIM/raNsfmGvf3eZixGCKRu2Q== X-Received: by 2002:a1c:81cb:: with SMTP id c194mr4985684wmd.45.1598262511754; Mon, 24 Aug 2020 02:48:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/27] target/arm: Separate decode from handling of coproc insns Date: Mon, 24 Aug 2020 10:47:59 +0100 Message-Id: <20200824094811.15439-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" As a prelude to making coproc insns use decodetree, split out the part of disas_coproc_insn() which does instruction decoding from the part which does the actual work, and make do_coproc_insn() handle the UNDEF-on-bad-permissions and similar cases itself rather than returning 1 to eventually percolate up to a callsite that calls unallocated_encoding() for it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-3-peter.maydell@linaro.org --- target/arm/translate.c | 76 ++++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 99663236aa9..01591f0e325 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4544,34 +4544,12 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, = uint32_t rn_ofs, tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } =20 -static int disas_coproc_insn(DisasContext *s, uint32_t insn) +static void do_coproc_insn(DisasContext *s, int cpnum, int is64, + int opc1, int crn, int crm, int opc2, + bool isread, int rt, int rt2) { - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; const ARMCPRegInfo *ri; =20 - cpnum =3D (insn >> 8) & 0xf; - - is64 =3D (insn & (1 << 25)) =3D=3D 0; - if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { - /* cdp */ - return 1; - } - - crm =3D insn & 0xf; - if (is64) { - crn =3D 0; - opc1 =3D (insn >> 4) & 0xf; - opc2 =3D 0; - rt2 =3D (insn >> 16) & 0xf; - } else { - crn =3D (insn >> 16) & 0xf; - opc1 =3D (insn >> 21) & 7; - opc2 =3D (insn >> 5) & 7; - rt2 =3D 0; - } - isread =3D (insn >> 20) & 1; - rt =3D (insn >> 12) & 0xf; - ri =3D get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { @@ -4579,7 +4557,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) =20 /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { - return 1; + unallocated_encoding(s); + return; } =20 if (s->hstr_active || ri->accessfn || @@ -4653,14 +4632,15 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) /* Handle special cases first */ switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { case ARM_CP_NOP: - return 0; + return; case ARM_CP_WFI: if (isread) { - return 1; + unallocated_encoding(s); + return; } gen_set_pc_im(s, s->base.pc_next); s->base.is_jmp =3D DISAS_WFI; - return 0; + return; default: break; } @@ -4720,7 +4700,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) /* Write */ if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ - return 0; + return; } =20 if (is64) { @@ -4786,7 +4766,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) gen_lookup_tb(s); } =20 - return 0; + return; } =20 /* Unknown register; this might be a guest error or a QEMU @@ -4806,7 +4786,39 @@ static int disas_coproc_insn(DisasContext *s, uint32= _t insn) s->ns ? "non-secure" : "secure"); } =20 - return 1; + unallocated_encoding(s); + return; +} + +static int disas_coproc_insn(DisasContext *s, uint32_t insn) +{ + int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; + + cpnum =3D (insn >> 8) & 0xf; + + is64 =3D (insn & (1 << 25)) =3D=3D 0; + if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { + /* cdp */ + return 1; + } + + crm =3D insn & 0xf; + if (is64) { + crn =3D 0; + opc1 =3D (insn >> 4) & 0xf; + opc2 =3D 0; + rt2 =3D (insn >> 16) & 0xf; + } else { + crn =3D (insn >> 16) & 0xf; + opc1 =3D (insn >> 21) & 7; + opc2 =3D (insn >> 5) & 7; + rt2 =3D 0; + } + isread =3D (insn >> 20) & 1; + rt =3D (insn >> 12) & 0xf; + + do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2); + return 0; } =20 /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263027; cv=none; d=zohomail.com; s=zohoarc; b=hx7fyDHffFwfmLB9z0fjTAZpZKuJIJmfYCsqi7B0tqRG7otOkjgxnlMCi7I4j+xix/0ELP9VM3R3X8nqTC0v0PaqdxumiDgMYYAZYEDO5ComegNw7vJDeaIPeLPK+6GtlXk5wrdAzN94T0ociVezZ5uIFm0WsXS5L7b2u+zrLiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263027; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zyrZv9ZwHPgzmB6CFFHtEKiJ8fWKyvVsLI46g+5LD/g=; b=QL3OMzItLjU/MwvZR8Mpjvz0vvBuGP16dd3oZ+sp2Jfx695vKb+AnDkIPETw+H12hi4nKqnj40VjjaLjEhOe4ez1jSCS0UtZjDiF0P1nhw63fWIyReoZuzx9+pOE69sTwlQix9kfszAEiRsmpyqw/twWVDH6tMI3IpbIG4QtKPM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263026981504.9761579734686; Mon, 24 Aug 2020 02:57:06 -0700 (PDT) Received: from localhost ([::1]:44176 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9Dt-0005n7-Gd for importer@patchew.org; Mon, 24 Aug 2020 05:57:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95g-0005Ee-Vf for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:36 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:36867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95e-0004oV-Ma for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:36 -0400 Received: by mail-wr1-x434.google.com with SMTP id y3so7988706wrl.4 for ; Mon, 24 Aug 2020 02:48:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zyrZv9ZwHPgzmB6CFFHtEKiJ8fWKyvVsLI46g+5LD/g=; b=JZn6WpwsAEvHvSfxNU4WJDA2cIPQZr1a6yHE0Ewb0QV1vSxHP2UisBDwidU7cZSCFi 7lLlQdvqi9PIDvbIHM2xRYRy7rlHrDsqlo/9VreeqnYwZ2TnERjIx8cPU+6VEkM61vEq zi/EZCUquGZtHHtIsl8LjLH70oeujGg6BIk6CujgpqbpWmh21JQ41LVDKbWzGCtkp01/ oqbEe0QBCpwBkYEnIpcA7uzbHrwta//QGZWbAREiNxJfvyJMKaY6hrgZxVQWo9Z8B8bW rWz0CpZW+eUQHyiaYuymmDcp+Qm84CtxJT/RKbAuVickrmozKmPpSGnFK8MiQkf750n2 n2Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zyrZv9ZwHPgzmB6CFFHtEKiJ8fWKyvVsLI46g+5LD/g=; b=fS2Y8+JVOeTjmtWrk6Pf8Aa/YUqEpYwqIhA9XG3zyBlsRrfmK9KQlIKXWFM5EmPjD/ DmSZnq6VvkGYZkPGgCSK6oIgaZx5b1b/eeJOq+55L+EYbJjFuLr+O/QoCQuPKTIfs9g6 uzZvmxmCvRxEzfDPY5CLaFBbSBFsm7hpRIAPVG/cdO7nZjUQCXMeuRN2z8O7SrtovOIz se7CXKeidkB2xuS4z6WxWXNnnE9jv0FPC03NabF3owCFFcq7a/n7uW8NDicynOEW+KIp UTO9tcLfP5L57wigJHPdsOV1rZcZl16MFmtP9hJg4N6lie772rUo13IHuHmfAZI7/vT+ sftw== X-Gm-Message-State: AOAM533+cmqI+RMuy9h74XOKGD077ugNNDcDsXaQO4e1gHL6QcbtpeQk g8MbA7tCgw4ZlJyaKXPVo+ZQoZBsvtHLbG2R X-Google-Smtp-Source: ABdhPJyb4MIhBHsrYpA4tUgBQ1h8IapAFU8ffaWxvj0WClgDaIOSOkpwa6CByTfsY8/Oqet05+t0AQ== X-Received: by 2002:a5d:45c8:: with SMTP id b8mr736132wrs.381.1598262512849; Mon, 24 Aug 2020 02:48:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/27] target/arm: Convert A32 coprocessor insns to decodetree Date: Mon, 24 Aug 2020 10:48:00 +0100 Message-Id: <20200824094811.15439-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the A32 coprocessor instructions to decodetree. Note that this corrects an underdecoding: for the 64-bit access case (MRRC/MCRR) we did not check that bits [24:21] were 0b0010, so we would incorrectly treat LDC/STC as MRRC/MCRR rather than UNDEFing them. The decodetree versions of these insns assume the coprocessor is in the range 0..7 or 14..15. This is architecturally sensible (as per the comments) and OK in practice for QEMU because the only uses of the ARMCPRegInfo infrastructure we have that aren't for coprocessors 14 or 15 are the pxa2xx use of coprocessor 6. We add an assertion to the define_one_arm_cp_reg_with_opaque() function to catch any accidental future attempts to use it to define coprocessor registers for invalid coprocessors. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-4-peter.maydell@linaro.org --- target/arm/a32.decode | 19 +++++++++++ target/arm/helper.c | 29 +++++++++++++++++ target/arm/translate.c | 74 +++++++++++++++++++++++++++++++++++------- 3 files changed, 111 insertions(+), 11 deletions(-) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 0bd952c0692..4dfd9139bf3 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -47,6 +47,8 @@ &bfi rd rn lsb msb &sat rd rn satimm imm sh &pkh rd rn rm imm tb +&mcr cp opc1 crn crm opc2 rt +&mcrr cp opc1 crm rt rt2 =20 # Data-processing (register) =20 @@ -529,6 +531,23 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:= 16 &ldst_block B .... 1010 ........................ @branch BL .... 1011 ........................ @branch =20 +# Coprocessor instructions + +# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the +# other coprocessor instructions always UNDEF. +# The trans_ functions for these will ignore cp values 8..13 for v7 or +# earlier, and 0..13 for v8 and later, because those areas of the +# encoding space may be used for other things, such as VFP or Neon. + +@mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr +@mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr + +MCRR .... 1100 0100 .... .... .... .... .... @mcrr +MRRC .... 1100 0101 .... .... .... .... .... @mcrr + +MCR .... 1110 ... 0 .... .... .... ... 1 .... @mcr +MRC .... 1110 ... 1 .... .... .... ... 1 .... @mcr + # Supervisor call =20 SVC ---- 1111 imm:24 &i diff --git a/target/arm/helper.c b/target/arm/helper.c index 455c92b8915..6b4f0eb5334 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8462,6 +8462,35 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + /* + * This API is only for Arm's system coprocessors (14 and 15) or + * (M-profile or v7A-and-earlier only) for implementation defined + * coprocessors in the range 0..7. Our decode assumes this, since + * 8..13 can be used for other insns including VFP and Neon. See + * valid_cp() in translate.c. Assert here that we haven't tried + * to use an invalid coprocessor number. + */ + switch (r->state) { + case ARM_CP_STATE_BOTH: + /* 0 has a special meaning, but otherwise the same rules as AA32. = */ + if (r->cp =3D=3D 0) { + break; + } + /* fall through */ + case ARM_CP_STATE_AA32: + if (arm_feature(&cpu->env, ARM_FEATURE_V8) && + !arm_feature(&cpu->env, ARM_FEATURE_M)) { + assert(r->cp >=3D 14 && r->cp <=3D 15); + } else { + assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); + } + break; + case ARM_CP_STATE_AA64: + assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); + break; + default: + g_assert_not_reached(); + } /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 * encodes a minimum access level for the register. We roll this * runtime check into our general permission check code, so check diff --git a/target/arm/translate.c b/target/arm/translate.c index 01591f0e325..6ee920eec53 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5237,6 +5237,68 @@ static int t16_pop_list(DisasContext *s, int x) #include "decode-t32.c.inc" #include "decode-t16.c.inc" =20 +static bool valid_cp(DisasContext *s, int cp) +{ + /* + * Return true if this coprocessor field indicates something + * that's really a possible coprocessor. + * For v7 and earlier, coprocessors 8..15 were reserved for Arm use, + * and of those only cp14 and cp15 were used for registers. + * cp10 and cp11 were used for VFP and Neon, whose decode is + * dealt with elsewhere. With the advent of fp16, cp9 is also + * now part of VFP. + * For v8A and later, the encoding has been tightened so that + * only cp14 and cp15 are valid, and other values aren't considered + * to be in the coprocessor-instruction space at all. v8M still + * permits coprocessors 0..7. + */ + if (arm_dc_feature(s, ARM_FEATURE_V8) && + !arm_dc_feature(s, ARM_FEATURE_M)) { + return cp >=3D 14; + } + return cp < 8 || cp >=3D 14; +} + +static bool trans_MCR(DisasContext *s, arg_MCR *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, + false, a->rt, 0); + return true; +} + +static bool trans_MRC(DisasContext *s, arg_MRC *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, + true, a->rt, 0); + return true; +} + +static bool trans_MCRR(DisasContext *s, arg_MCRR *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, + false, a->rt, a->rt2); + return true; +} + +static bool trans_MRRC(DisasContext *s, arg_MRRC *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, + true, a->rt, a->rt2); + return true; +} + /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) { @@ -8293,17 +8355,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) disas_xscale_insn(s, insn); break; } - - if ((cpnum & 0xe) =3D=3D 10) { - /* VFP, but failed disas_vfp. */ - goto illegal_op; - } - - if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ - goto illegal_op; - } - break; + /* fall through */ } default: illegal_op: --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262840; cv=none; d=zohomail.com; s=zohoarc; b=F/h7SwRWmSaWWMCFghAqeeRlD+Af7VJBolzcXDH9UF5xfq9BZM2gLMVibtGM8GPMUxB63RYOs5UJmC+X5bMxpgpiTD7fjL4VMTCN6OfsWl7tJ5Ypp61c89f36fR46dhTCL2gGchLVmK+rFWiESi7Res1+h2oSsw5YjFgFUgtBWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262840; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zQb4tl+pl+QQR0fGrgrVlmupRVf20x7rz7QGSNEoC2Q=; b=AhMB8dgzTmT6keETaSPJY+mCdespcAnAYI5dtBhp9QDXLJV6f1LmJUDM8RrFOgUVdVcyVFDzCC5YnzKG7rd4luXIaGm/bXY66W74rlnRSMpAmYgdhABZ8w38wfHOxs+Ds3Cr9BuMmQsHrkb4BbMo3q8nGzj+cd1TBb8aI4zIY+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262840780916.8712780112429; Mon, 24 Aug 2020 02:54:00 -0700 (PDT) Received: from localhost ([::1]:57160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9At-0007zV-HE for importer@patchew.org; Mon, 24 Aug 2020 05:53:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95h-0005GE-FM for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:37 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:39168) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95f-0004oh-Oo for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:37 -0400 Received: by mail-wm1-x329.google.com with SMTP id g75so7525423wme.4 for ; Mon, 24 Aug 2020 02:48:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zQb4tl+pl+QQR0fGrgrVlmupRVf20x7rz7QGSNEoC2Q=; b=FO2o6tuIwP5vs5bt5twZZz05/tJukZ5wgONKegeSipg46qnPYSS0xU9glbW9EJxTq8 n+5PrIvWAr1sonLAoobbid/W063/svVS+5B5yTtpf/xmQLJ2SJ5g//7W1VQcr69bApYF gYTYSvU59QggRe5Mbhcc7kqn2WFIjpjJyWTd1N4iIr55Oufew6gijeU1W6YUJ8f2YzdW qt/YOSdj5RTZvRFbeXE833bRXmWAr8byGjTO2qleexMm5dpF6S6Y0/zdj54UrY5tG74r t7aTUCL84gLwK/4c7ejr17SmPpq5SzZ+GJGrmOD6lxHZnqw6q3PAVH06gugsZ+L6gyr2 vkjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zQb4tl+pl+QQR0fGrgrVlmupRVf20x7rz7QGSNEoC2Q=; b=opxlJnXsgVJ9/ErRyjaN6whaNTFlSNZ+RJIvUnemOEy3y9cIO8ORyh4OIr0kGHufga N0EmweooqS9K0ozKFfInne0ev3VNsYxFobG/MWCV3dXsCViGvA8Z+63ovKCD2FGxv1cz /49G9zTXG+DuG/E8C99Be9ijyqh5ijgW9b9KTlEmWsKJ43b1HJHCEiAA4LcbWksF346f moq7Cm5ke1MRmfRvHMnOwCFfJoYLr1o3xibmm0BftGOcTIF1uJPAIGc4SIiAnlZbVjdp nTp9d1IGI5MYAqw4MjQMwAEAmB4Gn3/F1Q3c9og/QFkwV7zWFUuErm2L+3YgW+ypDw7B HGOQ== X-Gm-Message-State: AOAM531Am2+HV1YCUdGlWeMAm+dYOOXNGW7go6yjsNypYAGrRuKEkGzP h6VQgFpJ/0OJGyWJPpn/Apb12BqBNSa8Fchs X-Google-Smtp-Source: ABdhPJxf+L8allWN1Iepi1YJF20WSnIYkPcPmMZIv9a2vd9aDHBBk3iDta6gICGRF1wx8GcnT7XB3Q== X-Received: by 2002:a1c:5455:: with SMTP id p21mr1784156wmi.146.1598262514108; Mon, 24 Aug 2020 02:48:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/27] target/arm: Tidy up disas_arm_insn() Date: Mon, 24 Aug 2020 10:48:01 +0100 Message-Id: <20200824094811.15439-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The only thing left in the "legacy decoder" is the handling of disas_xscale_insn(), and we can simplify the code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-5-peter.maydell@linaro.org --- target/arm/translate.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6ee920eec53..362d1cc50fb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8342,26 +8342,18 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) return; } /* fall back to legacy decoder */ - - switch ((insn >> 24) & 0xf) { - case 0xc: - case 0xd: - case 0xe: - { - /* First check for coprocessor space used for XScale/iwMMXt insns = */ - int cpnum =3D (insn >> 8) & 0xf; - - if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { + /* TODO: convert xscale/iwmmxt decoder to decodetree ?? */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { + if (((insn & 0x0c000e00) =3D=3D 0x0c000000) + && ((insn & 0x03000000) !=3D 0x03000000)) { + /* Coprocessor insn, coprocessor 0 or 1 */ disas_xscale_insn(s, insn); - break; + return; } - /* fall through */ - } - default: - illegal_op: - unallocated_encoding(s); - break; } + +illegal_op: + unallocated_encoding(s); } =20 static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t ins= n) --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262783; cv=none; d=zohomail.com; s=zohoarc; b=GGa4c2dty1lj0s05u4w5CGmbSteUswHUpd285XYpHWXk52/halfJK8zJUMGxotq73Auj7IXBqN+VFPvr3GJHrMI6Nb/AEO9Z8s7zTa1GZPLJaAoO3ocujLLUqGBcerjJjUHw5fwOXTYSrdsfcK0I758lUlD400M6uVuqrw/MBN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262783; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bicHsrkJoIe9jeaWg/9f6nFp7gIOjDehttwEI0gLG2o=; b=LvIXE7gTOxbiv9yQd1DACjCl2Vz1k3l4BWEup8PchZXTggi2qNBwrgYvlY14edTbw0ry6SLT4mnyQy98yG6i44X2UhN3tDSSRCA2cnRYceM9qXC7jHzFxhR6SZynwPs0/LOU7KVr+8sbPyS05d/8nwPNIw0K8PQUdXoIwWmAQmQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262783973148.93241161229116; Mon, 24 Aug 2020 02:53:03 -0700 (PDT) Received: from localhost ([::1]:51698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA99y-0005md-Iz for importer@patchew.org; Mon, 24 Aug 2020 05:53:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95j-0005MI-K0 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:39 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:50533) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95h-0004oy-5r for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:39 -0400 Received: by mail-wm1-x329.google.com with SMTP id t2so7449112wma.0 for ; Mon, 24 Aug 2020 02:48:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bicHsrkJoIe9jeaWg/9f6nFp7gIOjDehttwEI0gLG2o=; b=QYqi7V4vcBcgg/EE2vIm6WNkSj0Sj7Jg/Wheh/USsydsRiV5l0rDiznxd7yG+8tyyF 3KfOlH0s666gNC/YUDY+/4/VwknpbNaVx4FTIjetFMl0qQ8YLxyZiHJkY4RD90j6CVdS JgqQGBAduNjJdZucGh6qwaMAzUOJBhzGNLBOvX8goeQ1dmq0uDkaNJRHxbeJ6/anpgFq 6MK2yI43hrq9tFqCg95gX8hpdN19yqu3O66h989tE4n6ZWHKRasusd193UGoRd+f1dhZ b1t1uyCallSEbIZMdZF1LxhqvQulX1XF8M7HlUtpC89uPazgsB3oyT4w2dsIDsx+OpVx tviA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bicHsrkJoIe9jeaWg/9f6nFp7gIOjDehttwEI0gLG2o=; b=hDXMu4OhRkq4bz8jeMUKsP8C5qZAl7tUaSUUDN+ha3EA3VXiJtTUCvnUxRk1JgoSK6 LmWNyNMGr/G9qAqScj972I8zth/lULVRDEtTS8NqqYbsriobutydp/ftmTngIJIEyU9H Wd1i9wl25ow10OzpfeBAVSGN9qhWUQy50KQ+iHk4O7HkLZ4BKEyuXfLoRYw2HJZy9qyK MEsXspudMxfdh/YeWajhiL56mKnOpALE5GzE/X+MUWUDwOesaNwj8OAE0du92QqzolXp B0kgpthwuXi1c0r9Jyxzxu8aGznKN7XdMo33jjLwCPdrQKB1yNcj6o/EnBSSp/JCJXYh GtLA== X-Gm-Message-State: AOAM532Px5HbL31eKmlNXel//n7IeicWSpNqYfQ1ur8O3mABVJqBWozW 2Ugjkporpi9v5tSqHuZ9e1vquuNqbCRSS7QU X-Google-Smtp-Source: ABdhPJwq6dZQX90WCcrEifnlxk72oCnsDWWKa7xi+PWvCQLm/nw3yyV/2uOlHcL8LpY0Ifjac2kVCA== X-Received: by 2002:a1c:9dc7:: with SMTP id g190mr3178243wme.118.1598262515274; Mon, 24 Aug 2020 02:48:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/27] target/arm: Do M-profile NOCP checks early and via decodetree Date: Mon, 24 Aug 2020 10:48:02 +0100 Message-Id: <20200824094811.15439-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For M-profile CPUs, the architecture specifies that the NOCP exception when a coprocessor is not present or disabled should cover the entire wide range of coprocessor-space encodings, and should take precedence over UNDEF exceptions. (This is the opposite of A-profile, where checking for a disabled FPU has to happen last.) Implement this with decodetree patterns that cover the specified ranges of the encoding space. There are a few instructions (VLLDM, VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must not be NOCP'd: these must be handled also in the new m-nocp.decode so they take precedence. This is a minor behaviour change: for unallocated insn patterns in the VFP area (cp=3D10,11) we will now NOCP rather than UNDEF when the FPU is disabled. As well as giving us the correct architectural behaviour for v8.1M and the recommended behaviour for v8.0M, this refactoring also removes the old NOCP handling from the remains of the 'legacy decoder' in disas_thumb2_insn(), paving the way for cleaning that up. Since we don't currently have a v8.1M feature bit or any v8.1M CPUs, the minor changes to this logic that we'll need for v8.1M are marked up with TODO comments. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-6-peter.maydell@linaro.org --- target/arm/m-nocp.decode | 42 +++++++++++++++++++++++++++ target/arm/vfp.decode | 2 -- target/arm/translate.c | 30 ++++++++++---------- target/arm/meson.build | 1 + target/arm/translate-vfp.c.inc | 52 +++++++++++++++++++++++++++------- 5 files changed, 100 insertions(+), 27 deletions(-) create mode 100644 target/arm/m-nocp.decode diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode new file mode 100644 index 00000000000..7182d7d1217 --- /dev/null +++ b/target/arm/m-nocp.decode @@ -0,0 +1,42 @@ +# M-profile UserFault.NOCP exception handling +# +# Copyright (c) 2020 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# For M-profile, the architecture specifies that NOCP UsageFaults +# should take precedence over UNDEF faults over the whole wide +# range of coprocessor-space encodings, with the exception of +# VLLDM and VLSTM. (Compare v8.1M IsCPInstruction() pseudocode and +# v8M Arm ARM rule R_QLGM.) This isn't mandatory for v8.0M but we choose +# to behave the same as v8.1M. +# This decode is handled before any others (and in particular before +# decoding FP instructions which are in the coprocessor space). +# If the coprocessor is not present or disabled then we will generate +# the NOCP exception; otherwise we let the insn through to the main decode. + +{ + # Special cases which do not take an early NOCP: VLLDM and VLSTM + VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 + # TODO: VSCCLRM (new in v8.1M) is similar: + #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + + NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- + NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- + # TODO: From v8.1M onwards we will also want this range to NOCP + #NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=3D10 +} diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 5fd70f975ae..2c793e3e87f 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -213,5 +213,3 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 = .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp - -VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 diff --git a/target/arm/translate.c b/target/arm/translate.c index 362d1cc50fb..958e9b6699f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1176,6 +1176,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) =20 /* Include the VFP and Neon decoders */ +#include "decode-m-nocp.c.inc" #include "translate-vfp.c.inc" #include "translate-neon.c.inc" =20 @@ -8433,6 +8434,19 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ARCH(6T2); } =20 + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * NOCP takes precedence over any UNDEF for (almost) the + * entire wide range of coprocessor-space encodings, so check + * for it first before proceeding to actually decode eg VFP + * insns. This decode also handles the few insns which are + * in copro space but do not have NOCP checks (eg VLLDM, VLSTM). + */ + if (disas_m_nocp(s, insn)) { + return; + } + } + if ((insn & 0xef000000) =3D=3D 0xef000000) { /* * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq @@ -8481,21 +8495,7 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ - if (extract32(insn, 24, 2) =3D=3D 3) { - goto illegal_op; /* op0 =3D 0b11 : unallocated */ - } - - if (((insn >> 8) & 0xe) =3D=3D 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } - break; + goto illegal_op; } if (((insn >> 24) & 3) =3D=3D 3) { /* Neon DP, but failed disas_neon_dp() */ diff --git a/target/arm/meson.build b/target/arm/meson.build index bd46cdb5239..89900907125 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,6 +5,7 @@ gen =3D [ decodetree.process('neon-ls.decode', extra_args: '--static-decode=3Ddisa= s_neon_ls'), decodetree.process('vfp.decode', extra_args: '--static-decode=3Ddisas_vf= p'), decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=3Dd= isas_vfp_uncond'), + decodetree.process('m-nocp.decode', extra_args: '--static-decode=3Ddisas= _m_nocp'), decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 2d63fa0d399..d376bd1c1ad 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -95,14 +95,11 @@ static inline long vfp_f16_offset(unsigned reg, bool to= p) static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized= (), - s->fp_excp_el); - } else { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); - } + /* M-profile handled this earlier, in disas_m_nocp() */ + assert (!arm_dc_feature(s, ARM_FEATURE_M)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); return false; } =20 @@ -2842,9 +2839,14 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) !arm_dc_feature(s, ARM_FEATURE_V8)) { return false; } - /* If not secure, UNDEF. */ + /* + * If not secure, UNDEF. We must emit code for this + * rather than returning false so that this takes + * precedence over the m-nocp.decode NOCP fallback. + */ if (!s->v8m_secure) { - return false; + unallocated_encoding(s); + return true; } /* If no fpu, NOP. */ if (!dc_isar_feature(aa32_vfp, s)) { @@ -2863,3 +2865,33 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) s->base.is_jmp =3D DISAS_UPDATE_EXIT; return true; } + +static bool trans_NOCP(DisasContext *s, arg_NOCP *a) +{ + /* + * Handle M-profile early check for disabled coprocessor: + * all we need to do here is emit the NOCP exception if + * the coprocessor is disabled. Otherwise we return false + * and the real VFP/etc decode will handle the insn. + */ + assert(arm_dc_feature(s, ARM_FEATURE_M)); + + if (a->cp =3D=3D 11) { + a->cp =3D 10; + } + /* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable= */ + + if (a->cp !=3D 10) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); + return true; + } + + if (s->fp_excp_el !=3D 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + return false; +} --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263105; cv=none; d=zohomail.com; s=zohoarc; b=hjarjmYMB5hmyTWaOCfX+zGOeGa7kuCYiP8r5BL/9VIZB5arP0UB9agCF6jp+WK5ZGBvzX2AEHb78M2+HrG3iwC1XC+B+XJN7/zsACzKYpx9HEfmMdTaX6GJU3PKn0Us7Xdse27DT5DuADrclO3j5WPT7faTJiuI4lcXpyvsFNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263105; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IZG5JPPNIRlIPpo72HZmBANuur0NLEoD5lEA/T/LC+I=; b=NcQQS5nj78at54I3WCOTOeI84nrGijxck0AcZGILVhpTfSk5YWgxLJmUZNKMRFMK5MPaJ9hmDkaCvfQG57GMoSDtV6MF24BJHQPnJ0iGBayNLQ9HPorlbpeqSXYfY07Xyg1AezsaHleSZ5vgKJtP8HISQLynF0I7TcAy1MyBjyU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263105130383.0068006773886; Mon, 24 Aug 2020 02:58:25 -0700 (PDT) Received: from localhost ([::1]:50404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9F9-0008Pf-RX for importer@patchew.org; Mon, 24 Aug 2020 05:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95k-0005OK-9o for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:40 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:55913) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95i-0004pD-Cy for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:39 -0400 Received: by mail-wm1-x32f.google.com with SMTP id a65so4085882wme.5 for ; Mon, 24 Aug 2020 02:48:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IZG5JPPNIRlIPpo72HZmBANuur0NLEoD5lEA/T/LC+I=; b=yySgJMlUnrXVGOFw9dcbrlk6iOUmWWbuYas4X6OugTSsk4xsK41/V653LRL20GogQi tSM2LF+n77MW7q8KgRSLN1orx0s/UkvrINWUuyl0VaNB7FxtWMr+5jZ2bk5ZYgFLxjoQ N4AA/mkdCUUgWgQIsinePmfbavcv5yjXISdl/eSotoa76AhBxrHrAWKHCOnV0vGOZL0h iHwQvzK1CGueWRD5rDrgQOvjIIJQxCn5MaiQYZsq9hfrQYcbgqjSiVvDFwt6UTmqhx0y bS0lLaqO+15ijJTmKx93cVkN6swPD/5xzKOHFKMZwDbLXhWcW1uqV+nNt5Sj2Uv3OzpY BoWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZG5JPPNIRlIPpo72HZmBANuur0NLEoD5lEA/T/LC+I=; b=fljjz9Nja6M9IPl0/G8Am+rGisIsGQanXrmLMiUZUn7j93bO5oVHOnXgB62pz45q/L ivbjoCu/Gy1sBl3ZOJBr08jcVkq23HO/J+a7AVRnC2+gaCQt9xh49Pr0Ppu3P7s9fRQY YoSyuIkE85gGiGr4Nm9mk5B0bOGO6w5qo5uXMME9Tfh3WXMGS4bB5SVocIAi/y8llAlR Qdiy8ve8SeaE6yLHrTMIt25wSj6Y9pQ16M9rB369Qx7F7ddTY63PZjq0aCHyLGHi0EN/ 8EcLEwH3iqBOeFsBuEZKATuu43rUpRZgnJcO80f1pKjwmmc03N1zgz5WNL5pzuMQVOPe V9ag== X-Gm-Message-State: AOAM531lSuWqGqxefnx8AVLfLXHO2sHsFTv5sdKg6JKI9PhW3NtbBzxz eGdIiqp9lyfrvVpT/3g08Yn36kLMwbI951Ac X-Google-Smtp-Source: ABdhPJw/gbc2IbTlIUJ7vOWgvtlkz8eHMS5UHsr883f7g2uQXHKNn4/Sea8OIjfyLCliiADeBMYZ5Q== X-Received: by 2002:a7b:ce12:: with SMTP id m18mr4623629wmc.3.1598262516693; Mon, 24 Aug 2020 02:48:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/27] target/arm: Convert T32 coprocessor insns to decodetree Date: Mon, 24 Aug 2020 10:48:03 +0100 Message-Id: <20200824094811.15439-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Convert the T32 coprocessor instructions to decodetree. As with the A32 conversion, this corrects an underdecoding where we did not check that MRRC/MCRR [24:21] were 0b0010 and so treated some kinds of LDC/STC and MRRC/MCRR rather than UNDEFing them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-7-peter.maydell@linaro.org --- target/arm/t32.decode | 19 +++++++++++++ target/arm/translate.c | 64 ++---------------------------------------- 2 files changed, 21 insertions(+), 62 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c21a988f971..7069d821fde 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -45,6 +45,8 @@ &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb &cps !extern mode imod M A I F +&mcr !extern cp opc1 crn crm opc2 rt +&mcrr !extern cp opc1 crm rt rt2 =20 # Data-processing (register) =20 @@ -621,6 +623,23 @@ RFE 1110 1001 10.1 .... 1100000000000000 = @rfe pu=3D1 SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=3D2 SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=3D1 =20 +# Coprocessor instructions + +# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the +# other coprocessor instructions always UNDEF. +# The trans_ functions for these will ignore cp values 8..13 for v7 or +# earlier, and 0..13 for v8 and later, because those areas of the +# encoding space may be used for other things, such as VFP or Neon. + +@mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 +@mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 + +MCRR 1110 1100 0100 .... .... .... .... .... @mcrr +MRRC 1110 1100 0101 .... .... .... .... .... @mcrr + +MCR 1110 1110 ... 0 .... .... .... ... 1 .... @mcr +MRC 1110 1110 ... 1 .... .... .... ... 1 .... @mcr + # Branches =20 %imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 diff --git a/target/arm/translate.c b/target/arm/translate.c index 958e9b6699f..e2ae4f79445 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4791,37 +4791,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, return; } =20 -static int disas_coproc_insn(DisasContext *s, uint32_t insn) -{ - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; - - cpnum =3D (insn >> 8) & 0xf; - - is64 =3D (insn & (1 << 25)) =3D=3D 0; - if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { - /* cdp */ - return 1; - } - - crm =3D insn & 0xf; - if (is64) { - crn =3D 0; - opc1 =3D (insn >> 4) & 0xf; - opc2 =3D 0; - rt2 =3D (insn >> 16) & 0xf; - } else { - crn =3D (insn >> 16) & 0xf; - opc1 =3D (insn >> 21) & 7; - opc2 =3D (insn >> 5) & 7; - rt2 =3D 0; - } - isread =3D (insn >> 20) & 1; - rt =3D (insn >> 12) & 0xf; - - do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2); - return 0; -} - /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ static void disas_xscale_insn(DisasContext *s, uint32_t insn) { @@ -8485,38 +8454,9 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } - /* fall back to legacy decoder */ =20 - switch ((insn >> 25) & 0xf) { - case 0: case 1: case 2: case 3: - /* 16-bit instructions. Should never happen. */ - abort(); - case 6: case 7: case 14: case 15: - /* Coprocessor. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ - goto illegal_op; - } - if (((insn >> 24) & 3) =3D=3D 3) { - /* Neon DP, but failed disas_neon_dp() */ - goto illegal_op; - } else if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP, but failed disas_vfp. */ - goto illegal_op; - } else { - if (insn & (1 << 28)) - goto illegal_op; - if (disas_coproc_insn(s, insn)) { - goto illegal_op; - } - } - break; - case 12: - goto illegal_op; - default: - illegal_op: - unallocated_encoding(s); - } +illegal_op: + unallocated_encoding(s); } =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598262941; cv=none; d=zohomail.com; s=zohoarc; b=ILlaQmQYuFYJPi3xlj76NBEqbbJh+FKN3qtygexCRYndPYRb9R02qAoJmqlFaE/tg9SrEady3stVrwgVah0PsAw3toWkvsIwWXRO8+a9WYOTMOr6JWqxXhY0Se/li73B5wNtiNE8EejF43tIRBsmaUsls9QYfnNwl2M2zWbG9Kk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598262941; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q1SGsLtGvl8tkzfyXqvO5I14atXH9ou0bzu3JEMmqBE=; b=Es1qjINHTax+SA9bQl3S50wmHllnsVowWO8PZMt3/4Jz4QCm2Tm+G/hgXqYjAE/I4ms/KAPDC/LLKXBatKZsMo/Q3wNMYCHdfHB5sVQPlfrOqA7lKVO4kBpcxahYX4kaa4WxJ06BdAEZHD6XEamHRhDjnpiq5Rcnc+bEHobUCpc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598262941638157.69644568898468; Mon, 24 Aug 2020 02:55:41 -0700 (PDT) Received: from localhost ([::1]:37232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9CW-0002vp-Bu for importer@patchew.org; Mon, 24 Aug 2020 05:55:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95l-0005Qo-46 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:41 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:33243) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95j-0004pJ-EH for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:40 -0400 Received: by mail-wr1-x42c.google.com with SMTP id o4so3962061wrn.0 for ; Mon, 24 Aug 2020 02:48:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=q1SGsLtGvl8tkzfyXqvO5I14atXH9ou0bzu3JEMmqBE=; b=ufbZLRYVgZbbTrWSo1TdSiwhLY7l3+1iCJH59ITVCE8nIemKQCvZ1lUSmGJhdosesQ Yc/eDIeTlDVEQNOkZBoEWMpOe+uR57VK4Nn6/mNPC26SwfM1kvq+t6Y4tADGzfus0SkF Bg6CWujILW4ilYYKGnRS3ZW3F3HzWTXk0DwlgzU3dJ6xOMtMmoMZ52dSclQaohcOhKqo 4pBwMBPVpWK1F6WDKP2iF322swMTMUYhHmD/mVWJ3mrCe/aZctJkH2SH/PJqNCyqTY4H 9t4Rr21ZLKdiGTIA7toKs7R8dnosDTS2B6yXbtUHiBh0NONUvgnSqnkOGycBnDB87YcD rXIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q1SGsLtGvl8tkzfyXqvO5I14atXH9ou0bzu3JEMmqBE=; b=dru7mfnk2UVHkszgiZEA+s1tVHg1RVGsrUijej47k+KgVf7TNDiOmMivocyl4gQcZD F9eDoNc7KluLLo8Jah8fzOu/XkZui8lYLuAWLPy6dL55B6y8UexkiEA64Gr4Ha1dgwXB ZW77zHcdOlQX1XPaYwy/zoYKm3Q2AeOs+NLPzcI6PgKcliLK56SBK68O0rZ+SO3vZKmO IyPiHqouhjqXTuS4UDrV0D61et11tAy9vHTCtJraIldURq5QiIJiGvCTOGeEUIyoFebT IJ3EeSC0F7TB+VaDf+/AlbG8pJqmPBGF055E6Pa5sCfe3ASnpUk42tTK72WBdmJgJyV7 6sRA== X-Gm-Message-State: AOAM532bSCSYKj9DpltmYZpEfF1LQQAP99clSJqU+QGrEUdQgnDMbfxK vlf1spB1QiMjKpSUld2u4JHm5rAmqEyOnZ7y X-Google-Smtp-Source: ABdhPJwgL8KwRAkFdjU8z5WK4jDSy+nY644r7TJnWC8LU2h7KCV+LrNdyDY2G4LI7sUUiR+bQE/VCg== X-Received: by 2002:adf:aa9e:: with SMTP id h30mr4799936wrc.377.1598262517836; Mon, 24 Aug 2020 02:48:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/27] target/arm: Remove ARCH macro Date: Mon, 24 Aug 2020 10:48:04 +0100 Message-Id: <20200824094811.15439-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARCH() macro was used a lot in the legacy decoder, but there are now just two uses of it left. Since a macro which expands out to a goto is liable to be confusing when reading code, replace the last two uses with a simple open-coded qeuivalent. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803111849.13368-8-peter.maydell@linaro.org --- target/arm/translate.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e2ae4f79445..b74a4350e39 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -49,8 +49,6 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 -#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) - #include "translate.h" =20 #if defined(CONFIG_USER_ONLY) @@ -7909,7 +7907,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { TCGv_i32 tmp; =20 - /* For A32, ARCH(5) is checked near the start of the uncond block. */ + /* For A32, ARM_FEATURE_V5 is checked near the start of the uncond blo= ck. */ if (s->thumb && (a->imm & 2)) { return false; } @@ -8275,7 +8273,10 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. */ - ARCH(5); + if (!arm_dc_feature(s, ARM_FEATURE_V5)) { + unallocated_encoding(s); + return; + } =20 /* Unconditional instructions. */ /* TODO: Perhaps merge these into one decodetree output file. */ @@ -8400,7 +8401,10 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) goto illegal_op; } } else if ((insn & 0xf800e800) !=3D 0xf000e800) { - ARCH(6T2); + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + unallocated_encoding(s); + return; + } } =20 if (arm_dc_feature(s, ARM_FEATURE_M)) { --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263031; cv=none; d=zohomail.com; s=zohoarc; b=Frl0CyZOvSxnRKkqrVTzOyWIzJjb8eQFcxkAQoghOPB9MfadV7owHQpaoCN+g8GoEHXolvmdpgP2FH6PqrRlsQD1/pzkuYbLSvyPu9pHJEZK+JthWCls0eaY8UTlf59jodv2euPSOtG4iW/2d/f/O9/HJhfppSBr8muMiz28HBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263031; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rXc1zd2h6n/7ieWiemihqkhV0rfIkaZUjYQ6Am+tbsw=; b=aZnkSD/B4U96n8xULSZyXGzj9pHkIbuCy+1VQDWBcHA9IWddAACrS2v46addtupIUazLjhf06PjulcK0t5Nr6ILnVMspmUn38QtQJUAWbOY+RvSvo2NID16TKG5FnHMojgIk4XMEn8ZOQveOPbG64NPpo/qS5L6lgyvdbtNfCsI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263031951391.2694511983501; Mon, 24 Aug 2020 02:57:11 -0700 (PDT) Received: from localhost ([::1]:44332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9Dy-0005qz-NQ for importer@patchew.org; Mon, 24 Aug 2020 05:57:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95l-0005TE-VK for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:41 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95k-0004pR-Br for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:41 -0400 Received: by mail-wr1-x42f.google.com with SMTP id f7so8031264wrw.1 for ; Mon, 24 Aug 2020 02:48:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rXc1zd2h6n/7ieWiemihqkhV0rfIkaZUjYQ6Am+tbsw=; b=Bjivqb1F8zUa+4MCVxoESr4CnKxu5wBc2ps+Vnh3Nopyl/QE6jPFibz70VbcNjlTP0 7M7A5aOa6jPxN/CM5lpNilcRfNmPdVvetwOoQwHMCjDrEH9o6xDHaSObeARnS+BP4gsb UU9ewuyeJ7UQKXuPRQX79yqwO/7v0bGu07IKVLQBLGcx7qikxBsyYwCMHsj/KmXQRTPM uM87f+Y68GqEoJdhzNGOH6aTj8zuS5Baj4dYDmnjYulLs2NZoGYDTW+aQDBIt454dux2 XTPHmgQt+8Pl/wwRXRvcTJ6SneVKQaBGGEbwNToGY0jn0KHOkaH5tZVOr4puBit/gQ9P /onw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rXc1zd2h6n/7ieWiemihqkhV0rfIkaZUjYQ6Am+tbsw=; b=kIAXhrRAJjW34Q0vYANp9NAOuT48F3hZUIiZg0OEVbMeu4zHSLdIUe/SxAvGjSmASI fUllKrzs7qX3rlaQL0YhODe/asMPh2Bf7uRHKs+Zp44ks2HlmSGhd5Bq1i/TijXR6LKY GtF5YCV/E8vEMN78wBOp57HpI+Vo/6aVVYhgPFg0N0Jacm80E93zpOIup4okRRZMODF4 mHk2Jrapd5OQO1ayqbBOx/w5t61kbrcplU1UVM1SpIlyxyint6t7zMtDF5fSFPx/WWGO 6NUtDZXspREHguj7rS8h6RmZTQBksAVXhXyztxnN1Ksqc8pnnHOJ241Xc2iBaoWZ7VJS 54Tg== X-Gm-Message-State: AOAM533rAYPm2EPSFeXht/7nc/hQqlRzaeGfiO7puz6dZ5zZS+m7FdJ6 BB2iiDoM1hsX3PbVQvmbfbvP9O5LHYYpVrW9 X-Google-Smtp-Source: ABdhPJwb0LF9hYJAKYix13FJCk2P9wgXu8bZPOILGzZfwrUM1vPWsF+lNEO1K0hD7yJNF2wW7k4znA== X-Received: by 2002:adf:fed0:: with SMTP id q16mr5007840wrs.400.1598262518862; Mon, 24 Aug 2020 02:48:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/27] target/arm: Delete unused VFP_DREG macros Date: Mon, 24 Aug 2020 10:48:05 +0100 Message-Id: <20200824094811.15439-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) As part of the Neon decodetree conversion we removed all the uses of the VFP_DREG macros, but forgot to remove the macro definitions. Do so now. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20200803124848.18295-1-peter.maydell@linaro.org --- target/arm/translate.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b74a4350e39..4ffd8b1fbe5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2470,21 +2470,6 @@ static int disas_dsp_insn(DisasContext *s, uint32_t = insn) return 1; } =20 -#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) -#define VFP_DREG(reg, insn, bigbit, smallbit) do { \ - if (dc_isar_feature(aa32_simd_r32, s)) { \ - reg =3D (((insn) >> (bigbit)) & 0x0f) \ - | (((insn) >> ((smallbit) - 4)) & 0x10); \ - } else { \ - if (insn & (1 << (smallbit))) \ - return 1; \ - reg =3D ((insn) >> (bigbit)) & 0x0f; \ - }} while (0) - -#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) -#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) -#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) - static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263102; cv=none; d=zohomail.com; s=zohoarc; b=azC9M5l+2riqDOT+b+jvV9wufaYmBditrD6L/fs4rGnL76tJNX+d6R/SVWtoQVqKDmvikRA1Lf3oG1B/umEJIZfoCu3iZAWwhGiL9lgoserUgpuKTITWgZoyuM900xl5uwsjj7PAcXN6ibkqKp0YKZcCWD/cHJVEjSxLhvcQwdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263102; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=986a+dtrAGXDxkRArhjNYo7MkVjUW9PLQfZ9R0W5SLo=; b=bOER8KkFaVLuMR5IvPby4QYsO/rYCHczw6I45zWQGGViCKe2N74v439t34hpVQw8q8hALBGT3NQxpJU27OOHYLFBuKGDGzK2+O70a6UN1U8KkvzrG8xVefp9DzcR/jpdFjF2L5Jlm5VI4ybzblqjv7lU+3LPi0V/I6oLW1Q3UKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263102650615.8496384668589; Mon, 24 Aug 2020 02:58:22 -0700 (PDT) Received: from localhost ([::1]:50200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9F7-0008Kd-EX for importer@patchew.org; Mon, 24 Aug 2020 05:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95n-0005We-5t for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:43 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:35177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95l-0004pb-E7 for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:42 -0400 Received: by mail-wm1-x32f.google.com with SMTP id o21so7551440wmc.0 for ; Mon, 24 Aug 2020 02:48:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=986a+dtrAGXDxkRArhjNYo7MkVjUW9PLQfZ9R0W5SLo=; b=jkGWnS8vCYIXlavTZRWs9aQi7tvOTdls7bgm+3BLuUbI18fxWzHeICnvajm1AH2sau PpMa3MkZVRJzBb+vY3m95Xv9v3mbU8MNj+TsTeXV/4zNDjG3ugdud09Wgei29PH+u8jM R+LLQ5a0Hi6dNzpUAJCw5UkYracmHyTlkLnG29U8J6o6nrPhUomF3vdnRlw31eO2fmQ8 EYDoO9fdGqWX62W0FvbUwcP+MFzGLrIMlSz+Lc5G2I7R1HgkuSkCSJiWkB7bohgfrUUJ s0JYH+I5JeGedJV6xh+qw5kvVAlmpKCon6NShRz+U0w8ftX+oY8tVbekryA7Nj78Zove qf3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=986a+dtrAGXDxkRArhjNYo7MkVjUW9PLQfZ9R0W5SLo=; b=a82gAAXNrtTlJ0Ck7n8yPgobtqkxmvlWCAGb/DVGRr1xf4dt3w7/kYGkBVXdIMlVxq JiMGj/yhknRvIqxjdbEIVSef/jH8yJniY0huuXXwKorwWt6gc8VO4cpLv2fR8fO/wwGQ 17+HX1vKbMA0dkfZ/vV/NOoWA+/LmvjsBlneMX9t6/VOHZsCORfHrU37dGa5msJw7fAn sieqO+G4ByML9t1gE4FAOQaNYWpp4cggIhAqbVkhJQEpio/iXpoQGrTJg3+HHxsWiXR1 IwRfA5rgD3LstQBqEZoV5yeFq7To2wo1OrpzYGLhaq6Q5W1pwJEoL1hqT93GTgp/d9Bl t6EQ== X-Gm-Message-State: AOAM532WDNOQDrovSHoCY9Yk6RJwzR/Mv/fIcsQk4RgLf5TMSUlKv3Io +S5z1N6Ywa2B9zxDfSJwfqQ1DKx22kC/Wls8 X-Google-Smtp-Source: ABdhPJxfDZeQR37FDhKcKbvNbCN3cDX/SqgFpcJ5qxWO7kHci8v8cp4nsA6NxN1pv90M1590olOcLQ== X-Received: by 2002:a1c:1b43:: with SMTP id b64mr5051161wmb.6.1598262519894; Mon, 24 Aug 2020 02:48:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/27] target/arm/translate.c: Delete/amend incorrect comments Date: Mon, 24 Aug 2020 10:48:06 +0100 Message-Id: <20200824094811.15439-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_tr_init_disas_context() we have a FIXME comment that suggests "cpu_M0 can probably be the same as cpu_V0". This isn't in fact possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(), and that function is called in various places where cpu_M0 contains a live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment. We also have a comment on the declarations of cpu_V0/V1/M0 which claims they're "for efficiency". This isn't true with modern TCG, so replace this comment with one which notes that they're only used with the iwmmxt decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200803132815.3861-1-peter.maydell@linaro.org --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ffd8b1fbe5..dd25adcf402 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -57,8 +57,9 @@ #define IS_USER(s) (s->user) #endif =20 -/* We reuse the same 64-bit temporaries for efficiency. */ +/* These are TCG temporaries used only by the legacy iwMMXt decoder */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +/* These are TCG globals which alias CPUARMState fields */ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; @@ -8566,7 +8567,6 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 cpu_V0 =3D tcg_temp_new_i64(); cpu_V1 =3D tcg_temp_new_i64(); - /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); } =20 --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263177; cv=none; d=zohomail.com; s=zohoarc; b=jH3lPuC0i9OnqXfugO0bW5bPFiVRFYU/W8XB2c8M93kkXTd5AEVZR/EbXy9zKDCXskoglOILy2YCLbMz5CqVrCCtWiEkw6xAvzgtzvK9/iBybO+pmnfNo2pKLicyVWC/drKyCpgAIrgFKWn+qFurqqNE8VZRlD20rlJHGs9g4To= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263177; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4SpG6X894Q08xJg7KSl0Dqp09v2NXNEz0pss3dMzgp4=; b=dtwKIFYc2StjMJltbI98Wd+AhWM/N+y/Xssxqv/WC/XkbimX6XDW2BrY6jZsxeGhfH/qp/8p/0LPNHhLiS8kJj+Rv8fKAEEieCgtA5+VIETmtyrrGZ//VOaVwlbS3nzAczrFeLZmkQTZFFXky30rTqQpHj3rTM3eTUrBC7JIuiE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263177835352.0802397877137; Mon, 24 Aug 2020 02:59:37 -0700 (PDT) Received: from localhost ([::1]:55988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9GK-0002JJ-LO for importer@patchew.org; Mon, 24 Aug 2020 05:59:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95o-0005a4-AT for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:44 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:36417) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95m-0004pl-JD for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:43 -0400 Received: by mail-wr1-x435.google.com with SMTP id x7so1932707wro.3 for ; Mon, 24 Aug 2020 02:48:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4SpG6X894Q08xJg7KSl0Dqp09v2NXNEz0pss3dMzgp4=; b=SDryJzrrqIRbdWqq1fnufgMPdIvdmsoR6/eXYe4fwhicUkA5/3KCzT4WIfgpnxySbg 8s5wwD12s/GvXKpYQbfVaMXdWGjTneq7wWZ1eJfanUdBh9w5J+cjCvPzXYDLLIK3G2lU bNvep2MduoAIjG1pLrBJlJwFxpq0oOKN4i8+DvptDYEgJkeEptgAGqOwxlb3tFFswFko h+g4HRjsAluHXjLDN9yfqCrClO5Mr8ysc1ccnGCZ3y0akGqSBrKH3IqSjmwRsjyNGXP7 ZduMk2I/nlO2NA91xzEB0brTIC6xjJdJANiiLab4LFK8pDHscb6pZt/EH5kF8TgZH9Gw 3I0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4SpG6X894Q08xJg7KSl0Dqp09v2NXNEz0pss3dMzgp4=; b=eDc1TIWKOWSQtw9rMQPSJvUgxGaRQRdI6zmgbBI1ZerV7bAxhqTioxn3fgEDz0XdLO TFCfPUtKuXI2NCjyxqHJr/69b4yrO1UrSl020uIyMn+cGbLkT8UzXU5jTW4QPsePlLPf flz/KdwFaU6f9qzYdbViodOXinvJY4sZtlMguen4LRH3L4LD+WTnO/uGyT0lfIGj0fxR z56Cw08JJIHu7MjIXaQe7Rbua2KG2df655c+YR4VZb5haIsrZZVGgd87GLawTyEcU9g9 1rQXr+arG/q1nsM8nsfFEV4C0TkXL3m47c1I3WC7tIySzz2J4rerMCVH2JJW6wti11dP bR/Q== X-Gm-Message-State: AOAM533ZZzVBEjDbWkvbLgvH5btnSk9m4aOjyt7LFUcF/Ox1/pLB3w7c W5919DPG4/AP+VpUBr/t+LDT/9K73x1k4+bO X-Google-Smtp-Source: ABdhPJza1kiL+5sRTQdw5IezXmTA94KzD0yX/RVTkDgkXr8vGiISXqDfm0h3bG3pyZxs/ihD+ne3Vw== X-Received: by 2002:adf:f007:: with SMTP id j7mr4746688wro.195.1598262520893; Mon, 24 Aug 2020 02:48:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/27] target/arm: Delete unused ARM_FEATURE_CRC Date: Mon, 24 Aug 2020 10:48:07 +0100 Message-Id: <20200824094811.15439-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In commit 962fcbf2efe57231a9f5df we converted the uses of the ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test instead. However we forgot to remove the now-unused definition of the feature name in the enum. Delete it now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200805210848.6688-1-peter.maydell@linaro.org --- target/arm/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9e8ed423ea1..9d2845c1797 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1950,7 +1950,6 @@ enum arm_features { ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ ARM_FEATURE_CBAR, /* has cp15 CBAR */ - ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ ARM_FEATURE_EL2, /* has EL2 Virtualization support */ ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263178; cv=none; d=zohomail.com; s=zohoarc; b=ZzB4XOOXMR6g9Xw7tf2nWHha2qYn2Zh1tTjn29qNARg9/+ep0vWJ+LRx68k/7mw8v5n/o0Q9lXeEwMJCalwX3PbQ+Nnlk3zIezPNpxCd8JrvQ1Ox+iC6m0N9wj/IP8ao96avq5TSHJoSN8EUm4x5LedwfuVMjNZY82oxdAm51ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263178; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E0M5ZgKEIutbz4nTL0XmI/Vkla88O9nUN67zPNf/NKU=; b=UHAu3V5g5QftOV/hQWxJHA3tp+YvgO1QHJ5ccMNT8zlrlUVfkDrpNdHElfGZDIGi1vxG1R2nJa+Lj06Qtqa9myRLPFYEdxjIQbTgDBcqnqS5kSoZKDcO/Wn6qLyFO+Ae11y/7U/bKYfJmmvM1OAHpiqMGkKd8/00pWnyvwZ9Rck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598263178042266.08642602759755; Mon, 24 Aug 2020 02:59:38 -0700 (PDT) Received: from localhost ([::1]:55938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9GK-0002I3-Mr for importer@patchew.org; Mon, 24 Aug 2020 05:59:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95r-0005jl-Qw for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:47 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:51553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95o-0004q1-Jx for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:47 -0400 Received: by mail-wm1-x32f.google.com with SMTP id s20so2648168wmj.1 for ; Mon, 24 Aug 2020 02:48:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E0M5ZgKEIutbz4nTL0XmI/Vkla88O9nUN67zPNf/NKU=; b=omgjD0WMN+pZ+53Lt+HiRhbsBf0DZFpKhw1ijBJ3QgCF0rwqFt29uN7LDC79k4QVX8 AnHnTJJ1svyOymTyP1mGIXMSksXnSbnyXP41H3Gr5ESvS/jjrVhZnMNjaNxhJeMqTGzK HpuX6h6i8Fpk0DOA2SrLrnF9ZgAfEOWlEQEiIEiFn7pej46jDcoJu/ca//4xSWOzzCRv JLnWFA1ftBWhvpZP6sK6g5F80Tnc4AAdrZN3zEAqj1XZgBIx2hd5gG7RM+Vl5YCdfPUg WRQZ3dFkpeLrf+7N0dUx+OqDdsH4yq9y8s7aYcATD0UArHY9AUp7kM8U+nGo91c4RZM4 28NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E0M5ZgKEIutbz4nTL0XmI/Vkla88O9nUN67zPNf/NKU=; b=lmt1JZB+DoAnDRO49peLBezx3cjFaIHO/yWzlIBKl4/U6IIVFqfqd1YDgUPjJtmG17 WNER2bZfFVZL2ML+SnjfdAuIRy09Yk9KERsNvLoh+qLVLL/41DEaIq52Uhj+JRBv9BgR pa8JSUv4MMmqxDwsrS5NijpyR6H9x4gvc6IVYi5uBTPRw+QN2q6BMcflGfqG9xWpaDh7 A3LmZuF62ndWmDXwH4pTTiaFjXmSxsDRScxUeyzJBN5tgmvaOTA+Ux+B7K3h+tzYhkan 7AntgKWjvWg32BZPEvXR9Vo9Xl798hVeDf9OI8OElsjZ30rEf4s/n1XFKWAqt4vEeXKn uqtA== X-Gm-Message-State: AOAM533bAEfiEiRkKf+yhrh983HtY1CwKsoyBefpXKj5kGg6i21239pa Ldoga60/soi/ekFXpgBxuzOdDyfq0hUzhYsx X-Google-Smtp-Source: ABdhPJwP5zvv8U6A8za6FYR0aA4ZF7xISH63b8ztSZuTyeQi8Qfa8mw2DGp2eQHdVNK0IV3Un3unjg== X-Received: by 2002:a1c:9ecf:: with SMTP id h198mr4876290wme.35.1598262522195; Mon, 24 Aug 2020 02:48:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/27] target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr() Date: Mon, 24 Aug 2020 10:48:08 +0100 Message-Id: <20200824094811.15439-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We currently have two versions of get_fpstatus_ptr(), which both take an effectively boolean argument: * the one for A64 takes "bool is_f16" to distinguish fp16 from other ops * the one for A32/T32 takes "int neon" to distinguish Neon from other ops This is confusing, and to implement ARMv8.2-FP16 the A32/T32 one will need to make a four-way distinction between "non-Neon, FP16", "non-Neon, single/double", "Neon, FP16" and "Neon, single/double". The A64 version will then be a strict subset of the A32/T32 version. To clean this all up, we want to go to a single implementation which takes an enum argument with values FPST_FPCR, FPST_STD, FPST_FPCR_F16, and FPST_STD_F16. We rename the function to fpstatus_ptr() so that unconverted code gets a compilation error rather than silently passing the wrong thing to the new function. This commit implements that new API, and converts A64 to use it: get_fpstatus_ptr(false) -> fpstatus_ptr(FPST_FPCR) get_fpstatus_ptr(true) -> fpstatus_ptr(FPST_FPCR_F16) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20200806104453.30393-2-peter.maydell@linaro.org --- target/arm/translate-a64.h | 1 - target/arm/translate.h | 51 ++++++++++++++++++++++ target/arm/translate-a64.c | 89 +++++++++++++++----------------------- target/arm/translate-sve.c | 34 +++++++-------- 4 files changed, 103 insertions(+), 72 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 647f0c74f62..2e0d16da259 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -37,7 +37,6 @@ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); -TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); diff --git a/target/arm/translate.h b/target/arm/translate.h index 16f2699ad72..e3680e65479 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -393,4 +393,55 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TC= Gv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); =20 +/* + * Enum for argument to fpstatus_ptr(). + */ +typedef enum ARMFPStatusFlavour { + FPST_FPCR, + FPST_FPCR_F16, + FPST_STD, + FPST_STD_F16, +} ARMFPStatusFlavour; + +/** + * fpstatus_ptr: return TCGv_ptr to the specified fp_status field + * + * We have multiple softfloat float_status fields in the Arm CPU state str= uct + * (see the comment in cpu.h for details). Return a TCGv_ptr which has + * been set up to point to the requested field in the CPU state struct. + * The options are: + * + * FPST_FPCR + * for non-FP16 operations controlled by the FPCR + * FPST_FPCR_F16 + * for operations controlled by the FPCR where FPCR.FZ16 is to be used + * FPST_STD + * for A32/T32 Neon operations using the "standard FPSCR value" + * FPST_STD_F16 + * as FPST_STD, but where FPCR.FZ16 is to be used + */ +static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) +{ + TCGv_ptr statusptr =3D tcg_temp_new_ptr(); + int offset; + + switch (flavour) { + case FPST_FPCR: + offset =3D offsetof(CPUARMState, vfp.fp_status); + break; + case FPST_FPCR_F16: + offset =3D offsetof(CPUARMState, vfp.fp_status_f16); + break; + case FPST_STD: + offset =3D offsetof(CPUARMState, vfp.standard_fp_status); + break; + case FPST_STD_F16: + /* Not yet used or implemented: fall through to assert */ + default: + g_assert_not_reached(); + } + tcg_gen_addi_ptr(statusptr, cpu_env, offset); + return statusptr; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 534c3ff5f37..0fc5e12fab4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -609,25 +609,6 @@ static void write_fp_sreg(DisasContext *s, int reg, TC= Gv_i32 v) tcg_temp_free_i64(tmp); } =20 -TCGv_ptr get_fpstatus_ptr(bool is_f16) -{ - TCGv_ptr statusptr =3D tcg_temp_new_ptr(); - int offset; - - /* In A64 all instructions (both FP and Neon) use the FPCR; there - * is no equivalent of the A32 Neon "standard FPSCR value". - * However half-precision operations operate under a different - * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. - */ - if (is_f16) { - offset =3D offsetof(CPUARMState, vfp.fp_status_f16); - } else { - offset =3D offsetof(CPUARMState, vfp.fp_status); - } - tcg_gen_addi_ptr(statusptr, cpu_env, offset); - return statusptr; -} - /* Expand a 2-operand AdvSIMD vector operation using an expander function.= */ static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, GVecGen2Fn *gvec_fn, int vece) @@ -689,7 +670,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_= q, int rd, int rn, int rm, bool is_fp16, int data, gen_helper_gvec_3_ptr *fn) { - TCGv_ptr fpst =3D get_fpstatus_ptr(is_fp16); + TCGv_ptr fpst =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), fpst, @@ -5898,7 +5879,7 @@ static void handle_fp_compare(DisasContext *s, int si= ze, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPS= T_FPCR); =20 if (size =3D=3D MO_64) { TCGv_i64 tcg_vn, tcg_vm; @@ -6157,7 +6138,7 @@ static void handle_fp_1src_half(DisasContext *s, int = opcode, int rd, int rn) tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; case 0x3: /* FSQRT */ - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); break; case 0x8: /* FRINTN */ @@ -6167,7 +6148,7 @@ static void handle_fp_1src_half(DisasContext *s, int = opcode, int rd, int rn) case 0xc: /* FRINTA */ { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); @@ -6177,11 +6158,11 @@ static void handle_fp_1src_half(DisasContext *s, in= t opcode, int rd, int rn) break; } case 0xe: /* FRINTX */ - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); break; case 0xf: /* FRINTI */ - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); break; default: @@ -6253,7 +6234,7 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) g_assert_not_reached(); } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (rmode >=3D 0) { TCGv_i32 tcg_rmode =3D tcg_const_i32(rmode); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -6330,7 +6311,7 @@ static void handle_fp_1src_double(DisasContext *s, in= t opcode, int rd, int rn) g_assert_not_reached(); } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (rmode >=3D 0) { TCGv_i32 tcg_rmode =3D tcg_const_i32(rmode); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -6365,7 +6346,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, /* Single to half */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); TCGv_i32 ahp =3D get_ahp_flag(); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); =20 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ @@ -6385,7 +6366,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); } else { - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); TCGv_i32 ahp =3D get_ahp_flag(); /* Double to half */ gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); @@ -6401,7 +6382,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, case 0x3: { TCGv_i32 tcg_rn =3D read_fp_sreg(s, rn); - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); + TCGv_ptr tcg_fpst =3D fpstatus_ptr(FPST_FPCR); TCGv_i32 tcg_ahp =3D get_ahp_flag(); tcg_gen_ext16u_i32(tcg_rn, tcg_rn); if (dtype =3D=3D 0) { @@ -6518,7 +6499,7 @@ static void handle_fp_2src_single(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); =20 @@ -6571,7 +6552,7 @@ static void handle_fp_2src_double(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i64(); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); =20 @@ -6624,7 +6605,7 @@ static void handle_fp_2src_half(DisasContext *s, int = opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); tcg_op1 =3D read_fp_hreg(s, rn); tcg_op2 =3D read_fp_hreg(s, rm); =20 @@ -6723,7 +6704,7 @@ static void handle_fp_3src_single(DisasContext *s, bo= ol o0, bool o1, { TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); @@ -6761,7 +6742,7 @@ static void handle_fp_3src_double(DisasContext *s, bo= ol o0, bool o1, { TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); @@ -6799,7 +6780,7 @@ static void handle_fp_3src_half(DisasContext *s, bool= o0, bool o1, { TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(true); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 tcg_op1 =3D read_fp_hreg(s, rn); tcg_op2 =3D read_fp_hreg(s, rm); @@ -6945,7 +6926,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, TCGv_i32 tcg_shift, tcg_single; TCGv_i64 tcg_double; =20 - tcg_fpstatus =3D get_fpstatus_ptr(type =3D=3D 3); + tcg_fpstatus =3D fpstatus_ptr(type =3D=3D 3 ? FPST_FPCR_F16 : FPST_FPC= R); =20 tcg_shift =3D tcg_const_i32(64 - scale); =20 @@ -7233,7 +7214,7 @@ static void handle_fmov(DisasContext *s, int rd, int = rn, int type, bool itof) static void handle_fjcvtzs(DisasContext *s, int rd, int rn) { TCGv_i64 t =3D read_fp_dreg(s, rn); - TCGv_ptr fpstatus =3D get_fpstatus_ptr(false); + TCGv_ptr fpstatus =3D fpstatus_ptr(FPST_FPCR); =20 gen_helper_fjcvtzs(t, t, fpstatus); =20 @@ -7847,7 +7828,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_ptr fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); int fpopcode =3D opcode | is_min << 4 | is_u << 5; int vmap =3D (1 << elements) - 1; TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, esize, @@ -8359,7 +8340,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) return; } =20 - fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); break; default: unallocated_encoding(s); @@ -8872,7 +8853,7 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, int elements, int is_signed, int fracbits, int size) { - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + TCGv_ptr tcg_fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); TCGv_i32 tcg_shift =3D NULL; =20 MemOp mop =3D size | (is_signed ? MO_SIGN : 0); @@ -9053,7 +9034,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - tcg_fpstatus =3D get_fpstatus_ptr(size =3D=3D MO_16); + tcg_fpstatus =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPST= _FPCR); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); fracbits =3D (16 << size) - immhb; tcg_shift =3D tcg_const_i32(fracbits); @@ -9392,7 +9373,7 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, int fpopcode, int rd, int rn, int rm) { int pass; - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); =20 for (pass =3D 0; pass < elements; pass++) { if (size) { @@ -9785,7 +9766,7 @@ static void disas_simd_scalar_three_reg_same_fp16(Dis= asContext *s, return; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 tcg_op1 =3D read_fp_hreg(s, rn); tcg_op2 =3D read_fp_hreg(s, rm); @@ -10038,7 +10019,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s,= int opcode, return; } =20 - fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPCR); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -10168,7 +10149,7 @@ static void handle_2misc_reciprocal(DisasContext *s= , int opcode, int size, int rn, int rd) { bool is_double =3D (size =3D=3D 3); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -10309,7 +10290,7 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, } else { TCGv_i32 tcg_lo =3D tcg_temp_new_i32(); TCGv_i32 tcg_hi =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); TCGv_i32 ahp =3D get_ahp_flag(); =20 tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); @@ -10571,7 +10552,7 @@ static void disas_simd_scalar_two_reg_misc(DisasCon= text *s, uint32_t insn) =20 if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - tcg_fpstatus =3D get_fpstatus_ptr(false); + tcg_fpstatus =3D fpstatus_ptr(FPST_FPCR); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; @@ -11396,7 +11377,7 @@ static void handle_simd_3same_pair(DisasContext *s,= int is_q, int u, int opcode, =20 /* Floating point operations need fpst */ if (opcode >=3D 0x58) { - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); } else { fpst =3D NULL; } @@ -11994,7 +11975,7 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) break; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 if (pairwise) { int maxpass =3D is_q ? 8 : 4; @@ -12287,7 +12268,7 @@ static void handle_2misc_widening(DisasContext *s, = int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt =3D is_q ? 4 : 0; TCGv_i32 tcg_res[4]; - TCGv_ptr fpst =3D get_fpstatus_ptr(false); + TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); TCGv_i32 ahp =3D get_ahp_flag(); =20 for (pass =3D 0; pass < 4; pass++) { @@ -12759,7 +12740,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } =20 if (need_fpstatus || need_rmode) { - tcg_fpstatus =3D get_fpstatus_ptr(false); + tcg_fpstatus =3D fpstatus_ptr(FPST_FPCR); } else { tcg_fpstatus =3D NULL; } @@ -13149,7 +13130,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) } =20 if (need_rmode || need_fpst) { - tcg_fpstatus =3D get_fpstatus_ptr(true); + tcg_fpstatus =3D fpstatus_ptr(FPST_FPCR_F16); } =20 if (need_rmode) { @@ -13458,7 +13439,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 if (is_fp) { - fpst =3D get_fpstatus_ptr(is_fp16); + fpst =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); } else { fpst =3D NULL; } diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 8c7fbbd5033..d97cb37d83f 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3470,7 +3470,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA= _zzxz *a) =20 if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3496,7 +3496,7 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_= zzx *a) =20 if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3528,7 +3528,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, =20 tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); - status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); =20 fn(temp, t_zn, t_pg, status, t_desc); tcg_temp_free_ptr(t_zn); @@ -3570,7 +3570,7 @@ DO_VPZ(FMAXV, fmaxv) static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr= *fn) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); =20 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3618,7 +3618,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3_ptr *fn) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); =20 tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3670,7 +3670,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a) } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3710,7 +3710,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) t_pg =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); - t_fpst =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); t_desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); =20 fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); @@ -3737,7 +3737,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3779,7 +3779,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz = *a, } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3831,7 +3831,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int= zn, int pg, bool is_fp16, tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); =20 - status =3D get_fpstatus_ptr(is_fp16); + status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); =20 @@ -3895,7 +3895,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3939,7 +3939,7 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a) } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3958,7 +3958,7 @@ static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4001,7 +4001,7 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FC= MLA_zpzzz *a) } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4024,7 +4024,7 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCM= LA_zzxz *a) tcg_debug_assert(a->rd =3D=3D a->ra); if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -4045,7 +4045,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int r= n, int pg, { if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D get_fpstatus_ptr(is_fp16); + TCGv_ptr status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FP= CR); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), pred_full_reg_offset(s, pg), @@ -4191,7 +4191,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_es= z *a, int mode) if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); TCGv_i32 tmode =3D tcg_const_i32(mode); - TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_FPCR); =20 gen_helper_set_rmode(tmode, tmode, status); =20 --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598263104; cv=none; d=zohomail.com; s=zohoarc; b=ZGO4IUhjIRF1BB1VTCKtvWFHN6+NBwcTHrY2J+szcNeKBGh0DKjXrpsVAJBLqD8dUFbypRVEidiYVaoSfAIJsWUsP0y+D8NysY1OGWmZxU7b3zWPK6R9km49RhF6ZlvTHouHCTfZ+robRGsUwRg5VJRUO4a3YDm9zCFlD4CZSG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598263104; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Aky2cNmcsC4iKc/+4O1X/HAtndxken1Glj23h4cNX8c=; b=TdMFs8qp2l1Y2w4g/CQWBhQRHMRb5l9HLvbiJ9rQsdBrSePFoCxJdfgPSIhSuGUO0wR/pBOYVL2xcAG9BuHsT3puAMaNUXz+vFeVL3s+9enSo3qtpfNyg28Vb16YRNccVjXntzHKUZ+aJGpUrZZiGwyHOUrsslvev4bzovONnDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159826310489845.763262045172496; Mon, 24 Aug 2020 02:58:24 -0700 (PDT) Received: from localhost ([::1]:50372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kA9F9-0008Or-K6 for importer@patchew.org; Mon, 24 Aug 2020 05:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kA95s-0005kX-5u for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:48 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kA95p-0004qA-GL for qemu-devel@nongnu.org; Mon, 24 Aug 2020 05:48:47 -0400 Received: by mail-wm1-x32d.google.com with SMTP id t14so7537320wmi.3 for ; Mon, 24 Aug 2020 02:48:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Make A32/T32 code use the new fpstatus_ptr() API: get_fpstatus_ptr(0) -> fpstatus_ptr(FPST_FPCR) get_fpstatus_ptr(1) -> fpstatus_ptr(FPST_STD) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20200806104453.30393-3-peter.maydell@linaro.org --- target/arm/translate.c | 13 ---------- target/arm/translate-neon.c.inc | 28 ++++++++++----------- target/arm/translate-vfp.c.inc | 44 ++++++++++++++++----------------- 3 files changed, 36 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dd25adcf402..d34c1d351a6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,19 +1094,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 -static TCGv_ptr get_fpstatus_ptr(int neon) -{ - TCGv_ptr statusptr =3D tcg_temp_new_ptr(); - int offset; - if (neon) { - offset =3D offsetof(CPUARMState, vfp.standard_fp_status); - } else { - offset =3D offsetof(CPUARMState, vfp.fp_status); - } - tcg_gen_addi_ptr(statusptr, cpu_env, offset); - return statusptr; -} - static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 8fbe8cef9f6..f8f2cb1869f 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -181,7 +181,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcm= lah; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -218,7 +218,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fca= ddh; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -322,7 +322,7 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCM= LA_scalar *a) fn_gvec_ptr =3D (a->size ? gen_helper_gvec_fcmlas_idx : gen_helper_gvec_fcmlah_idx); opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -358,7 +358,7 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT= _scalar *a) =20 fn_gvec =3D a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_i= dx_b; opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->rm), @@ -1063,7 +1063,7 @@ static bool do_3same_fp(DisasContext *s, arg_3same *a= , VFPGen3OpSPFn *fn, return true; } =20 - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); + TCGv_ptr fpstatus =3D fpstatus_ptr(FPST_STD); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { tmp =3D neon_load_reg(a->vn, pass); tmp2 =3D neon_load_reg(a->vm, pass); @@ -1091,7 +1091,7 @@ static bool do_3same_fp(DisasContext *s, arg_3same *a= , VFPGen3OpSPFn *fn, uint32_t rn_ofs, uint32_t rm_ofs, \ uint32_t oprsz, uint32_t maxsz) \ { \ - TCGv_ptr fpst =3D get_fpstatus_ptr(1); \ + TCGv_ptr fpst =3D fpstatus_ptr(FPST_STD); \ tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ oprsz, maxsz, 0, FUNC); \ tcg_temp_free_ptr(fpst); \ @@ -1287,7 +1287,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3sa= me *a, VFPGen3OpSPFn *fn) * early. Since Q is 0 there are always just two passes, so instead * of a complicated loop over each pass we just unroll. */ - fpstatus =3D get_fpstatus_ptr(1); + fpstatus =3D fpstatus_ptr(FPST_STD); tmp =3D neon_load_reg(a->vn, 0); tmp2 =3D neon_load_reg(a->vn, 1); fn(tmp, tmp, tmp2, fpstatus); @@ -1790,7 +1790,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, return true; } =20 - fpstatus =3D get_fpstatus_ptr(1); + fpstatus =3D fpstatus_ptr(FPST_STD); shiftv =3D tcg_const_i32(a->shift); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { tmp =3D neon_load_reg(a->vm, pass); @@ -2591,7 +2591,7 @@ static bool trans_VMLS_2sc(DisasContext *s, arg_2scal= ar *a) #define WRAP_FP_FN(WRAPNAME, FUNC) \ static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \ { \ - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); \ + TCGv_ptr fpstatus =3D fpstatus_ptr(FPST_STD); \ FUNC(rd, rn, rm, fpstatus); \ tcg_temp_free_ptr(fpstatus); \ } @@ -3480,7 +3480,7 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2= misc *a) return true; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); tmp =3D neon_load_reg(a->vm, 0); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); @@ -3528,7 +3528,7 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2= misc *a) return true; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); tmp3 =3D tcg_temp_new_i32(); tmp =3D neon_load_reg(a->vm, 0); @@ -3838,7 +3838,7 @@ static bool do_2misc_fp(DisasContext *s, arg_2misc *a, return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); fn(tmp, tmp, fpst); @@ -3932,7 +3932,7 @@ static bool do_vrint(DisasContext *s, arg_2misc *a, i= nt rmode) return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { @@ -3993,7 +3993,7 @@ static bool do_vcvt(DisasContext *s, arg_2misc *a, in= t rmode, bool is_signed) return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_shift =3D tcg_const_i32(0); tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index d376bd1c1ad..4eeafb494ad 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -359,7 +359,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return true; } =20 - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -422,7 +422,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return true; } =20 - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_shift =3D tcg_const_i32(0); =20 @@ -1231,7 +1231,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpS= PFn *fn, f0 =3D tcg_temp_new_i32(); f1 =3D tcg_temp_new_i32(); fd =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 neon_load_reg32(f0, vn); neon_load_reg32(f1, vm); @@ -1314,7 +1314,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, f0 =3D tcg_temp_new_i64(); f1 =3D tcg_temp_new_i64(); fd =3D tcg_temp_new_i64(); - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 neon_load_reg64(f0, vn); neon_load_reg64(f1, vm); @@ -1796,7 +1796,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); neon_store_reg32(vd, a->vd); =20 @@ -1887,7 +1887,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); neon_store_reg64(vd, a->vd); =20 @@ -2171,7 +2171,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2208,7 +2208,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2237,7 +2237,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); =20 @@ -2274,7 +2274,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); @@ -2304,7 +2304,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRIN= TR_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints(tmp, tmp, fpst); neon_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2336,7 +2336,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd(tmp, tmp, fpst); neon_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2360,7 +2360,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRIN= TZ_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tmp, tmp, fpst); @@ -2397,7 +2397,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tmp, tmp, fpst); @@ -2424,7 +2424,7 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRIN= TX_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints_exact(tmp, tmp, fpst); neon_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2456,7 +2456,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd_exact(tmp, tmp, fpst); neon_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2535,7 +2535,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) =20 vm =3D tcg_temp_new_i32(); neon_load_reg32(vm, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f32 */ gen_helper_vfp_sitos(vm, vm, fpst); @@ -2571,7 +2571,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); neon_load_reg32(vm, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f64 */ gen_helper_vfp_sitod(vd, vm, fpst); @@ -2637,7 +2637,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) vd =3D tcg_temp_new_i32(); neon_load_reg32(vd, a->vd); =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -2702,7 +2702,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) vd =3D tcg_temp_new_i64(); neon_load_reg64(vd, a->vd); =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -2755,7 +2755,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i32(); neon_load_reg32(vm, a->vm); =20 @@ -2797,7 +2797,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); neon_load_reg64(vm, a->vm); --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LAl/MClU8bQ+8K7XrIqILgs8EvZ3f66imhAW3H8aksA=; b=W693syUvpL+PtHq97ntok6Q89KZ5UPLzfpJrOwifAIMzug17uJ7ixcH1I00DImmHx5 7ioJLTn7wJAdM2xzbEovAfmnKO/+ok4ZxgbWDONRdkwkwtlhCezTDlS8t5dYJr7o47Vv kOpsxNUUgctDJcm2IbffSKoXkN9KR2dlXS3kqDjXLu6YmvEn46Oj7TCidg+tjTTMHwbP a2z23Gt/hXxtOx/QFP7STR90jlDkV4mS7ZNrtP6TI6WUGqrvaVmjY7OzH7mP1uXMf48I jTLnxPgIl5qKtQYXyNOnjnMxIA+WPq5S7JIFZGAIeEl93zW3i+1ahnejS8IM16tFvIXH bhVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAl/MClU8bQ+8K7XrIqILgs8EvZ3f66imhAW3H8aksA=; b=HMftP6r/Mo2fgz+RNOqhxwke4mP2E6MKXBzkfJrs18kHq5+aCsT9ceJrVsj5hdC0cA RNWN4KGdFuyfMflptj/00Ri+dktKz0NezCQoZZaPuuxQiOx0o3MeAsjr4bmUwTxC0bSR FxOCte30oB+3/rLJw3HazVqgutlBH2lXJcIxXG+qlsj0VX83XzqIcNZ6TOWD5FCobKtW htJljbIAV26lziGe/sf+mf7mkNhqco8Lo5ycAVa+0WH/HcSATsZlKRfClJgHRoRn+o/u Nm5UWM3HTNdlTt7RPM99BPBiRER6/ntTnMFnNq7qmMP6MDuNV4yZLpiiuX8+5kkxr5wT 2/lA== X-Gm-Message-State: AOAM530x1j4spagHmzfb21mW/25aJXBDPU0wnRfvRnRVr1BWhvLxh8mD o30B9UxPNqerkjy1y3peWhVlymQPHnLe9K9x X-Google-Smtp-Source: ABdhPJwy8SxikkvuJvK+IAq9aY3jf7gUSf7cbQleJ+Y1nE4zOr4hKpjUenaX8WGb9cD8bAHG/VxThw== X-Received: by 2002:a5d:5352:: with SMTP id t18mr4919353wrv.407.1598262524259; Mon, 24 Aug 2020 02:48:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/27] target/arm: Implement FPST_STD_F16 fpstatus Date: Mon, 24 Aug 2020 10:48:10 +0100 Message-Id: <20200824094811.15439-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Architecturally, Neon FP16 operations use the "standard FPSCR" like all other Neon operations. However, this is defined in the Arm ARM pseudocode as "a fixed value, except that FZ16 (and AHP) follow the FPSCR bits". In QEMU, the softfloat float_status doesn't include separate flush-to-zero for FP16 operations, so we must keep separate fp_status for "Neon non-FP16" and "Neon fp16" operations, in the same way we do already for the non-Neon "fp_status" vs "fp_status_f16". Add the extra float_status field to the CPU state structure, ensure it is correctly initialized and updated on FPSCR writes, and make fpstatus_ptr(FPST_STD_F16) return a pointer to it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20200806104453.30393-4-peter.maydell@linaro.org --- target/arm/cpu.h | 9 ++++++++- target/arm/translate.h | 3 ++- target/arm/cpu.c | 3 +++ target/arm/vfp_helper.c | 5 +++++ 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9d2845c1797..ac857bdc2c1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -609,6 +609,8 @@ typedef struct CPUARMState { * fp_status: is the "normal" fp status. * fp_status_fp16: used for half-precision calculations * standard_fp_status : the ARM "Standard FPSCR Value" + * standard_fp_status_fp16 : used for half-precision + * calculations with the ARM "Standard FPSCR Value" * * Half-precision operations are governed by a separate * flush-to-zero control bit in FPSCR:FZ16. We pass a separate @@ -619,15 +621,20 @@ typedef struct CPUARMState { * Neon) which the architecture defines as controlled by the * standard FPSCR value rather than the FPSCR. * + * The "standard FPSCR but for fp16 ops" is needed because + * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than + * using a fixed value for it. + * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the three fp statuses. This relies on the + * OR of the flags in the four fp statuses. This relies on the * only thing which needs to read the exception flags being * an explicit FPSCR read. */ float_status fp_status; float_status fp_status_f16; float_status standard_fp_status; + float_status standard_fp_status_f16; =20 /* ZCR_EL[1-3] */ uint64_t zcr_el[4]; diff --git a/target/arm/translate.h b/target/arm/translate.h index e3680e65479..6d6d4c0f425 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -436,7 +436,8 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour = flavour) offset =3D offsetof(CPUARMState, vfp.standard_fp_status); break; case FPST_STD_F16: - /* Not yet used or implemented: fall through to assert */ + offset =3D offsetof(CPUARMState, vfp.standard_fp_status_f16); + break; default: g_assert_not_reached(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 111579554fb..6b382fcd60e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -391,12 +391,15 @@ static void arm_cpu_reset(DeviceState *dev) set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); + set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.fp_status_f16); + set_float_detect_tininess(float_tininess_before_rounding, + &env->vfp.standard_fp_status_f16); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 60dcd4bf145..64266ece620 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -93,6 +93,8 @@ static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) /* FZ16 does not generate an input denormal exception. */ i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) & ~float_flag_input_denormal); + i |=3D (get_float_exception_flags(&env->vfp.standard_fp_status_f16) + & ~float_flag_input_denormal); return vfp_exceptbits_from_host(i); } =20 @@ -124,7 +126,9 @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uin= t32_t val) if (changed & FPCR_FZ16) { bool ftz_enabled =3D val & FPCR_FZ16; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status= _f16); } if (changed & FPCR_FZ) { bool ftz_enabled =3D val & FPCR_FZ; @@ -146,6 +150,7 @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uin= t32_t val) set_float_exception_flags(i, &env->vfp.fp_status); set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); + set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); } =20 #else --=20 2.20.1 From nobody Sun May 19 00:42:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q6sm24877057wma.22.2020.08.24.02.48.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2020 02:48:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MO+LUQ5wKXjbzpP+WR/DhW7XRCUf7wjkORTiMAEjiYg=; b=iJZGVD7yFVrgSZ6IBzvG6vMYSKgMNKWR+s4K9rVbdMQDfggIL4yGgNdSurMTyGuWBC PxrvzSIKwDkITxnN+fIgFtpsXW/6e/T7uvhLQ3qn3E0AIJ/C9R5KrDdMlyJkpbEPGGwU nwIXkhDx0aqTgRl5SQc7RXWbSMtwdCZABLVlvrYXU9yGFvkGcY0q3s0e464JK1Ohmn6t 54ZfmSl5nVrS8u6Z6ukiSNoI9IEEUdgvHHwQVPzG9t/+zP28L+DJvtWCFeiQaSKuiJz7 Xz64uDqz623KkC/DwUUJ+JW2ewmOebUtMe6rYGYXFbAdc/+DNQyfhmtIl1bUsfRtOMww fTsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MO+LUQ5wKXjbzpP+WR/DhW7XRCUf7wjkORTiMAEjiYg=; b=QqsbdtEpI+Rqn5It6nrKxujZev+ODzDaJkM3fi7vJnpMm1Ypc1t/7XcVfRkM2j5vJw lbpgQ0X3RNyr6Upc9l9Pu1Z5VyxOIxkIwxz2Ax3vrUOwCSzw4v01SklWfDBMff3l6hNv eORmEHxUZAq5A+YjO+5a8+0FZg8ZBNfj9FIfawVhRBDcglwNOiICV5cIhyaCEYG08qew DuC60xMnodx9cVzV4SBGSQSYc6kcOBFZoe9eDIPihvKNGwsJBHslGtqxb68lPUE6cd9g lltH3RlEt9XsYuZCb8mGMjxnLK2gzjJZRVo5W1s8Bbs+GepYWD/Wfn8S5hr0AEVLhvYS 6MuA== X-Gm-Message-State: AOAM530GOuHunvg4wNEWT9a/RbgKctErO/F+XiZoS1BSFzB408hDmpKU ZLsEwAOo2Ns+TadDGF+lfX0HxhKxuO0rbvqT X-Google-Smtp-Source: ABdhPJysf457axYMxmJp1kxV6Kn05LGzez9Df79tXsE+B9612a/Tj4tZq29xfWoboGv0ooiALoWuVg== X-Received: by 2002:a7b:cd88:: with SMTP id y8mr4739021wmj.14.1598262525070; Mon, 24 Aug 2020 02:48:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/27] target/arm: Use correct FPST for VCMLA, VCADD on fp16 Date: Mon, 24 Aug 2020 10:48:11 +0100 Message-Id: <20200824094811.15439-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org> References: <20200824094811.15439-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) When we implemented the VCMLA and VCADD insns we put in the code to handle fp16, but left it using the standard fp status flags. Correct them to use FPST_STD_F16 for fp16 operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20200806104453.30393-5-peter.maydell@linaro.org --- target/arm/translate-neon.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index f8f2cb1869f..9879731a521 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -181,7 +181,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(FPST_STD); + fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcm= lah; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -218,7 +218,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(FPST_STD); + fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fca= ddh; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -322,7 +322,7 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCM= LA_scalar *a) fn_gvec_ptr =3D (a->size ? gen_helper_gvec_fcmlas_idx : gen_helper_gvec_fcmlah_idx); opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(FPST_STD); + fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), --=20 2.20.1