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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 6 ++++++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 +++++++++++++++- target/riscv/csr.c | 25 ++++++++++++++++++++++++- 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9ef20fe89a..08d2c10a024 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -317,6 +317,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArr= ay *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); @@ -360,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ul= ong); =20 #define TB_FLAGS_MMU_MASK 3 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; @@ -410,11 +412,15 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, =20 #ifdef CONFIG_USER_ONLY flags |=3D TB_FLAGS_MSTATUS_FS; + flags |=3D TB_FLAGS_MSTATUS_VS; #else flags |=3D cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { flags |=3D env->mstatus & MSTATUS_FS; } + if (riscv_cpu_vector_enabled(env)) { + flags |=3D env->mstatus & MSTATUS_VS; + } #endif *pflags =3D flags; } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b5a7e..a8b31208833 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -367,6 +367,7 @@ #define MSTATUS_SPIE 0x00000020 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae34349..3fae736529a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -108,10 +108,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | + MSTATUS_VS; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6a96a01b1cf..b0413f52d77 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) return -1; } env->mstatus |=3D MSTATUS_FS; + env->mstatus |=3D MSTATUS_VS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; if (vs(env, csrno) >=3D 0) { @@ -210,6 +211,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, ta= rget_ulong *val) =20 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxrm =3D val; return 0; } @@ -222,6 +230,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxsat =3D val; return 0; } @@ -234,6 +249,13 @@ static int read_vstart(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vstart =3D val; return 0; } @@ -400,7 +422,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; #if defined(TARGET_RISCV64) /* * RV32: MPV and MTL are not in mstatus. The current plan is to @@ -412,6 +434,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mstatus =3D (mstatus & ~mask) | (val & mask); =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | + ((mstatus & MSTATUS_VS) =3D=3D MSTATUS_VS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; --=20 2.17.1