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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id d9sm16478588pgv.45.2020.08.17.01.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2020 01:51:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PeNRirOsAYetV+xE0dMFlxFMaG6kB8KyHDl0oM6vhPg=; b=Mi6GU1ZHrB3tXhXAtm5y9Uhbng5e1lOuqdgtvxyLdf8Qz7yEEKp486bEgE87PRZms2 Sje5dOtup0/XjKJ0WkCa/VzXFGVTuOxYt9iSOl3gWFFXv4wVMpiKHCgXKg3d8PFLS2Y0 BExNRdQ1mHz+9rRVea4CJJ5QzNMm6LOhe+3dgJko4Yl8oguYjRu0o/+53rrqKmFaky7d GOGJLKpb+7wWtDgRNTjbtMAvAguzXfdKOWv/ZSzhGI1h1T0JU38vG3BcRQfocvatt8LY 43rh5Vy/VdsW9aiCx79oB+tBmexrE9Nfq4s2+y0aaYlcDzw7f6G9/qwAHwJWQB+FR2zv Vb4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PeNRirOsAYetV+xE0dMFlxFMaG6kB8KyHDl0oM6vhPg=; b=hPkZ3PpHuFzwtfYEgBfFW4TyFEGF0aqqLRBGTqTELFW1V61+4+AJvqCsP4FDKaqjsE 9TGiBnPfl9irGcRXy+JK4lEHBOjjpafRAHH68GnH2Q3X0jhI9VftVTioY9KRtB7SULpA wwKFueaGeYQO298IBwmH8hMr9K9dcE0liHuxE0EGtXCn/v6o4hqd6Wgup0goWPRx+RFn tVikCeYKUUlJMhZJKlWOcFk1ZHnnWAEBTpPR61lJExfyHq3cHssOKsU0uK7jMaWYazpy Rzf5GmZPXLKpHeHtWhpuU//P+FcM6mJ41WjBYpD6Z4PbGZrOfEDQJ1rNmGzxiwG76RAu IXbQ== X-Gm-Message-State: AOAM533kXfiKiaTq6jO0CE5fLTUFaiIkz8nTurA1uv9k7s2x6m71jQQV 8ZwlvoC4kraWcvoyjukxLgoeEmyAECeeFA== X-Google-Smtp-Source: ABdhPJw66PmA7IeJjOAhKY1a6JX9ieUzL0pqRdA0zJf+BRgjp8zjFA1dWphEiC2hVy9F0EEJCHgA3A== X-Received: by 2002:a17:90a:c591:: with SMTP id l17mr11453226pjt.17.1597654276410; Mon, 17 Aug 2020 01:51:16 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Date: Mon, 17 Aug 2020 16:49:10 +0800 Message-Id: <20200817084955.28793-26-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200817084955.28793-1-frank.chang@sifive.com> References: <20200817084955.28793-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1035.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 43 ++++++++++++++++++------- target/riscv/insn_trans/trans_rvv.inc.c | 12 ++++++- 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b5e6429015..715faed8824 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -376,18 +376,27 @@ FIELD(TB_FLAGS, SEW, 6, 3) FIELD(TB_FLAGS, VILL, 11, 1) =20 /* - * A simplification for VLMAX - * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * =3D (VLEN << LMUL) / (8 << SEW) - * =3D (VLEN << LMUL) >> (SEW + 3) - * =3D VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX =3D vlen >> (vsew + 3 - lmul) + * e.g. vlen =3D 256 bits, SEW =3D 16, LMUL =3D 1/8 + * =3D> VLMAX =3D vlen >> (1 + 3 - (-3)) + * =3D 256 >> 7 + * =3D 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew =3D FIELD_EX64(vtype, VTYPE, VSEW); - lmul =3D FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew =3D FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul =3D sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 @@ -400,12 +409,22 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax << sew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) + && (maxsz >=3D 8); flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 334e1fc123b..2c6efce00a7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1268,7 +1268,17 @@ GEN_VEXT_TRANS(vamomaxuei64_v, 64, 35, rwdvm, amo_op= , amo_check) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale =3D s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) { --=20 2.17.1