From nobody Tue Feb 10 17:34:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1597314866; cv=none; d=zohomail.com; s=zohoarc; b=OCKOxPuSRbEzLFd5L7Vddey9qpB4WXQLVdnSFXt5FtnqmxjP2g22NAAQ8vUSpdrja9DD2oQv0hdlJS4KgggFnLdeWvd4W2v5gRSleOk4nUfndw6/x6F50HQl3soqZ+7L8Yj5haxESXiP1jGGWof9j1KqffXoRYEhi0dnp7wIfkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597314866; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4KE/dJj4bo8W4MEDEjEwbFHYyFtdedSa5R2rjP6q5x8=; b=DNSE2GuXozm8Y/pBQ06HIuN70HaJh6P1OiyOuEWhFLh1EV14434Og3CkZiLfnVYOrZydayfcKzJMAAHdx7Oy16Er6aPq92ye37O3T2uNpCYJCJVOCI2iVks7izwj6m4v2bCJ9nBpspWmpVxpI37tuH9aGT5F1i5C6U09wSlkFhE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1597314866134885.789014508591; Thu, 13 Aug 2020 03:34:26 -0700 (PDT) Received: from localhost ([::1]:37248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6AYy-0002vg-Uh for importer@patchew.org; Thu, 13 Aug 2020 06:34:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6AXE-00008M-3Y; Thu, 13 Aug 2020 06:32:36 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4181 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6AXA-0006oz-Ef; Thu, 13 Aug 2020 06:32:35 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 10802DDD0521AA55BFD7; Thu, 13 Aug 2020 18:32:27 +0800 (CST) Received: from localhost.localdomain (10.175.104.175) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Thu, 13 Aug 2020 18:32:20 +0800 From: Peng Liang To: , Subject: [RFC 5/9] target/arm: introduce CPU feature dependency mechanism Date: Thu, 13 Aug 2020 18:26:53 +0800 Message-ID: <20200813102657.2588720-6-liangpeng10@huawei.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200813102657.2588720-1-liangpeng10@huawei.com> References: <20200813102657.2588720-1-liangpeng10@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.175] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=liangpeng10@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/13 06:32:27 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, zhang.zhanghailiang@huawei.com, mst@redhat.com, cohuck@redhat.com, xiexiangyou@huawei.com, Peng Liang , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some CPU features are dependent on other CPU features. For example, ID_AA64PFR0_EL1.FP field and ID_AA64PFR0_EL1.AdvSIMD must have the same value, which means FP and ADVSIMD are dependent on each other, FPHP and ADVSIMDHP are dependent on each other. This commit introduces a mechanism for CPU feature dependency in AArch64. We build a directed graph from the CPU feature dependency relationship, each edge from->to means the `to` CPU feature is dependent on the `from` CPU feature. And we will automatically enable/disable CPU feature according to the directed graph. For example, a, b, and c CPU features are in relationship a->b->c, which means c is dependent on b and b is dependent on a. If c is enabled by user, then a and b is enabled automatically. And if a is disabled by user, then b and c is disabled automatically. Signed-off-by: zhanghailiang Signed-off-by: Peng Liang --- target/arm/cpu.c | 129 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 113cf4a9e7..4e67b8f22c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1418,6 +1418,103 @@ static struct CPUFeatureInfo cpu_features[] =3D { }, }; =20 +typedef struct CPUFeatureDep { + CPUFeatureInfo from, to; +} CPUFeatureDep; + +static const CPUFeatureDep feature_dependencies[] =3D { + { + .from =3D FIELD_INFO(ID_AA64PFR0, FP, true, 0, 0xf, false), + .to =3D FIELD_INFO(ID_AA64PFR0, ADVSIMD, true, 0, 0xf, false), + }, + { + .from =3D FIELD_INFO(ID_AA64PFR0, ADVSIMD, true, 0, 0xf, false), + .to =3D FIELD_INFO(ID_AA64PFR0, FP, true, 0, 0xf, false), + }, + { + .from =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_FP_LENGTH, + .shift =3D R_ID_AA64PFR0_FP_SHIFT, .sign =3D true, .min_value = =3D 1, + .ni_value =3D 0, .name =3D "FPHP", .is_32bit =3D false, + }, + .to =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_ADVSIMD_LENGTH, + .shift =3D R_ID_AA64PFR0_ADVSIMD_SHIFT, .sign =3D true, .min_v= alue =3D 1, + .ni_value =3D 0, .name =3D "ADVSIMDHP", .is_32bit =3D false, + }, + }, + { + .from =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_ADVSIMD_LENGTH, + .shift =3D R_ID_AA64PFR0_ADVSIMD_SHIFT, .sign =3D true, .min_v= alue =3D 1, + .ni_value =3D 0, .name =3D "ADVSIMDHP", .is_32bit =3D false, + }, + .to =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_FP_LENGTH, + .shift =3D R_ID_AA64PFR0_FP_SHIFT, .sign =3D true, .min_value = =3D 1, + .ni_value =3D 0, .name =3D "FPHP", .is_32bit =3D false, + }, + }, + { + + .from =3D FIELD_INFO(ID_AA64ISAR0, AES, false, 1, 0, false), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_AES_LENGTH, + .shift =3D R_ID_AA64ISAR0_AES_SHIFT, .sign =3D false, .min_val= ue =3D 2, + .ni_value =3D 1, .name =3D "PMULL", .is_32bit =3D false, + }, + }, + { + + .from =3D FIELD_INFO(ID_AA64ISAR0, SHA2, false, 1, 0, false), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "SHA512", .is_32bit =3D false, + }, + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR1, LRCPC, false, 1, 0, false), + .to =3D { + .reg =3D ID_AA64ISAR1, .length =3D R_ID_AA64ISAR1_LRCPC_LENGTH, + .shift =3D R_ID_AA64ISAR1_LRCPC_SHIFT, .sign =3D false, .min_v= alue =3D 2, + .ni_value =3D 1, .name =3D "ILRCPC", .is_32bit =3D false, + }, + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR0, SM3, false, 1, 0, false), + .to =3D FIELD_INFO(ID_AA64ISAR0, SM4, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR0, SM4, false, 1, 0, false), + .to =3D FIELD_INFO(ID_AA64ISAR0, SM3, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR0, SHA1, false, 1, 0, false), + .to =3D FIELD_INFO(ID_AA64ISAR0, SHA2, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR0, SHA1, false, 1, 0, false), + .to =3D FIELD_INFO(ID_AA64ISAR0, SHA3, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO(ID_AA64ISAR0, SHA3, false, 1, 0, false), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "SHA512", .is_32bit =3D false, + }, + }, + { + .from =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "SHA512", .is_32bit =3D false, + }, + .to =3D FIELD_INFO(ID_AA64ISAR0, SHA3, false, 1, 0, false), + }, +}; + static void arm_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1454,13 +1551,45 @@ static void arm_cpu_set_bit_prop(Object *obj, Visit= or *v, const char *name, } =20 if (value) { + if (object_property_get_bool(obj, feat->name, NULL)) { + return; + } isar->regs[feat->reg] =3D deposit64(isar->regs[feat->reg], feat->shift, feat->length, feat->min_value); + /* Auto enable the features which current feature is dependent on.= */ + for (int i =3D 0; i < ARRAY_SIZE(feature_dependencies); ++i) { + const CPUFeatureDep *d =3D &feature_dependencies[i]; + if (strcmp(d->to.name, feat->name) !=3D 0) { + continue; + } + + object_property_set_bool(obj, d->from.name, true, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } } else { + if (!object_property_get_bool(obj, feat->name, NULL)) { + return; + } isar->regs[feat->reg] =3D deposit64(isar->regs[feat->reg], feat->shift, feat->length, feat->ni_value); + /* Auto disable the features which are dependent on current featur= e. */ + for (int i =3D 0; i < ARRAY_SIZE(feature_dependencies); ++i) { + const CPUFeatureDep *d =3D &feature_dependencies[i]; + if (strcmp(d->from.name, feat->name) !=3D 0) { + continue; + } + + object_property_set_bool(obj, d->to.name, false, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } } } =20 --=20 2.18.4