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bh=O3rQyYFC2scFIz/XUUni2PfV2OOrFxGCh7tG7NMzdYM=; b=KcxgS2ZBnAVfrFryvSWF8bG69j0Yv3usWet1HAJn4PGjDzqwMEvqJgyQOHsteGJKE42AHP rZ9Fc0Rhmsr227hZrMmK0gK2C0PZu9jOQiJWb+jpeLWL71FosGL8Qr78xDlfDGb3kLVICD nk1MezzrsJryxSO7DZRfpcjcT3ouuRQ= X-MC-Unique: zw6DeT4zMQCO7K0OBtWUuA-1 From: P J P To: Peter Maydell , Paolo Bonzini Subject: [PATCH v4 2/9] pci-host: designware: add pcie-msi read method Date: Tue, 11 Aug 2020 17:11:26 +0530 Message-Id: <20200811114133.672647-3-ppandit@redhat.com> In-Reply-To: <20200811114133.672647-1-ppandit@redhat.com> References: <20200811114133.672647-1-ppandit@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ppandit@redhat.com X-Mimecast-Spam-Score: 0.001 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Prasad J Pandit Add pcie-msi mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun Reviewed-by: Li Qiang Reviewed-by: Peter Maydell Signed-off-by: Prasad J Pandit --- hw/pci-host/designware.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) Update v4: add explanatory comment and Reviewed-by tag -> https://lists.nongnu.org/archive/html/qemu-devel/2020-07/msg05315.html diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 8492c18991..db036aac71 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -63,6 +64,23 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } =20 +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + /* + * Attempts to read from the MSI address are undefined in + * the PCI specifications. For this hardware, the datasheet + * specifies that a read from the magic address is simply not + * intercepted by the MSI controller, and will go out to the + * AHB/AXI bus like any other PCI-device-initiated DMA read. + * This is not trivial to implement in QEMU, so since + * well-behaved guests won't ever ask a PCI device to DMA from + * this address we just log the missing functionality. + */ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -77,6 +95,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, } =20 static const MemoryRegionOps designware_pci_host_msi_ops =3D { + .read =3D designware_pcie_root_msi_read, .write =3D designware_pcie_root_msi_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { --=20 2.26.2