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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 13 ++++--- target/riscv/insn_trans/trans_rvv.inc.c | 51 +++++++++++++++++++++---- target/riscv/vector_helper.c | 25 +++++++++++- 4 files changed, 82 insertions(+), 13 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5ef37b9dc49..7539b4a5004 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -995,12 +995,18 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, en= v, i32) DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c25c03dfb7c..fae96194078 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -563,11 +563,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 101= 0111 @r2_vm vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm -vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm -vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm -vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm -vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm -vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm + +vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm +vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm +vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm +vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm +vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm +vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm +vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index e1627637aff..7db3de8e032 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2842,7 +2842,7 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr= *a) (s->sew !=3D 0); } =20 -#define GEN_OPFV_WIDEN_TRANS(NAME) \ +#define GEN_OPFV_WIDEN_TRANS(NAME, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_widen_check(s, a)) { \ @@ -2852,7 +2852,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, FRM_DYN); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2867,11 +2867,48 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ return false; \ } =20 -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, FRM_RTZ) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, FRM_RTZ) + +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV widening instructions ignore vs1 check */ + vext_check_dss(s, a->rd, 0, a->rs2, a->vm, false); +} + +#define GEN_OPFXV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfxv_widen_check(s, a)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over =3D gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v) +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c12d697c440..2f5a2dca336 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4066,6 +4066,7 @@ GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8) =20 /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger.*/ @@ -4081,19 +4082,41 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8) =20 /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat */ +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8) =20 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2) GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8) =20 /* - * vfwcvt.f.f.v vd, vs2, vm # + * vfwcvt.rtz.xu.f.v vd, vs2, vm + * Convert float to double-width unsigned integer, truncating + */ +RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) +RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) +GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_w, 4, 8) + +/* + * vfwcvt.rtz.x.f.v vd, vs2, vm + * Convert float to double-width signed integer, truncating. + */ +RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32) +RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64) +GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_w, 4, 8) + +/* + * vfwcvt.f.f.v vd, vs2, vm * Convert single-width float to double-width float. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) --=20 2.17.1