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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a10sm6042189wrx.15.2020.08.06.03.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2020 03:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UFF5f+eJ9S3MOWSlwF3nLC25z1jwDMEdd5QQVZv2OZA=; b=WyAihLEv0ZTl0tyI2mlk9FZFJ7wWDH3S4Qw3KcoEOYAxo07nlRIOxuXOgZvDmnaVXL gorDr7M1ofsi9VPFTUswEuTgr+TGvgKzNPCff9NdGwqM/UbRe5bxrIfxVIjqwZf4P7pp ZLE1YfMnFg2euqLg2K7rnp4k/wBa5Ytaz8UR681yRUV2oKRJn7zwJZ009pqI4iWXXcDG UjfBnbeCV32B85YoGPtFxneBZwmxoYFOSjZIqWs9Tw+sFkHpAMY6YFKBdIhzGs0kLIht 9xcgANQaG7BZ7eB/roPvgei50c4M0857twdxgVhExLxRVCP4c1XwKUeGaOb/GQbCvsmX ZPRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UFF5f+eJ9S3MOWSlwF3nLC25z1jwDMEdd5QQVZv2OZA=; b=ZuEw9ilPmeWjV8tj8QJVlxcf9OFlSKa0Es5PIRuqAeRv/ysgyJX0UAwLZuJVbS9Fqy GgLOrBtq62iRcNE9PKdDh0f349Uhc0T9YoaStWMvMeAxaXuOIVeqs/ggpg2VCLcUsmbF m6cAKk60dD1RtNnTre+qEfZnBmYgQeG5h4M1EyJNIWziSjYaaLpAohG6BDOL7o+leAUT jO1SmA7IvRyO491/lFBzwdwKBl7/xb3LG4fngwH8XOagj7/kxU+VKiUUBHL03LULlwX+ NFQ2IVTpCM4p/G/NwNsO98nUC5KMYtNTo2KUEmhb4waVEgX4aPIzkE/gjIyDxEX13aGG GrOQ== X-Gm-Message-State: AOAM530LmAarWWURpDA8i85ZnM8icJUfnXM2q6nUNwb5tDUnwkxawn5x MTPm77gb7DX+UKV6rY8iTjiBZw== X-Google-Smtp-Source: ABdhPJxhqdVVUDka4ftLPZATUq8SRgo6kLO6gsumjqx0yzi4VoYQytp+CWqoIqfVcf3lVBimjrBNMA== X-Received: by 2002:a1c:1d2:: with SMTP id 201mr6917750wmb.132.1596710698919; Thu, 06 Aug 2020 03:44:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/4] target/arm: Make A32/T32 use new fpstatus_ptr() API Date: Thu, 6 Aug 2020 11:44:51 +0100 Message-Id: <20200806104453.30393-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200806104453.30393-1-peter.maydell@linaro.org> References: <20200806104453.30393-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Make A32/T32 code use the new fpstatus_ptr() API: get_fpstatus_ptr(0) -> fpstatus_ptr(FPST_FPCR) get_fpstatus_ptr(1) -> fpstatus_ptr(FPST_STD) Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-neon.inc.c | 28 ++++++++++----------- target/arm/translate-vfp.inc.c | 44 ++++++++++++++++----------------- target/arm/translate.c | 13 ---------- 3 files changed, 36 insertions(+), 49 deletions(-) diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in= c.c index f6cb9215739..5158dd14ad2 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -181,7 +181,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcm= lah; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -218,7 +218,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fca= ddh; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), @@ -322,7 +322,7 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCM= LA_scalar *a) fn_gvec_ptr =3D (a->size ? gen_helper_gvec_fcmlas_idx : gen_helper_gvec_fcmlah_idx); opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -358,7 +358,7 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT= _scalar *a) =20 fn_gvec =3D a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_i= dx_b; opr_sz =3D (1 + a->q) * 8; - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->rm), @@ -1063,7 +1063,7 @@ static bool do_3same_fp(DisasContext *s, arg_3same *a= , VFPGen3OpSPFn *fn, return true; } =20 - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); + TCGv_ptr fpstatus =3D fpstatus_ptr(FPST_STD); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { tmp =3D neon_load_reg(a->vn, pass); tmp2 =3D neon_load_reg(a->vm, pass); @@ -1091,7 +1091,7 @@ static bool do_3same_fp(DisasContext *s, arg_3same *a= , VFPGen3OpSPFn *fn, uint32_t rn_ofs, uint32_t rm_ofs, \ uint32_t oprsz, uint32_t maxsz) \ { \ - TCGv_ptr fpst =3D get_fpstatus_ptr(1); \ + TCGv_ptr fpst =3D fpstatus_ptr(FPST_STD); \ tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ oprsz, maxsz, 0, FUNC); \ tcg_temp_free_ptr(fpst); \ @@ -1287,7 +1287,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3sa= me *a, VFPGen3OpSPFn *fn) * early. Since Q is 0 there are always just two passes, so instead * of a complicated loop over each pass we just unroll. */ - fpstatus =3D get_fpstatus_ptr(1); + fpstatus =3D fpstatus_ptr(FPST_STD); tmp =3D neon_load_reg(a->vn, 0); tmp2 =3D neon_load_reg(a->vn, 1); fn(tmp, tmp, tmp2, fpstatus); @@ -1790,7 +1790,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, return true; } =20 - fpstatus =3D get_fpstatus_ptr(1); + fpstatus =3D fpstatus_ptr(FPST_STD); shiftv =3D tcg_const_i32(a->shift); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { tmp =3D neon_load_reg(a->vm, pass); @@ -2591,7 +2591,7 @@ static bool trans_VMLS_2sc(DisasContext *s, arg_2scal= ar *a) #define WRAP_FP_FN(WRAPNAME, FUNC) \ static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \ { \ - TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); \ + TCGv_ptr fpstatus =3D fpstatus_ptr(FPST_STD); \ FUNC(rd, rn, rm, fpstatus); \ tcg_temp_free_ptr(fpstatus); \ } @@ -3480,7 +3480,7 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2= misc *a) return true; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); tmp =3D neon_load_reg(a->vm, 0); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); @@ -3528,7 +3528,7 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2= misc *a) return true; } =20 - fpst =3D get_fpstatus_ptr(true); + fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); tmp3 =3D tcg_temp_new_i32(); tmp =3D neon_load_reg(a->vm, 0); @@ -3838,7 +3838,7 @@ static bool do_2misc_fp(DisasContext *s, arg_2misc *a, return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); fn(tmp, tmp, fpst); @@ -3932,7 +3932,7 @@ static bool do_vrint(DisasContext *s, arg_2misc *a, i= nt rmode) return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { @@ -3993,7 +3993,7 @@ static bool do_vcvt(DisasContext *s, arg_2misc *a, in= t rmode, bool is_signed) return true; } =20 - fpst =3D get_fpstatus_ptr(1); + fpst =3D fpstatus_ptr(FPST_STD); tcg_shift =3D tcg_const_i32(0); tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 463253de90b..4e0458e4206 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -359,7 +359,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return true; } =20 - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -422,7 +422,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return true; } =20 - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 tcg_shift =3D tcg_const_i32(0); =20 @@ -1231,7 +1231,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpS= PFn *fn, f0 =3D tcg_temp_new_i32(); f1 =3D tcg_temp_new_i32(); fd =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 neon_load_reg32(f0, vn); neon_load_reg32(f1, vm); @@ -1314,7 +1314,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, f0 =3D tcg_temp_new_i64(); f1 =3D tcg_temp_new_i64(); fd =3D tcg_temp_new_i64(); - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); =20 neon_load_reg64(f0, vn); neon_load_reg64(f1, vm); @@ -1796,7 +1796,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); neon_store_reg32(vd, a->vd); =20 @@ -1887,7 +1887,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } - fpst =3D get_fpstatus_ptr(0); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); neon_store_reg64(vd, a->vd); =20 @@ -2171,7 +2171,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2208,7 +2208,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2237,7 +2237,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); =20 @@ -2274,7 +2274,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); @@ -2304,7 +2304,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRIN= TR_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints(tmp, tmp, fpst); neon_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2336,7 +2336,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd(tmp, tmp, fpst); neon_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2360,7 +2360,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRIN= TZ_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tmp, tmp, fpst); @@ -2397,7 +2397,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tmp, tmp, fpst); @@ -2424,7 +2424,7 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRIN= TX_sp *a) =20 tmp =3D tcg_temp_new_i32(); neon_load_reg32(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints_exact(tmp, tmp, fpst); neon_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2456,7 +2456,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) =20 tmp =3D tcg_temp_new_i64(); neon_load_reg64(tmp, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd_exact(tmp, tmp, fpst); neon_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); @@ -2535,7 +2535,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) =20 vm =3D tcg_temp_new_i32(); neon_load_reg32(vm, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f32 */ gen_helper_vfp_sitos(vm, vm, fpst); @@ -2571,7 +2571,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); neon_load_reg32(vm, a->vm); - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f64 */ gen_helper_vfp_sitod(vd, vm, fpst); @@ -2637,7 +2637,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) vd =3D tcg_temp_new_i32(); neon_load_reg32(vd, a->vd); =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -2702,7 +2702,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) vd =3D tcg_temp_new_i64(); neon_load_reg64(vd, a->vd); =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -2755,7 +2755,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i32(); neon_load_reg32(vm, a->vm); =20 @@ -2797,7 +2797,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return true; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); neon_load_reg64(vm, a->vm); diff --git a/target/arm/translate.c b/target/arm/translate.c index e1f5357c367..3bce39c953a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,19 +1094,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 -static TCGv_ptr get_fpstatus_ptr(int neon) -{ - TCGv_ptr statusptr =3D tcg_temp_new_ptr(); - int offset; - if (neon) { - offset =3D offsetof(CPUARMState, vfp.standard_fp_status); - } else { - offset =3D offsetof(CPUARMState, vfp.fp_status); - } - tcg_gen_addi_ptr(statusptr, cpu_env, offset); - return statusptr; -} - static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { --=20 2.20.1