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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, cota@braap.org, peter.puhov@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec_interrupt. The purpose of this set of changes is to set the groundwork so that an arch could move towards removing the BQL from the cpu_handle_interrupt/exception paths. This approach was suggested by Paolo Bonzini. For reference, here are two key posts in the discussion, explaining the reasoning/benefits of this approach. https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html Signed-off-by: Robert Foley --- target/hppa/int_helper.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 462747baf8..eda40bc5d9 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -94,12 +94,20 @@ void hppa_cpu_do_interrupt(CPUState *cs) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - int i =3D cs->exception_index; - target_ureg iaoq_f =3D env->iaoq_f; - target_ureg iaoq_b =3D env->iaoq_b; - uint64_t iasq_f =3D env->iasq_f; - uint64_t iasq_b =3D env->iasq_b; - + int i; + target_ureg iaoq_f; + target_ureg iaoq_b; + uint64_t iasq_f; + uint64_t iasq_b; + bool bql =3D !qemu_mutex_iothread_locked(); + if (bql) { + qemu_mutex_lock_iothread(); + } + i =3D cs->exception_index; + iaoq_f =3D env->iaoq_f; + iaoq_b =3D env->iaoq_b; + iasq_f =3D env->iasq_f; + iasq_b =3D env->iasq_b; #ifndef CONFIG_USER_ONLY target_ureg old_psw; =20 @@ -244,6 +252,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) env->cr[CR_IOR])); } cs->exception_index =3D -1; + if (bql) { + qemu_mutex_unlock_iothread(); + } } =20 bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -251,6 +262,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) #ifndef CONFIG_USER_ONLY HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; + qemu_mutex_lock_iothread(); =20 /* If interrupts are requested and enabled, raise them. */ if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { @@ -258,6 +270,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) hppa_cpu_do_interrupt(cs); return true; } + qemu_mutex_unlock_iothread(); #endif return false; } --=20 2.17.1