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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" As a prelude to making coproc insns use decodetree, split out the part of disas_coproc_insn() which does instruction decoding from the part which does the actual work, and make do_coproc_insn() handle the UNDEF-on-bad-permissions and similar cases itself rather than returning 1 to eventually percolate up to a callsite that calls unallocated_encoding() for it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 76 ++++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a2765fc60b2..cfdcf5281d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4544,34 +4544,12 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, = uint32_t rn_ofs, tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } =20 -static int disas_coproc_insn(DisasContext *s, uint32_t insn) +static void do_coproc_insn(DisasContext *s, int cpnum, int is64, + int opc1, int crn, int crm, int opc2, + bool isread, int rt, int rt2) { - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; const ARMCPRegInfo *ri; =20 - cpnum =3D (insn >> 8) & 0xf; - - is64 =3D (insn & (1 << 25)) =3D=3D 0; - if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { - /* cdp */ - return 1; - } - - crm =3D insn & 0xf; - if (is64) { - crn =3D 0; - opc1 =3D (insn >> 4) & 0xf; - opc2 =3D 0; - rt2 =3D (insn >> 16) & 0xf; - } else { - crn =3D (insn >> 16) & 0xf; - opc1 =3D (insn >> 21) & 7; - opc2 =3D (insn >> 5) & 7; - rt2 =3D 0; - } - isread =3D (insn >> 20) & 1; - rt =3D (insn >> 12) & 0xf; - ri =3D get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { @@ -4579,7 +4557,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) =20 /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { - return 1; + unallocated_encoding(s); + return; } =20 if (s->hstr_active || ri->accessfn || @@ -4653,14 +4632,15 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) /* Handle special cases first */ switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { case ARM_CP_NOP: - return 0; + return; case ARM_CP_WFI: if (isread) { - return 1; + unallocated_encoding(s); + return; } gen_set_pc_im(s, s->base.pc_next); s->base.is_jmp =3D DISAS_WFI; - return 0; + return; default: break; } @@ -4720,7 +4700,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) /* Write */ if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ - return 0; + return; } =20 if (is64) { @@ -4786,7 +4766,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) gen_lookup_tb(s); } =20 - return 0; + return; } =20 /* Unknown register; this might be a guest error or a QEMU @@ -4806,7 +4786,39 @@ static int disas_coproc_insn(DisasContext *s, uint32= _t insn) s->ns ? "non-secure" : "secure"); } =20 - return 1; + unallocated_encoding(s); + return; +} + +static int disas_coproc_insn(DisasContext *s, uint32_t insn) +{ + int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; + + cpnum =3D (insn >> 8) & 0xf; + + is64 =3D (insn & (1 << 25)) =3D=3D 0; + if (!is64 && ((insn & (1 << 4)) =3D=3D 0)) { + /* cdp */ + return 1; + } + + crm =3D insn & 0xf; + if (is64) { + crn =3D 0; + opc1 =3D (insn >> 4) & 0xf; + opc2 =3D 0; + rt2 =3D (insn >> 16) & 0xf; + } else { + crn =3D (insn >> 16) & 0xf; + opc1 =3D (insn >> 21) & 7; + opc2 =3D (insn >> 5) & 7; + rt2 =3D 0; + } + isread =3D (insn >> 20) & 1; + rt =3D (insn >> 12) & 0xf; + + do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2); + return 0; } =20 /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ --=20 2.20.1