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dkim=none (message not signed) header.d=none;nongnu.org; dmarc=none action=none header.from=leostella.com; From: Matthieu Bucchianeri To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH] target/ppc: Fix SPE unavailable exception triggering Date: Sat, 25 Jul 2020 12:14:36 -0700 Message-Id: <20200725191436.31828-1-matthieu.bucchianeri@leostella.com> X-Mailer: git-send-email 2.17.1 Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: DM3P110CA0022.NAMP110.PROD.OUTLOOK.COM (2001:489a:200:410::20) To SN5P110MB0543.NAMP110.PROD.OUTLOOK.COM (2001:489a:200:41c::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [2601:601:f01:e820:349c:f32e:2333:ec4c] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a5dbd490-585c-4502-87e3-08d830cf0685 X-MS-TrafficTypeDiagnostic: SN5P110MB0365: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: Content-Transfer-Encoding: quoted-printable X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=23.103.208.98; envelope-from=matthieu.bucchianeri@leostella.com; helo=USG02-BN3-obe.outbound.protection.office365.us X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/25 16:00:30 X-ACL-Warn: Detected OS = Windows 7 or 8 [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 25 Jul 2020 16:57:53 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthieu Bucchianeri , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @leostella.onmicrosoft.com) When emulating certain floating point instructions or vector instructions on PowerPC machines, QEMU did not properly generate the SPE/Embedded Floating- Point Unavailable interrupt. See the buglink further below for references to the relevant NXP documentation. This patch fixes the behavior of some evfs* instructions that were incorrectly emitting the interrupt. More importantly, this patch fixes the behavior of several efd* and ev* instructions that were not generating the interrupt. Triggering the interrupt for these instructions fixes lazy FPU/vector context switching on some operating systems like Linux. Without this patch, the result of some double-precision arithmetic could be corrupted due to the lack of proper saving and restoring of the upper 32-bit part of the general-purpose registers. Buglink: https://bugs.launchpad.net/qemu/+bug/1888918 Buglink: https://bugs.launchpad.net/qemu/+bug/1611394 Signed-off-by: Matthieu Bucchianeri --- target/ppc/translate/spe-impl.inc.c | 101 ++++++++++++++++++---------- 1 file changed, 66 insertions(+), 35 deletions(-) diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe= -impl.inc.c index 36b4d5654d..2e6e799a25 100644 --- a/target/ppc/translate/spe-impl.inc.c +++ b/target/ppc/translate/spe-impl.inc.c @@ -349,14 +349,24 @@ static inline void gen_evmergelohi(DisasContext *ctx) } static inline void gen_evsplati(DisasContext *ctx) { - uint64_t imm =3D ((int32_t)(rA(ctx->opcode) << 27)) >> 27; + uint64_t imm; + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + imm =3D ((int32_t)(rA(ctx->opcode) << 27)) >> 27; tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); } static inline void gen_evsplatfi(DisasContext *ctx) { - uint64_t imm =3D rA(ctx->opcode) << 27; + uint64_t imm; + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + imm =3D rA(ctx->opcode) << 27; tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); @@ -389,21 +399,37 @@ static inline void gen_evsel(DisasContext *ctx) static void gen_evsel0(DisasContext *ctx) { + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } gen_evsel(ctx); } static void gen_evsel1(DisasContext *ctx) { + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } gen_evsel(ctx); } static void gen_evsel2(DisasContext *ctx) { + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } gen_evsel(ctx); } static void gen_evsel3(DisasContext *ctx) { + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } gen_evsel(ctx); } @@ -518,6 +544,11 @@ static inline void gen_evmwsmia(DisasContext *ctx) { TCGv_i64 tmp; + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + gen_evmwsmi(ctx); /* rD :=3D rA * rB */ tmp =3D tcg_temp_new_i64(); @@ -531,8 +562,13 @@ static inline void gen_evmwsmia(DisasContext *ctx) static inline void gen_evmwsmiaa(DisasContext *ctx) { - TCGv_i64 acc =3D tcg_temp_new_i64(); - TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 acc; + TCGv_i64 tmp; + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } gen_evmwsmi(ctx); /* rD :=3D rA * rB */ @@ -892,8 +928,14 @@ static inline void gen_##name(DisasContext *ctx) = \ #define GEN_SPEFPUOP_CONV_32_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ { = \ - TCGv_i64 t0 =3D tcg_temp_new_i64(); = \ - TCGv_i32 t1 =3D tcg_temp_new_i32(); = \ + TCGv_i64 t0; = \ + TCGv_i32 t1; = \ + if (unlikely(!ctx->spe_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_SPEU); = \ + return; = \ + } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i32(); = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ gen_helper_##name(t1, cpu_env, t0); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); = \ @@ -903,8 +945,14 @@ static inline void gen_##name(DisasContext *ctx) = \ #define GEN_SPEFPUOP_CONV_64_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ { = \ - TCGv_i64 t0 =3D tcg_temp_new_i64(); = \ - TCGv_i32 t1 =3D tcg_temp_new_i32(); = \ + TCGv_i64 t0; = \ + TCGv_i32 t1; = \ + if (unlikely(!ctx->spe_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_SPEU); = \ + return; = \ + } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i32(); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(t0, cpu_env, t1); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ @@ -914,7 +962,12 @@ static inline void gen_##name(DisasContext *ctx) = \ #define GEN_SPEFPUOP_CONV_64_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ { = \ - TCGv_i64 t0 =3D tcg_temp_new_i64(); = \ + TCGv_i64 t0; = \ + if (unlikely(!ctx->spe_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_SPEU); = \ + return; = \ + } = \ + t0 =3D tcg_temp_new_i64(); = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ gen_helper_##name(t0, cpu_env, t0); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ @@ -923,13 +976,8 @@ static inline void gen_##name(DisasContext *ctx) = \ #define GEN_SPEFPUOP_ARITH2_32_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ { = \ - TCGv_i32 t0, t1; = \ - if (unlikely(!ctx->spe_enabled)) { = \ - gen_exception(ctx, POWERPC_EXCP_SPEU); = \ - return; = \ - } = \ - t0 =3D tcg_temp_new_i32(); = \ - t1 =3D tcg_temp_new_i32(); = \ + TCGv_i32 t0 =3D tcg_temp_new_i32(); = \ + TCGv_i32 t1 =3D tcg_temp_new_i32(); = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(t0, cpu_env, t0, t1); = \ @@ -958,13 +1006,8 @@ static inline void gen_##name(DisasContext *ctx) = \ #define GEN_SPEFPUOP_COMP_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ { = \ - TCGv_i32 t0, t1; = \ - if (unlikely(!ctx->spe_enabled)) { = \ - gen_exception(ctx, POWERPC_EXCP_SPEU); = \ - return; = \ - } = \ - t0 =3D tcg_temp_new_i32(); = \ - t1 =3D tcg_temp_new_i32(); = \ + TCGv_i32 t0 =3D tcg_temp_new_i32(); = \ + TCGv_i32 t1 =3D tcg_temp_new_i32(); = \ = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ @@ -1074,28 +1117,16 @@ GEN_SPEFPUOP_ARITH2_32_32(efsmul); GEN_SPEFPUOP_ARITH2_32_32(efsdiv); static inline void gen_efsabs(DisasContext *ctx) { - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); } static inline void gen_efsnabs(DisasContext *ctx) { - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); } static inline void gen_efsneg(DisasContext *ctx) { - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); 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