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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:17:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lIAWnZ0kGmaPMXxXhAaDX7KeOlS4ElOBc/y5+NIu9jI=; b=fAl+4JmGLef92i5d7ZnmTLeloBTWFijxEAC/C05KRKBEJAQ5wZfZ7vBwsnp6x6gRLI aRpZMFtfc5X62ppaaJxwsQONDTX8mWEuYrrnaFGG4lmCuNHsuBZekdlOsblPcGlB4yIu 1jredABBfPh2Ba94IG1pfugvTmmd1QQ8PhlS/WuE4prA5GTggEBPnX2+TlektnqSM/Hn 52AR/CQe8oKJv2EdVnmRSHBu6xTiB64rndRUxhye3VVAensIfsQ+Fp8qyF3UMgoogs4I q7GLBHgw4th1jDOuGRFRqnD+RSaRKTG81BJmo1q1qRIqsUTpJUnxHouDByxtHWp7gtY3 pWWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lIAWnZ0kGmaPMXxXhAaDX7KeOlS4ElOBc/y5+NIu9jI=; b=CAszbH3KJPbU7NYo+qm9/a5Anli5eAPfoJv4nhdeBXoleJoCfWlH9rkDnJSZOEfBgH InfvkOcbcQY9AC0PVjuYsaiGRn8/fwgp0MC8kONN8obFk3xGQ+4Rfz/C0U/D9JwuXEHB 3ZhZyBO0hz3S4tKTVhlqB3MQpXYU91mlyHG8rSeMzJDe53cjnySbQBUTfviXPZOfkr9M OydSDBzLkeE4C1t3rSaB4TxN52JPUHFsUpWiMjfdLmpujZolhckhtmc/q4QUJ4k7IfJr zdujlP/sOBdOxWRRmBDHx8ojClxeHZ5rGdSFpAcsWCp3HAumnJdvvtGtum0Xd12jl+mE tLdQ== X-Gm-Message-State: AOAM533tbDtFwZaLbjMrSEkogPSxwi5SF2lBye94PCWeA5FX9h0IzOmy F5vfhPv7K8fhE6sIQGo0KJ21C3Pxq7E= X-Google-Smtp-Source: ABdhPJyElK+jTC6uT3yuXXlo0UodDCf+khJgxVo2b1iKT1siY25JKg5zkJHj6zkC5d0TOXe3NES1Vg== X-Received: by 2002:a17:902:b185:: with SMTP id s5mr26253436plr.211.1595409434101; Wed, 22 Jul 2020 02:17:14 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support Date: Wed, 22 Jul 2020 17:15:24 +0800 Message-Id: <20200722091641.8834-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 24 ++++++------------------ target/riscv/cpu.h | 2 -- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..2800953e6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -106,11 +106,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver =3D vext_ver; -} - static void set_feature(CPURISCVState *env, int feature) { env->features |=3D (1ULL << feature); @@ -339,7 +334,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); int priv_version =3D PRIV_VERSION_1_11_0; - int vext_version =3D VEXT_VERSION_0_07_1; target_ulong target_misa =3D 0; Error *local_err =3D NULL; =20 @@ -363,7 +357,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 set_priv_version(env, priv_version); - set_vext_version(env, vext_version); =20 if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -455,19 +448,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) return; } if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version =3D VEXT_VERSION_0_07_1; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; } else { - qemu_log("vector verison is not specified, " - "use the default value v0.7.1\n"); + qemu_log("vector version is not specified\n"); + return; } - set_vext_version(env, vext_version); } =20 set_misa(env, RVXLEN | target_misa); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eef20ca6e5..6766dcd914 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,8 +79,6 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 -#define VEXT_VERSION_0_07_1 0x00000701 - #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 24 ++++++++++++++++++------ target/riscv/cpu.h | 2 ++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2800953e6c..641c803089 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -106,6 +106,11 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 +static void set_vext_version(CPURISCVState *env, int vext_ver) +{ + env->vext_ver =3D vext_ver; +} + static void set_feature(CPURISCVState *env, int feature) { env->features |=3D (1ULL << feature); @@ -334,6 +339,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); int priv_version =3D PRIV_VERSION_1_11_0; + int vext_version =3D VEXT_VERSION_0_09_0; target_ulong target_misa =3D 0; Error *local_err =3D NULL; =20 @@ -357,6 +363,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 set_priv_version(env, priv_version); + set_vext_version(env, vext_version); =20 if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -448,14 +455,19 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) return; } if (cpu->cfg.vext_spec) { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.9")) { + vext_version =3D VEXT_VERSION_0_09_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } } else { - qemu_log("vector version is not specified\n"); - return; + qemu_log("vector version is not specified, " + "use the default value v0.9\n"); } + set_vext_version(env, vext_version); } =20 set_misa(env, RVXLEN | target_misa); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6766dcd914..378f6e82bf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,6 +79,8 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 +#define VEXT_VERSION_0_09_0 0x00000900 + #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AsV8nXeGOBZSH3zrEUqd9iliNzH/znlE74D2q/iZRbA=; b=WKZHXpsKzctP/i1YhVCpIyBr6v9tYK32nFXo0WeWDDOxvbUqE4YiKto45Ic5fT6129 fNDa5WnmJQRX/dx9OiL76ax7d9ZfgQTYvA51NF21D7ah40Me40NjZGK/4NRHjHFiLoR8 tNYNBmEQih4w/pOWs3Krrvbl2k3pr+FX+LM6GZkwDZgFJKqjurXp7i4u0npL/+BFomZn +TMv1Ycamgaa7zJQ1RGs128IB1yyqnSE71wXH4Fae2FoiyiQczHrwt5ZNIwc85domgZX hN0qm0YTkJrz1Qup4PxoxYVl64cQWdA4M9IxQVpXHjviTHrQ2T08FmN4PMUkJrxU3/eM doxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AsV8nXeGOBZSH3zrEUqd9iliNzH/znlE74D2q/iZRbA=; b=DYrvD9XMzEp60n/Sgr5krR/TiXWIuzMKHIK8ev9xTFL6EWnas+6rbZ+pq4CsHj7Qph ggwc81LhgQBUY7pjbJIc2YGpYB4XHYH3wfr1krZT2Tg+LxIN/Nz+qI0+TRvZZrjj7CgE /gFNlfKXJUDEigTz5XkeYtK4kZ28Cu6zd7iigy3N6CIGanHDGo3VmHoYpuXLQkADhi2F oebNR5XDfQxMtMnNZuqVt1USTt59YrD/Lv3hX517w+zWyaUqA2LpubpUdg4PFLIa8n9/ sga3odKa5eXVR0MGQONp/hjrxf3JmAZ6aHO2ikm7UASusNNZbmrAbz9fosWK8b3fRRGZ hinQ== X-Gm-Message-State: AOAM532v9GUHmfguvxeMX3uZgUH9Fdb8oHgAfuDl3B2Vneit7gmC0r2X s5lkeDhVamUxmxFUzdxwO9yLHjL+h+s= X-Google-Smtp-Source: ABdhPJyI4As6fp/k4k7+8FrEN9ZQiZEWwCBdbAoemoFTg47dew3fMqoijIlSKNznVHT8RVMdZ/377Q== X-Received: by 2002:a62:6285:: with SMTP id w127mr27143261pfb.12.1595409449760; Wed, 22 Jul 2020 02:17:29 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Date: Wed, 22 Jul 2020 17:15:26 +0800 Message-Id: <20200722091641.8834-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang gvec should provide vecop_list to avoid: "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index dc333e6a91..433cdacbe1 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, T= CGv_vec a, TCGv_vec b) static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, 0 }; static const GVecGen2s rsub_op[4] =3D { { .fni8 =3D gen_vec_rsub8_i64, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs8, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D gen_vec_rsub16_i64, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs16, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D gen_rsub_i32, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs32, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D gen_rsub_i64, .fniv =3D gen_rsub_vec, .fno =3D gen_helper_vec_rsubs64, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409585; cv=none; d=zohomail.com; s=zohoarc; b=TPnRdU+9z0fEDxDUoGmJURHSD+gaQ9Vfoh0t4mC64gehUSEeZJ/4K0o4fs+nOK4RmnrqA3lC4rxNZPmJq2mAMz6VC/15lRxZCTFH4zGkj1TNCyf+2fS0BjaeQ0WljKz1dh2Ehq6fZxDjzpae9BJTILxoqto/2mcMl2jVT5aAe+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409585; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=dY1VnCufQZpa+aF68DC4K7OikxwvWj2GSrpOqri/zyA=; b=TTz1vJUVJgnoCddDrQgfXWikLVxN+TjByzwDBAbAPeKHfA+waxZxjLmr9LebwWcUMtXsejpWIYCza9jM5U27INSx2brGogDvMsCmpPN2bFvE3bGp9lbVTW1GeFg27LjFIobJFF5RYnFFscpa/3+4EWFdZVWW9FqpXA6jBHgk20g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409585796435.45310928449896; Wed, 22 Jul 2020 02:19:45 -0700 (PDT) Received: from localhost ([::1]:37538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAue-00011a-L6 for importer@patchew.org; Wed, 22 Jul 2020 05:19:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAsb-0005O0-PA for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:37 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:35545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAsa-0005EX-8A for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:37 -0400 Received: by mail-pf1-x436.google.com with SMTP id a14so872691pfi.2 for ; Wed, 22 Jul 2020 02:17:35 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 433cdacbe1..7cd08f0868 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, T= CGv_i64 b) =20 static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_vec_sub8_i64(d, b, a); + tcg_gen_vec_sub16_i64(d, b, a); } =20 static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409727; cv=none; d=zohomail.com; s=zohoarc; b=l9WY9hMeAXf78S/yW+Y6ER9JvMXcpTYLTUO79ZtNLdDVk1fcnW+1q2Y1mzogdnv3pQVZQhNkwbryBG6pBKXrQaoDY9bxed71/KEX4H7R+0B613gHQ5SJZ8toneij4Rj3+4BF++exCeB7xBzSbinOkANT+YB3svyx2OI0gXjHl9g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409727; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=gIClYh77YnToY+rzZTLHItNPlAaqhPTdCd+nqEyek5o=; b=gBFqCfnHDpbgPbdSeFxHQB9eYifPcfIoNxvrkDonSLihR2NEaoxtMAYcmbvVmbALJLMu4O9W+vhQInUcUZNtpk92qzTFUlJdqNzupjpuSwAXingdt0qNVO2Pd4ea55OMxH7VY5cPjCfEVGmFoItqI9tMXaOKuvw7lj0Ob38+fZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159540972703858.34871987512531; Wed, 22 Jul 2020 02:22:07 -0700 (PDT) Received: from localhost ([::1]:48922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAwv-0005pt-Hv for importer@patchew.org; Wed, 22 Jul 2020 05:22:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAsh-0005bK-S4 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:43 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:36935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAsf-0005FL-Qj for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:43 -0400 Received: by mail-pl1-x633.google.com with SMTP id p1so652226pls.4 for ; Wed, 22 Jul 2020 02:17:41 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gIClYh77YnToY+rzZTLHItNPlAaqhPTdCd+nqEyek5o=; b=Kuoq6oHAYiTccKvHPtXDhHZUKOKrbHn2n0pH7zA2OeX8IN8tczUlD2clgSQ4ucKNu9 +y3Mq+egu4ffVF97uKG6HX6/OuYE8fJwdyCkTxrqvgBhyAAKoV7RIuaVG8wiVfr1B+ym Omm8D3QrmCAlMzM/ALc0eYFtyeCYix4w6qC/EtZRMyj27oZw80ecXaN+vS3Ohc0uRFxK iQvK2Ekl70soezxIRZfBwz1PvKoewV+NfhUo7RlOrMdgABCObofEhazKHroTkVTgR7t1 plk91qrK4f98Yhm44Y47DZ7KpxpcA7tAp/lMy61UEcrlsbWWX5W1rlWYiteLjHvxi5JN Q0kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gIClYh77YnToY+rzZTLHItNPlAaqhPTdCd+nqEyek5o=; b=ij4n9qJxlX7WQo25eeDafoFrwDUFW0MKlcX+ocgA2piAl7tMJZhSHOY0CqvRuVbP7k FmsVG3qkrfhy4Jz8EAY0LGjvWbtZHtvHiFu2BaxV3diJHlvyicoTM2X51v/Z7I3I4xaZ Nut8go9PehzVBZSSl3uRvpRxwe8/CJCIDT5/bhAWXB80YsE+V5kUcItF2dL5jDeuibtF 6kiFVEDQ3Ius2NIZlvAmyY1Hzleepwz2EoKDWs3bYt379LbdtuWgl713y32b6quMio3z eZWSWinOcXMWs/SoJ+NA5I54qQYQuxrNv2v+AO3iiyxlHsamAfyX89+6ysWcb/Iqmvt9 EhLQ== X-Gm-Message-State: AOAM532zy+0/scg+RVVQuYtTtpBcPaN3FC/RjIjgkAqT6bn1B13tO8dZ Ouhz9irrXCreu1hDYv2jGLdRC3n3mc0= X-Google-Smtp-Source: ABdhPJwzRRM2hFSuka3tv+LFfhOOWLxIoRmM+1tg+X4AzcR62Hguu+QU0XMPs8q/law6HhKtV1BMoA== X-Received: by 2002:a17:90a:2dcb:: with SMTP id q11mr9122542pjm.135.1595409460417; Wed, 22 Jul 2020 02:17:40 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() Date: Wed, 22 Jul 2020 17:15:28 +0800 Message-Id: <20200722091641.8834-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x633.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang do_opivx_widen() should return false if check function returns false. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 7cd08f0868..c0b7375927 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1151,7 +1151,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr = *a, if (opivx_widen_check(s, a)) { return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); } - return true; + return false; } =20 #define GEN_OPIVX_WIDEN_TRANS(NAME) \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409690; cv=none; d=zohomail.com; s=zohoarc; b=ll2UOvlvemV/pyg5g/UsisiqCKdQqqYxd0qywogzUd86Nfw4m1engS6CxD+N7QdyOWMaOlCNtHBmUejbsD0zQx+cTQYtV6QLSqfapdjx8QXVgEDHmIrNqJE0rnjv1X1pMIWPA9N5+IvuheMsjJhNc2EXIOz6MCXINwvhVnQtrnQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409690; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=ty5URjUyAzHgdvndBCovXPI97TuuSa9GCoER6PMKuQs=; b=AZYXfM/8rrvAPLGCLWmv6Z5x264xDsH4FHYbQ8FQRTDbe3P5u+QOw5GTDEAEjIzC3d+IM8SripN2+4GHa+WAimGNdzo60Lk2UT9+noUhiGVUzxoE5EOwduR/8l9nZvc9ttglY1aZVf9XUv/geX1QgPSRToGE5PkEuHBMxkKDKLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409690151237.89800886095054; Wed, 22 Jul 2020 02:21:30 -0700 (PDT) Received: from localhost ([::1]:46200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAwK-0004hx-SX for importer@patchew.org; Wed, 22 Jul 2020 05:21:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAsv-00065z-Qh for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:57 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:45225) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAst-0005G5-7f for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:17:57 -0400 Received: by mail-pg1-x533.google.com with SMTP id l63so857202pge.12 for ; Wed, 22 Jul 2020 02:17:54 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang vill bit is at vtype[XLEN-1]. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 378f6e82bf..27ce075e50 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { target_ulong gpr[32]; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409546; cv=none; d=zohomail.com; s=zohoarc; b=FSBho26EzYjxBsI/sJD1cBZ2+ry9qYNwD5uihqlsWea8bV6Qz4eiCwgBQhBm91eReH6FyZX3GeT+LxKlut3xjn3ryI6Fj/M/1rXdYs9Q5BjQ2zwEfUTY9ql8zHS8Jc3yIatGTibtKttpXiYFXhxapdVcPZUWJ2TkGQxBhrbiXV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409546; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=X1LjG6RnJFzOwqupbNN0fmDaBqQS4kt6NiMvgH0v9Do=; b=A6OgEiWT7aP5diIF3nEM8jnbw+cw8EZibibxvGBCPIOSbzawBPZWS653rIqGycYMjx91Y2ujLPdgEpP8IjPYpW2ITIoL0TPGfHQHz2t19S1ID8RMG64AUTam+Z0EpF3+fn/5BT+h75dehaIEI1ZIVoX8b/t4bY/yzMYb2xyd1Rc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409546042637.5075431146653; Wed, 22 Jul 2020 02:19:06 -0700 (PDT) Received: from localhost ([::1]:34248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAu0-00084x-Pm for importer@patchew.org; Wed, 22 Jul 2020 05:19:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAt0-0006H9-Pl for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:02 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:35894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAsy-0005Gb-6W for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:02 -0400 Received: by mail-pf1-x441.google.com with SMTP id 207so872017pfu.3 for ; Wed, 22 Jul 2020 02:17:59 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:17:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X1LjG6RnJFzOwqupbNN0fmDaBqQS4kt6NiMvgH0v9Do=; b=AsemGna+W0Blh3cqN058BH2n1LSs+uk/6prjWLWNB6knKdgwWv5/iVL0utXJMUZBa5 9Q7DYpptA9tnQMTzjtKqBrv3t6f44nozJzC871JOaHhmlrIfeGYlw1Xg9JHUlcdRmxXS UjmqTuX9N2uGGZf1xgeQJVRDc8+wnJCK9L5EDbp6ktqh4o0IsYAez9grhHlbkR4vC4A6 TztujTiqOVmC2OHfxRXPcuxSRHSjmybVBh7oXyAhWtylzWSEu5ux0dJSQdy4R1b50nxd INedkWUH9MiOPfNZipDBVGZploPCYTQd8YS23SwfQUMmxjc58JC46lLfm+QgVL8G2T1L 7NcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X1LjG6RnJFzOwqupbNN0fmDaBqQS4kt6NiMvgH0v9Do=; b=iZEKNb50jx9Va5G/r3HZ0G7UpXTmOWl71k6KeRiJnzBqvrzOFFynAQH8zHsIgq7rk1 IgcB/rQBlA/OgGiiKgu5Wo4UmYy81q26cGNjdYMFQt3PDYY45hjQc87J+7TMSZIchA55 gtIUNWn+c53/9vdgIwTrEjaAJNVyVXPgg9MabopCfT6Di7N7JBLjPfN8mUj/C22PI/Ur tu4Z65zBJNgm7ff+wgdJwd4tgOTTtBVF1j6jSCO45iQanOrvP/X2PMYCcNPWU3S21QbL vsc303Hp/z78Gd9dXmcA7L40QGwHsB/uhhJE4P+qMJ1kzWftQo9S3z67vzmD0h0r5Ypq D9YQ== X-Gm-Message-State: AOAM531Ba9yUIXqd0xVrjPm0kGF2hbf8XHZpIGsbn8zwu+jl5hjgKDZK xxs89q8ueN9PwcDtNnevbjjjH4uFUkU= X-Google-Smtp-Source: ABdhPJyq3lYX4I+k9jL/m85IDJag6nyaAaEwIpP+yBJ7j90p2xPOgu8VXKehVN1lTRv/PKdpZqYJTA== X-Received: by 2002:a62:3587:: with SMTP id c129mr28124312pfa.212.1595409478746; Wed, 22 Jul 2020 02:17:58 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field Date: Wed, 22 Jul 2020 17:15:30 +0800 Message-Id: <20200722091641.8834-8-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39f44d1029..4c0a6198e7 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc) =20 static uint32_t vext_wd(uint32_t desc) { - return (simd_data(desc) >> 11) & 0x1; + return FIELD_EX32(simd_data(desc), VDATA, WD); } =20 /* --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409645; cv=none; d=zohomail.com; s=zohoarc; b=ZbEzWhS6WoR1SU8AYpqF3ORsYctJ8UE0KHe0O6OmSq7BYCiBLJDHK7sJv12nh1B3m+8Mu2ZenULtuzwkH9jNlh1OIZQ34fWju4hOrw8zo8bmjzI1j/RyFHPVXezTi7Epvfi2paveraTkz5xBGhJr8np8CQ6CKfQ0eG2e0MMO18M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409645; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=4RSHo1DiLZAg7Ka4Kyeh2i0LvOj8ItQyeMAy6eC+/XE=; b=Ewz7vq6dQrUMhLF22pmATYwWcQqYA7KviNrKEJOq10q5U83e7PLkP2EHIaLsotWw8+MA5Dfnu1y2yjySidysZly8Lo5dOA3Ch/FDKe/ika1CUUhWvQNeo1/LOOvcGY+rO8oGUJHkYuadknXyLcqYJBKrNydYbC9H3TKdJdM4crU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409645352208.5067777438502; Wed, 22 Jul 2020 02:20:45 -0700 (PDT) Received: from localhost ([::1]:41878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAvc-0002pm-3g for importer@patchew.org; Wed, 22 Jul 2020 05:20:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAt6-0006WC-4k for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:08 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44243) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAt3-0005HC-O8 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:07 -0400 Received: by mail-pf1-x444.google.com with SMTP id t11so851334pfq.11 for ; Wed, 22 Jul 2020 02:18:05 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:18:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4RSHo1DiLZAg7Ka4Kyeh2i0LvOj8ItQyeMAy6eC+/XE=; b=MLSEMcZKGjKiMuJ77WvWs5zu/2YMGOSwPlKks7yPMIMOfec64oYKCXg0iRQJTMbqDd g6/EVcVXZoJOHKSge9tPOpQnLYGXiZMopc65lKjXNQYyF8KbmELTBltKotCu0Rgqo8hM GPeFsZJ2IffTk1xaMmhi3WCBNscTZ4X2dpycGqLGC7piDS0tvXm9sCYi7ncGuSq5uCCq w33xoniImmaay9g/8MVvqkFjcPNYPOs/J7attMlHHYBDzdABquFF/EVB9G7HjCtkAAE/ VU0h3NhNkBmiaM2K3WeS2B54HAoorcGzdJuagzBh/wV7vIGJ+4Xq8CbZiOUpJ0mJ5jpB 8nHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4RSHo1DiLZAg7Ka4Kyeh2i0LvOj8ItQyeMAy6eC+/XE=; b=NeHRYJMLdKyEhktbt8uAbODMIUpvL19XZWx2ZUgWAIopZ0U4I2L1z9si393lFo39hB sbR2LErjYzpxWxOXIAsUwqeVlu8txNDU/01vlnaf4VhRn6JOsuNo8usFZPuPRrCTSyE1 EXj7ZTCWabNaxCNhEkauLTM76qbOGmgfWcDHP2KGHTMEkX2+H5xz1Xk4wWAAgD6IuXn/ wPk2dBylaDukuNhPbtBYohZxhoj8UvCRN1ZjPa5sC/eDGTifE/Hu+TIpd5EeHS1d12H7 VDLpORnUn+xtRB5HWi+lh74aQ8C94ehUUOJhkGH8yR4XFm32pbaA30pUIzmr7PXy5/vj /ATg== X-Gm-Message-State: AOAM5318stK60rRuj7qDcLP7iYuwEp09SvduOBUVzA+uB3BpWVdNwaQe 8UydB/0yGyoN6gq+mQqT5HBiDeN8oZQ= X-Google-Smtp-Source: ABdhPJxz0UwWQTQ0cxTneNr3SiWmJK/Xu74/uqhGDgCez09AbL3e2BXkCK1zlLl7Rz+kqR3q8vE3UA== X-Received: by 2002:a62:164a:: with SMTP id 71mr28808187pfw.266.1595409484159; Wed, 22 Jul 2020 02:18:04 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field Date: Wed, 22 Jul 2020 17:15:31 +0800 Message-Id: <20200722091641.8834-9-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 6 ++++++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 +++++++++++++++- target/riscv/csr.c | 25 ++++++++++++++++++++++++- 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 27ce075e50..0a175151da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -317,6 +317,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArr= ay *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); @@ -360,6 +361,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ul= ong); =20 #define TB_FLAGS_MMU_MASK 3 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; @@ -410,11 +412,15 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, =20 #ifdef CONFIG_USER_ONLY flags |=3D TB_FLAGS_MSTATUS_FS; + flags |=3D TB_FLAGS_MSTATUS_VS; #else flags |=3D cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { flags |=3D env->mstatus & MSTATUS_FS; } + if (riscv_cpu_vector_enabled(env)) { + flags |=3D env->mstatus & MSTATUS_VS; + } #endif *pflags =3D flags; } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b5a7..a8b3120883 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -367,6 +367,7 @@ #define MSTATUS_SPIE 0x00000020 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..3fae736529 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -108,10 +108,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | + MSTATUS_VS; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ac01c835e1..fb21c87488 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) return -1; } env->mstatus |=3D MSTATUS_FS; + env->mstatus |=3D MSTATUS_VS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; if (vs(env, csrno) >=3D 0) { @@ -210,6 +211,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, ta= rget_ulong *val) =20 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxrm =3D val; return 0; } @@ -222,6 +230,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxsat =3D val; return 0; } @@ -234,6 +249,13 @@ static int read_vstart(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vstart =3D val; return 0; } @@ -400,7 +422,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; #if defined(TARGET_RISCV64) /* * RV32: MPV and MTL are not in mstatus. The current plan is to @@ -412,6 +434,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mstatus =3D (mstatus & ~mask) | (val & mask); =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | + ((mstatus & MSTATUS_VS) =3D=3D MSTATUS_VS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409660; cv=none; d=zohomail.com; s=zohoarc; b=MFuVeTttZy6L+mYw/yCQ+LhYN+3l8YGxfbQGepieG0J94RLnOyb3d27bZXfCjCJCFYPUx2l5jPj/bGLNVz5KQhYZcp8DBc+UXxPTobSTeYx1RCmdxmGcUUrGJa8cW9Uj8Hy/5rqCi9I1yaNLBd6qeY14ORBJeBdP6y+YQfGDiKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409660; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=/qLsSnqF0o8+PHvgbRszILIBQb0kzGW6bHTY2HlnYvg=; b=Y/mowMbA346/C72Yn7kaiFEQllFBfjh8AFKi+jw9m/5+NeQaYGU8z/4iadWrDsLlqIaOWrWLbQBExwdIfYmgOfJa5DZB5cnLKAcLHCT84zIlIkG6rWQUX4pckRWUAbmfVE4KvIG3L0ehnYAWXnZQ6kVsiOvImAJMg/fwcjigzCY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409660906834.6706931221389; Wed, 22 Jul 2020 02:21:00 -0700 (PDT) Received: from localhost ([::1]:43376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAvr-0003Sn-JQ for importer@patchew.org; Wed, 22 Jul 2020 05:20:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAt9-0006g5-R5 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:11 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:35537) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAt8-0005Hr-5d for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:11 -0400 Received: by mail-pf1-x42b.google.com with SMTP id a14so873408pfi.2 for ; Wed, 22 Jul 2020 02:18:09 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a8b3120883..5b0be0bb88 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -422,6 +422,7 @@ #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fb21c87488..ab4a4fc132 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -365,7 +365,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MI= P_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409750; cv=none; d=zohomail.com; s=zohoarc; b=lVxs0V6kz6g18EErrncIE+PyrUo3tAj7NVfRPOcZbgmA6KaIEb3yN0VSl1DCSLZpEuNB4O9JvwYBlIPIPWhCWe3Xz5myDzSZVmYkautIxBxoeW/gRJ8N45qRZZ8rsajPttSO2deuwUcAtFhM/h9eSesnV/PkPK0LBqyU+cJoP74= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409750; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=VjKocre13t4DBkTwq5bqz9F+KcVss4J+LmWeQSFgDb4=; b=i7FZ/U9KeEKqX2qrSLj4oLgzViMAVkxqZQrzPz/qHjAtJNl97w2nI7gOLWQifzT74eRmV3gHc+6RNFm21dTHXMJ1Vp/BAUBZYR/g3FjN0kSQ+7cEWs60MMo83+dvddBe5hLLzHEGjcQXPYfGEmpqV8rtNLb1LnbJ0Y0AcE92u0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159540975092517.437356094709912; Wed, 22 Jul 2020 02:22:30 -0700 (PDT) Received: from localhost ([::1]:51208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyAxJ-0006mA-D8 for importer@patchew.org; Wed, 22 Jul 2020 05:22:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAtG-0006xm-Aj for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:18 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:36272) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAtD-0005J7-GI for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:18 -0400 Received: by mail-pl1-x636.google.com with SMTP id t6so656683plo.3 for ; Wed, 22 Jul 2020 02:18:15 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 69 ++++++++++++++++++++----- target/riscv/translate.c | 33 ++++++++++++ 2 files changed, 90 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index c0b7375927..e537e80550 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -48,6 +48,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) tcg_temp_free(s1); tcg_temp_free(s2); tcg_temp_free(dst); + mark_vs_dirty(ctx); return true; } =20 @@ -78,6 +79,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli = *a) tcg_temp_free(s1); tcg_temp_free(s2); tcg_temp_free(dst); + mark_vs_dirty(ctx); return true; } =20 @@ -163,7 +165,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCG= v, TCGv_env, TCGv_i32); =20 static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) + gen_helper_ldst_us *fn, DisasContext *s, + bool is_store) { TCGv_ptr dest, mask; TCGv base; @@ -195,6 +198,9 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, tcg_temp_free_ptr(mask); tcg_temp_free(base); tcg_temp_free_i32(desc); + if (!is_store) { + mark_vs_dirty(s); + } gen_set_label(over); return true; } @@ -245,7 +251,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) @@ -298,7 +304,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 static bool st_us_check(DisasContext *s, arg_r2nfvm* a) @@ -321,7 +327,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr,= TCGv, =20 static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask; TCGv base, stride; @@ -348,6 +354,9 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, tcg_temp_free(base); tcg_temp_free(stride); tcg_temp_free_i32(desc); + if (!is_store) { + mark_vs_dirty(s); + } gen_set_label(over); return true; } @@ -382,7 +391,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) @@ -426,7 +435,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) return false; } =20 - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } =20 static bool st_stride_check(DisasContext *s, arg_rnfvm* a) @@ -449,7 +458,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, = TCGv, =20 static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask, index; TCGv base; @@ -476,6 +485,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, tcg_temp_free_ptr(index); tcg_temp_free(base); tcg_temp_free_i32(desc); + if (!is_store) { + mark_vs_dirty(s); + } gen_set_label(over); return true; } @@ -510,7 +522,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 static bool ld_index_check(DisasContext *s, arg_rnfvm* a) @@ -554,7 +566,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } =20 static bool st_index_check(DisasContext *s, arg_rnfvm* a) @@ -598,6 +610,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint3= 2_t data, tcg_temp_free_ptr(mask); tcg_temp_free(base); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -677,6 +690,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32= _t vs2, tcg_temp_free_ptr(index); tcg_temp_free(base); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -823,6 +837,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn = *gvec_fn, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fn); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -877,6 +892,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, tcg_temp_free_ptr(src2); tcg_temp_free(src1); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -911,6 +927,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn= *gvec_fn, =20 tcg_temp_free_i64(src1); tcg_temp_free(tmp); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1024,6 +1041,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, tcg_temp_free_ptr(src2); tcg_temp_free(src1); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1047,10 +1065,10 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen= 2iFn *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); } - } else { - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + mark_vs_dirty(s); + return true; } - return true; + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); } =20 /* OPIVI with GVEC IR */ @@ -1111,6 +1129,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1198,6 +1217,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1276,6 +1296,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1407,6 +1428,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, =20 tcg_temp_free_i32(src1); tcg_temp_free(tmp); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1465,6 +1487,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1648,6 +1671,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) cpu_env, 0, s->vlen / 8, data, fns[s->sew]); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -1690,6 +1714,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) } =20 tcg_temp_free(s1); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1705,6 +1730,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); + mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -1726,6 +1752,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) tcg_temp_free_ptr(dest); tcg_temp_free_i32(desc); tcg_temp_free_i64(s1); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -1830,6 +1857,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1865,6 +1893,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1942,6 +1971,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2016,6 +2046,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2130,6 +2161,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2202,6 +2234,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2221,6 +2254,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) =20 tcg_temp_free_ptr(dest); tcg_temp_free_i32(desc); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -2270,6 +2304,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2318,6 +2353,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2380,6 +2416,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2477,6 +2514,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, 0, s->vlen / 8, data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2508,6 +2546,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2533,6 +2572,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) }; tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2708,6 +2748,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); done: gen_set_label(over); return true; @@ -2758,6 +2799,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) } vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2824,6 +2866,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); tcg_temp_free_i64(dest); + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] =3D { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2850,6 +2893,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) endian_ofs(s, a->rs2, a->rs1), MAXSZ(s), MAXSZ(s)); } + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] =3D { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2886,6 +2930,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..02b4204584 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -47,6 +47,7 @@ typedef struct DisasContext { bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; + uint32_t mstatus_vs; uint32_t misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, @@ -416,6 +417,37 @@ static void mark_fs_dirty(DisasContext *ctx) static inline void mark_fs_dirty(DisasContext *ctx) { } #endif =20 +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_vs are: + * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_vs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_vs =3D=3D MSTATUS_VS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_vs =3D MSTATUS_VS; + + tmp =3D tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } + tcg_temp_free(tmp); +} +#else +static inline void mark_vs_dirty(DisasContext *ctx) { } +#endif + #if !defined(TARGET_RISCV64) static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) @@ -764,6 +796,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->pc_succ_insn =3D ctx->base.pc_first; ctx->mem_idx =3D tb_flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; + ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab4a4fc132..33c77be06e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -166,10 +166,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong *val) #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); - if (vs(env, csrno) >=3D 0) { - *val |=3D (env->vxrm << FSR_VXRM_SHIFT) - | (env->vxsat << FSR_VXSAT_SHIFT); - } return 0; } =20 @@ -183,10 +179,6 @@ static int write_fcsr(CPURISCVState *env, int csrno, t= arget_ulong val) env->mstatus |=3D MSTATUS_VS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; - if (vs(env, csrno) >=3D 0) { - env->vxrm =3D (val & FSR_VXRM) >> FSR_VXRM_SHIFT; - env->vxsat =3D (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; - } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); return 0; } --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409938; cv=none; d=zohomail.com; s=zohoarc; b=AC34rhGtJxCEaqxYMeSnyn4Lha/RU5VlujHZmnQLiap/NwvOZGpKjBSNSS9v4fl+Rf/SnlctpvnVndlnN0P12pcucqW3ls081YtU1s+DqfN+UELnlNMkCLX/oyhnJDmX5jq4WSJclUq69n7kbw2qUAxLGhYXU5PkxMABEWFPs0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409938; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=0BTSvnm6ouC9jlpI1w689nf30Q81rAaMwIj+C2UZaE0=; b=JTrugrBOv7mf5igqUZ70PHlULTWAImEued8R0G/8e3Ukbmg5o8oxlWRawgUKNxQ5UYhrbXSh7r1I4qvokZ0+itW25NgjsJbVVR3wS5QM5CpQEgV/W4PWYaK5OFCNydZMhW5qHo2GwwAJFo8bqb8TdmcsHAlkhdhpjXHEsUAqR/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409938759144.4785809845214; Wed, 22 Jul 2020 02:25:38 -0700 (PDT) Received: from localhost ([::1]:38376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB0L-0004Y1-Cv for importer@patchew.org; Wed, 22 Jul 2020 05:25:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAtM-0007Cj-9z for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:24 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:40585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAtK-0005M0-Gs for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:23 -0400 Received: by mail-pf1-x436.google.com with SMTP id u5so858682pfn.7 for ; Wed, 22 Jul 2020 02:18:22 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 7 +++++++ target/riscv/csr.c | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5b0be0bb88..7afdd4814b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -60,9 +60,16 @@ #define CSR_VSTART 0x008 #define CSR_VXSAT 0x009 #define CSR_VXRM 0x00a +#define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 =20 +/* VCSR fields */ +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 33c77be06e..e05acb5a24 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -252,6 +252,26 @@ static int write_vstart(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SH= IFT); + return 0; +} + +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -1; + } + env->mstatus |=3D MSTATUS_VS; +#endif + + env->vxrm =3D (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; + env->vxsat =3D (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; + return 0; +} + /* User Timers and Counters */ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1270,6 +1290,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_VSTART] =3D { vs, read_vstart, write_vstart = }, [CSR_VXSAT] =3D { vs, read_vxsat, write_vxsat = }, [CSR_VXRM] =3D { vs, read_vxrm, write_vxrm = }, + [CSR_VCSR] =3D { vs, read_vcsr, write_vcsr = }, [CSR_VL] =3D { vs, read_vl = }, [CSR_VTYPE] =3D { vs, read_vtype = }, /* User Timers and Counters */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Greentime Hu , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7afdd4814b..fe055b67a6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -63,6 +63,7 @@ #define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 =20 /* VCSR fields */ #define VCSR_VXSAT_SHIFT 0 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e05acb5a24..cdf6198d8c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -189,6 +189,12 @@ static int read_vtype(CPURISCVState *env, int csrno, t= arget_ulong *val) return 0; } =20 +static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env_archcpu(env)->cfg.vlen >> 3; + return 0; +} + static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->vl; @@ -1293,6 +1299,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_VCSR] =3D { vs, read_vcsr, write_vcsr = }, [CSR_VL] =3D { vs, read_vl = }, [CSR_VTYPE] =3D { vs, read_vtype = }, + [CSR_VLENB] =3D { vs, read_vlenb = }, /* User Timers and Counters */ [CSR_CYCLE] =3D { ctr, read_instret = }, [CSR_INSTRET] =3D { ctr, read_instret = }, --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409997; cv=none; d=zohomail.com; s=zohoarc; b=R8fw/Ao++pWPUPbfCCBhZ6tahtE2mdIPEAoz6bpV4xjccH+059b4JByIx9rOrTW9PUtUgWtxJHUWxHnylJ8u9B4YX5mLjuRnx4c0J52MMTGOJhuVjx3uZ9qooF8UsfmoDZkZOaTXQ0Qs+Vj4buamoRaQAZRSNQv399AscSDqdJI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595409997; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=O9BHeyw/KcfOUKtWV0vEH1ZZlHc2MThjrfyUSGoDRM4=; b=EZmHz4kmXuwnX9HNsiJ84GGunla0XDU6P8y5ODveX+N2U2jXh+p3rPFA5FQZ0P0q7SKstoRfOMtd0SdAOHTRLcbbpHCn+onFhM/T2BNS2YKfg3BuV5LukFIFCgbvyL2E/9oQ2ImVxdjqDRMPyHUuC6toJIwdxizIijgX0OdYLPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595409997169352.31721918827225; Wed, 22 Jul 2020 02:26:37 -0700 (PDT) Received: from localhost ([::1]:41814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB1H-00060F-OU for importer@patchew.org; Wed, 22 Jul 2020 05:26:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAta-0007oe-8x for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:38 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:35046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAtU-0005RX-NC for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:18:37 -0400 Received: by mail-pj1-x1042.google.com with SMTP id f16so874583pjt.0 for ; Wed, 22 Jul 2020 02:18:32 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 35 +--- target/riscv/internals.h | 9 +- target/riscv/translate.c | 2 - target/riscv/vector_helper.c | 250 ++++++++++-------------- 4 files changed, 110 insertions(+), 186 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index e537e80550..018a134599 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -247,7 +247,6 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -300,7 +299,6 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -387,7 +385,6 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -426,7 +423,6 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) gen_helper_vsse_v_w, gen_helper_vsse_v_d } }; =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -518,7 +514,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -562,7 +557,6 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -641,7 +635,6 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uin= t8_t seq) return false; } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); @@ -751,7 +744,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) } } =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, WD, a->wd); @@ -830,7 +822,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn = *gvec_fn, } else { uint32_t data =3D 0; =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -876,7 +867,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, src1 =3D tcg_temp_new(); gen_get_gpr(src1, rs1); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); @@ -1025,7 +1015,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, } else { src1 =3D tcg_const_tl(sextract64(imm, 0, 5)); } - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); @@ -1121,7 +1110,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -1210,7 +1198,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -1289,7 +1276,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1480,7 +1466,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1850,7 +1835,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1923,7 +1907,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_d, \ }; \ gen_set_rm(s, 7); \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -1964,7 +1947,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2002,7 +1984,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ gen_set_rm(s, 7); \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2039,7 +2020,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2075,7 +2055,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ gen_set_rm(s, 7); \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2155,7 +2134,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2298,7 +2276,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2347,7 +2324,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2410,7 +2386,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ @@ -2440,7 +2415,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) TCGv dst; TCGv_i32 desc; uint32_t data =3D 0; - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); =20 @@ -2472,7 +2446,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) TCGv dst; TCGv_i32 desc; uint32_t data =3D 0; - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); =20 @@ -2508,7 +2481,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ @@ -2536,7 +2508,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_3_ptr * const fns[4] =3D { @@ -2563,7 +2534,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_2_ptr * const fns[4] =3D { @@ -2854,7 +2824,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) } =20 if (a->vm && s->vl_eq_vlmax) { - int vlmax =3D s->vlen / s->mlen; + int vlmax =3D s->vlen; TCGv_i64 dest =3D tcg_temp_new_i64(); =20 if (a->rs1 =3D=3D 0) { @@ -2885,7 +2855,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) } =20 if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >=3D s->vlen / s->mlen) { + if (a->rs1 >=3D s->vlen) { tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); } else { @@ -2925,7 +2895,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 37d33820ad..89fc0753bc 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -22,11 +22,10 @@ #include "hw/registerfields.h" =20 /* share data between vector helpers and decode code */ -FIELD(VDATA, MLEN, 0, 8) -FIELD(VDATA, VM, 8, 1) -FIELD(VDATA, LMUL, 9, 2) -FIELD(VDATA, NF, 11, 4) -FIELD(VDATA, WD, 11, 1) +FIELD(VDATA, VM, 0, 1) +FIELD(VDATA, LMUL, 1, 3) +FIELD(VDATA, NF, 4, 4) +FIELD(VDATA, WD, 4, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 02b4204584..7593b41a1f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -62,7 +62,6 @@ typedef struct DisasContext { uint8_t lmul; uint8_t sew; uint16_t vlen; - uint16_t mlen; bool vl_eq_vlmax; } DisasContext; =20 @@ -824,7 +823,6 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); - ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4c0a6198e7..6545f91732 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -81,11 +81,6 @@ static inline uint32_t vext_nf(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, NF); } =20 -static inline uint32_t vext_mlen(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, MLEN); -} - static inline uint32_t vext_vm(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, VM); @@ -188,19 +183,24 @@ static void clearq(void *vd, uint32_t idx, uint32_t c= nt, uint32_t tot) vext_clear(cur, cnt, tot); } =20 -static inline void vext_set_elem_mask(void *v0, int mlen, int index, +static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { - int idx =3D (index * mlen) / 64; - int pos =3D (index * mlen) % 64; + int idx =3D index / 64; + int pos =3D index % 64; uint64_t old =3D ((uint64_t *)v0)[idx]; - ((uint64_t *)v0)[idx] =3D deposit64(old, pos, mlen, value); + ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 -static inline int vext_elem_mask(void *v0, int mlen, int index) +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=3D1. + * (Section 4.6) + */ +static inline int vext_elem_mask(void *v0, int index) { - int idx =3D (index * mlen) / 64; - int pos =3D (index * mlen) % 64; + int idx =3D index / 64; + int pos =3D index % 64; return (((uint64_t *)v0)[idx] >> pos) & 1; } =20 @@ -277,12 +277,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong bas= e, { uint32_t i, k; uint32_t nf =3D vext_nf(desc); - uint32_t mlen =3D vext_mlen(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; =20 /* probe every access*/ for (i =3D 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, base + stride * i, nf * msz, ra, access_type); @@ -290,7 +289,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, /* do real access */ for (i =3D 0; i < env->vl; i++) { k =3D 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -506,12 +505,11 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); - uint32_t mlen =3D vext_mlen(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; =20 /* probe every access*/ for (i =3D 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, @@ -520,7 +518,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, /* load bytes from guest memory */ for (i =3D 0; i < env->vl; i++) { k =3D 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -604,7 +602,6 @@ vext_ldff(void *vd, void *v0, target_ulong base, { void *host; uint32_t i, k, vl =3D 0; - uint32_t mlen =3D vext_mlen(desc); uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; @@ -612,7 +609,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, =20 /* probe every access*/ for (i =3D 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } addr =3D base + nf * i * msz; @@ -653,7 +650,7 @@ ProbeSuccess: } for (i =3D 0; i < env->vl; i++) { k =3D 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -784,18 +781,17 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong b= ase, target_long addr; uint32_t wd =3D vext_wd(desc); uint32_t vm =3D vext_vm(desc); - uint32_t mlen =3D vext_mlen(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; =20 for (i =3D 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_L= OAD); probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_S= TORE); } for (i =3D 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } addr =3D get_index_addr(base, i, vs2); @@ -911,13 +907,12 @@ static void do_vext_vv(void *vd, void *v0, void *vs1,= void *vs2, opivv2_fn *fn, clear_fn *clearfn) { uint32_t vlmax =3D vext_maxsz(desc) / esz; - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; uint32_t i; =20 for (i =3D 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i); @@ -976,13 +971,12 @@ static void do_vext_vx(void *vd, void *v0, target_lon= g s1, void *vs2, opivx2_fn fn, clear_fn *clearfn) { uint32_t vlmax =3D vext_maxsz(desc) / esz; - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; uint32_t i; =20 for (i =3D 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i); @@ -1172,7 +1166,6 @@ GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ @@ -1181,7 +1174,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ for (i =3D 0; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - uint8_t carry =3D vext_elem_mask(v0, mlen, i); \ + uint8_t carry =3D vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, s1, carry); \ } \ @@ -1202,7 +1195,6 @@ GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, = clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t vlmax =3D vext_maxsz(desc) / esz; = \ @@ -1210,7 +1202,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ \ for (i =3D 0; i < vl; i++) { = \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); = \ - uint8_t carry =3D vext_elem_mask(v0, mlen, i); = \ + uint8_t carry =3D vext_elem_mask(v0, i); = \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, (ETYPE)(target_long)s1, carry)= ;\ } \ @@ -1235,7 +1227,6 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, = clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ @@ -1243,12 +1234,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ for (i =3D 0; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - uint8_t carry =3D vext_elem_mask(v0, mlen, i); \ + uint8_t carry =3D vext_elem_mask(v0, i); \ \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\ + vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -1266,20 +1257,19 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MS= BC) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - uint8_t carry =3D vext_elem_mask(v0, mlen, i); \ + uint8_t carry =3D vext_elem_mask(v0, i); \ \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -1353,7 +1343,6 @@ GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(TS1); = \ @@ -1361,7 +1350,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS1 s1 =3D *((TS1 *)vs1 + HS1(i)); = \ @@ -1391,7 +1380,6 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H= 8, DO_SRL, 0x3f, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(TD); \ @@ -1399,7 +1387,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ @@ -1448,7 +1436,6 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H= 8, DO_SRL, 0x3f, clearl) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ @@ -1457,13 +1444,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ for (i =3D 0; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -1501,7 +1488,6 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ @@ -1509,14 +1495,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -2078,14 +2064,13 @@ GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ - ETYPE *vt =3D (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \ + ETYPE *vt =3D (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) =3D *(vt + H(i)); \ } \ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ @@ -2100,7 +2085,6 @@ GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ @@ -2108,7 +2092,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - ETYPE d =3D (!vext_elem_mask(v0, mlen, i) ? s2 : \ + ETYPE d =3D (!vext_elem_mask(v0, i) ? s2 : \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) =3D d; \ } \ @@ -2146,11 +2130,11 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, = \ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn) { for (uint32_t i =3D 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i, env, vxrm); @@ -2164,26 +2148,25 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *v= s2, opivv2_rm_fn *fn, clear_fn *clearfn) { uint32_t vlmax =3D vext_maxsz(desc) / esz; - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; =20 switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } =20 @@ -2266,11 +2249,11 @@ do_##NAME(void *vd, target_long s1, void *vs2, int = i, \ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn) { for (uint32_t i =3D 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i, env, vxrm); @@ -2284,26 +2267,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, vo= id *vs2, opivx2_rm_fn *fn, clear_fn *clearfn) { uint32_t vlmax =3D vext_maxsz(desc) / esz; - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; =20 switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } =20 @@ -3188,13 +3170,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t desc) \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ @@ -3223,13 +3204,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t desc) \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ @@ -3794,7 +3774,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ @@ -3803,7 +3782,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ return; \ } \ for (i =3D 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ @@ -3935,7 +3914,6 @@ GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ @@ -3944,14 +3922,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ for (i =3D 0; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, s1, &env->fp_status)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -3969,7 +3947,6 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64= _eq_quiet) void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ @@ -3977,14 +3954,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = void *vs2, \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -4117,13 +4094,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i); \ @@ -4200,7 +4176,6 @@ GEN_VEXT_V(vfclass_v_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ @@ -4210,7 +4185,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ *((ETYPE *)vd + H(i)) \ - =3D (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \ + =3D (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } @@ -4341,7 +4316,6 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ @@ -4350,7 +4324,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ \ for (i =3D 0; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 =3D OP(s1, (TD)s2); \ @@ -4424,7 +4398,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ @@ -4433,7 +4406,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ \ for (i =3D 0; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 =3D OP(s1, (TD)s2, &env->fp_status); \ @@ -4462,7 +4435,6 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, = H8, float64_minnum, clearq) void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; uint32_t i; @@ -4471,7 +4443,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void = *vs1, =20 for (i =3D 0; i < vl; i++) { uint16_t s2 =3D *((uint16_t *)vs2 + H2(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 =3D float32_add(s1, float16_to_float32(s2, true, &env->fp_statu= s), @@ -4484,7 +4456,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void = *vs1, void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; uint32_t i; @@ -4493,7 +4464,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void = *vs1, =20 for (i =3D 0; i < vl; i++) { uint32_t s2 =3D *((uint32_t *)vs2 + H4(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 =3D float64_add(s1, float32_to_float64(s2, &env->fp_status), @@ -4512,19 +4483,18 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; \ uint32_t vl =3D env->vl; \ uint32_t i; \ int a, b; \ \ for (i =3D 0; i < vl; i++) { \ - a =3D vext_elem_mask(vs1, mlen, i); \ - b =3D vext_elem_mask(vs2, mlen, i); \ - vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ + a =3D vext_elem_mask(vs1, i); \ + b =3D vext_elem_mask(vs2, i); \ + vext_set_elem_mask(vd, i, OP(b, a)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } =20 @@ -4548,14 +4518,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, = CPURISCVState *env, uint32_t desc) { target_ulong cnt =3D 0; - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; int i; =20 for (i =3D 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { cnt++; } } @@ -4567,14 +4536,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, = CPURISCVState *env, target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen =3D vext_mlen(desc); uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; int i; =20 for (i =3D 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { return i; } } @@ -4591,39 +4559,38 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t mlen =3D vext_mlen(desc); - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; int i; bool first_mask_bit =3D false; =20 for (i =3D 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } /* write a zero to all following active elements */ if (first_mask_bit) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); continue; } - if (vext_elem_mask(vs2, mlen, i)) { + if (vext_elem_mask(vs2, i)) { first_mask_bit =3D true; if (type =3D=3D BEFORE_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } else { if (type =3D=3D ONLY_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } } for (; i < vlmax; i++) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } } =20 @@ -4650,19 +4617,18 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2,= CPURISCVState *env, void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t sum =3D 0; = \ int i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D sum; = \ - if (vext_elem_mask(vs2, mlen, i)) { \ + if (vext_elem_mask(vs2, i)) { \ sum++; \ } \ } \ @@ -4678,14 +4644,13 @@ GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq) #define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ int i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D i; = \ @@ -4707,14 +4672,13 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ target_ulong offset =3D s1, i; = \ \ for (i =3D offset; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ @@ -4732,15 +4696,14 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, c= learq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ target_ulong offset =3D s1, i; = \ \ for (i =3D 0; i < vl; ++i) { = \ target_ulong j =3D i + offset; = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D j >=3D vlmax ? 0 : *((ETYPE *)vs2 + H(j)= ); \ @@ -4758,14 +4721,13 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H= 8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (i =3D=3D 0) { = \ @@ -4787,14 +4749,13 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8,= clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (i =3D=3D vl - 1) { = \ @@ -4817,14 +4778,13 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t,= H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t index, i; \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ index =3D *((ETYPE *)vs1 + H(i)); = \ @@ -4847,14 +4807,13 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, c= learq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t index =3D s1, i; = \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (index >=3D vlmax) { = \ @@ -4877,13 +4836,12 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, c= learq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen =3D vext_mlen(desc); = \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ + uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vl =3D env->vl; = \ uint32_t num =3D 0, i; = \ \ for (i =3D 0; i < vl; i++) { = \ - if (!vext_elem_mask(vs1, mlen, i)) { \ + if (!vext_elem_mask(vs1, i)) { \ continue; \ } \ *((ETYPE *)vd + H(num)) =3D *((ETYPE *)vs2 + H(i)); = \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce the concepts of fractional LMUL, EEW and EMUL for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 16 ++++++++++------ target/riscv/insn_trans/trans_rvv.inc.c | 17 ++++++++++++++--- target/riscv/internals.h | 11 +++++++++-- target/riscv/translate.c | 4 ++++ target/riscv/vector_helper.c | 10 ++++++++-- 5 files changed, 45 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a175151da..a16c6ed8e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,8 +96,9 @@ typedef struct CPURISCVState CPURISCVState; =20 FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VFLMUL, 5, 1) +FIELD(VTYPE, VEDIV, 8, 9) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { @@ -368,9 +369,10 @@ typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) -FIELD(TB_FLAGS, LMUL, 3, 2) -FIELD(TB_FLAGS, SEW, 5, 3) -FIELD(TB_FLAGS, VILL, 8, 1) +FIELD(TB_FLAGS, LMUL, 3, 3) +FIELD(TB_FLAGS, SEW, 6, 3) +/* Skip MSTATUS_VS (0x600) fields */ +FIELD(TB_FLAGS, VILL, 11, 1) =20 /* * A simplification for VLMAX @@ -399,12 +401,14 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, if (riscv_has_ext(env, RVV)) { uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, FIELD_EX64(env->vtype, VTYPE, VSEW)); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); + (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2) + | FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 018a134599..f6f0954c60 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -249,6 +249,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } @@ -301,6 +302,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } @@ -387,6 +389,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -425,6 +428,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); fn =3D fns[seq][s->sew]; if (fn =3D=3D NULL) { @@ -516,6 +520,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -559,6 +564,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } @@ -637,6 +643,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uin= t8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldff_trans(a->rd, a->rs1, data, fn, s); } @@ -746,6 +753,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); data =3D FIELD_DP32(data, VDATA, WD, a->wd); return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); } @@ -1644,7 +1652,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) vreg_ofs(s, a->rs1), MAXSZ(s), MAXSZ(s)); } else { - uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + uint32_t data =3D 0; + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, @@ -1682,7 +1691,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) TCGv_i32 desc ; TCGv_i64 s1_i64 =3D tcg_temp_new_i64(); TCGv_ptr dest =3D tcg_temp_new_ptr(); - uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + uint32_t data =3D 0; + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -1720,7 +1730,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) TCGv_i32 desc; TCGv_i64 s1; TCGv_ptr dest; - uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + uint32_t data =3D 0; + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 89fc0753bc..eaf792db5b 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -24,8 +24,9 @@ /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) -FIELD(VDATA, NF, 4, 4) -FIELD(VDATA, WD, 4, 1) +FIELD(VDATA, SEW, 4, 3) +FIELD(VDATA, NF, 7, 4) +FIELD(VDATA, WD, 7, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); @@ -37,4 +38,10 @@ target_ulong fclass_d(uint64_t frs1); #define SEW32 2 #define SEW64 3 =20 +/* table to convert fractional LMUL value */ +static const float flmul_table[8] =3D { + 1, 2, 4, 8, /* LMUL */ + -1, /* reserved */ + 0.125, 0.25, 0.5 /* fractional LMUL */ +}; #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7593b41a1f..72eb7c2e74 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -60,6 +60,9 @@ typedef struct DisasContext { /* vector extension */ bool vill; uint8_t lmul; + float flmul; + uint8_t eew; + float emul; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -823,6 +826,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->flmul =3D flmul_table[ctx->lmul]; ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6545f91732..a7963c3a2b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -86,9 +86,15 @@ static inline uint32_t vext_vm(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VM); } =20 -static inline uint32_t vext_lmul(uint32_t desc) +static inline uint32_t vext_sew(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); + return 1 << (FIELD_EX32(simd_data(desc), VDATA, SEW) + 3); +} + +static inline float vext_vflmul(uint32_t desc) +{ + uint32_t lmul =3D FIELD_EX32(simd_data(desc), VDATA, LMUL); + return flmul_table[lmul]; } =20 static uint32_t vext_wd(uint32_t desc) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410130; cv=none; d=zohomail.com; s=zohoarc; b=kDjc4PKmHMEU0JqGxzn9Tj/r77WDuKRI2KQKS68Lv3o4T3RjPWXpnIfUGNMYtpNQ5tu1XDT6VmuuTXnadXr2MqmE1ivQwsvBmCYU4rIU2DJw/H02o00DUL8SN8ES62TrmJML/xRe62kZ2DT45puutAThpvPHbg7KAZ9aWL+LrN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce the concepts of VMA and VTA for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 11 +- target/riscv/insn_trans/trans_rvv.inc.c | 62 +++++++++ target/riscv/internals.h | 6 +- target/riscv/translate.c | 4 + target/riscv/vector_helper.c | 165 +++++++++++++++++------- 5 files changed, 195 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a16c6ed8e6..a650df0441 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,6 +97,8 @@ typedef struct CPURISCVState CPURISCVState; FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VFLMUL, 5, 1) +FIELD(VTYPE, VTA, 6, 1) +FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 9) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) @@ -372,7 +374,10 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) FIELD(TB_FLAGS, LMUL, 3, 3) FIELD(TB_FLAGS, SEW, 6, 3) /* Skip MSTATUS_VS (0x600) fields */ -FIELD(TB_FLAGS, VILL, 11, 1) +FIELD(TB_FLAGS, VTA, 11, 1) +FIELD(TB_FLAGS, VMA, 12, 1) +/* Skip MSTATUS_FS (0x6000) fields */ +FIELD(TB_FLAGS, VILL, 15, 1) =20 /* * A simplification for VLMAX @@ -409,6 +414,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2) | FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index f6f0954c60..0cbecdd786 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -250,6 +250,8 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } @@ -303,6 +305,8 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } @@ -390,6 +394,8 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -429,6 +435,8 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); fn =3D fns[seq][s->sew]; if (fn =3D=3D NULL) { @@ -521,6 +529,8 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -565,6 +575,8 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } @@ -644,6 +656,8 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uin= t8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); return ldff_trans(a->rd, a->rs1, data, fn, s); } @@ -754,6 +768,8 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, SEW, s->sew); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, WD, a->wd); return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); } @@ -832,6 +848,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn = *gvec_fn, =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fn); @@ -877,6 +895,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -1025,6 +1045,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, } data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -1120,6 +1142,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), @@ -1208,6 +1232,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), @@ -1286,6 +1312,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -1476,6 +1504,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -1654,6 +1684,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) } else { uint32_t data =3D 0; data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, @@ -1693,6 +1724,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) TCGv_ptr dest =3D tcg_temp_new_ptr(); uint32_t data =3D 0; data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -1732,6 +1764,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) TCGv_ptr dest; uint32_t data =3D 0; data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -1848,6 +1882,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -1920,6 +1956,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -1960,6 +1998,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -1997,6 +2037,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2033,6 +2075,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -2068,6 +2112,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_set_rm(s, 7); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2147,6 +2193,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ @@ -2289,6 +2337,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ @@ -2337,6 +2387,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ s->vlen / 8, data, fns[s->sew - 1]); \ @@ -2398,6 +2450,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, 0, \ @@ -2428,6 +2481,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) uint32_t data =3D 0; data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); @@ -2459,6 +2513,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) uint32_t data =3D 0; data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); @@ -2494,6 +2549,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, 0, s->vlen / 8, data, fn); \ @@ -2521,6 +2577,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_3_ptr * const fns[4] =3D { gen_helper_viota_m_b, gen_helper_viota_m_h, gen_helper_viota_m_w, gen_helper_viota_m_d, @@ -2547,6 +2605,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vid_v_b, gen_helper_vid_v_h, gen_helper_vid_v_w, gen_helper_vid_v_d, @@ -2907,6 +2967,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, 0, s->vlen / 8, data, fns[s->sew]); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index eaf792db5b..4538e5faf8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -25,8 +25,10 @@ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) FIELD(VDATA, SEW, 4, 3) -FIELD(VDATA, NF, 7, 4) -FIELD(VDATA, WD, 7, 1) +FIELD(VDATA, VTA, 7, 1) +FIELD(VDATA, VMA, 8, 1) +FIELD(VDATA, NF, 9, 4) +FIELD(VDATA, WD, 9, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 72eb7c2e74..4599e3574e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -63,6 +63,8 @@ typedef struct DisasContext { float flmul; uint8_t eew; float emul; + uint8_t vta; + uint8_t vma; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -827,6 +829,8 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->flmul =3D flmul_table[ctx->lmul]; + ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA); + ctx->vma =3D FIELD_EX32(tb_flags, TB_FLAGS, VMA); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a7963c3a2b..83e317c500 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -102,6 +102,16 @@ static uint32_t vext_wd(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, WD); } =20 +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + /* * Get vector group length in bytes. Its range is [64, 2048]. * @@ -141,9 +151,15 @@ static void probe_pages(CPURISCVState *env, target_ulo= ng addr, } =20 #ifdef HOST_WORDS_BIGENDIAN -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) +static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t to= t) { + if (vta =3D=3D 0) { + /* tail element undisturbed */ + return; + } + /* + * Tail element agnostic. * Split the remaining range to two parts. * The first part is in the last uint64_t unit. * The second part start from the next uint64_t unit. @@ -152,41 +168,50 @@ static void vext_clear(void *tail, uint32_t cnt, uint= 32_t tot) if (cnt % 8) { part1 =3D 8 - (cnt % 8); part2 =3D tot - cnt - part1; - memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); - memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); + memset((void *)((uintptr_t)tail & ~(7ULL)), 1, part1); + memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 1, part2); } else { - memset(tail, 0, part2); + memset(tail, 1, part2); } } #else -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) +static void vext_clear(void *tail, uint32_t vta, uint32_t cnt, uint32_t to= t) { - memset(tail, 0, tot - cnt); + if (vta =3D=3D 0) { + /* tail element undisturbed */ + return; + } + /* tail element agnostic */ + memset(tail, 1, tot - cnt); } #endif =20 -static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) +static void clearb(void *vd, uint32_t vta, uint32_t idx, + uint32_t cnt, uint32_t tot) { int8_t *cur =3D ((int8_t *)vd + H1(idx)); - vext_clear(cur, cnt, tot); + vext_clear(cur, vta, cnt, tot); } =20 -static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) +static void clearh(void *vd, uint32_t vta, uint32_t idx, + uint32_t cnt, uint32_t tot) { int16_t *cur =3D ((int16_t *)vd + H2(idx)); - vext_clear(cur, cnt, tot); + vext_clear(cur, vta, cnt, tot); } =20 -static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) +static void clearl(void *vd, uint32_t vta, uint32_t idx, + uint32_t cnt, uint32_t tot) { int32_t *cur =3D ((int32_t *)vd + H4(idx)); - vext_clear(cur, cnt, tot); + vext_clear(cur, vta, cnt, tot); } =20 -static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) +static void clearq(void *vd, uint32_t vta, uint32_t idx, + uint32_t cnt, uint32_t tot) { int64_t *cur =3D (int64_t *)vd + idx; - vext_clear(cur, cnt, tot); + vext_clear(cur, vta, cnt, tot); } =20 static inline void vext_set_elem_mask(void *v0, int index, @@ -213,7 +238,8 @@ static inline int vext_elem_mask(void *v0, int index) /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); -typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot); +typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx, + uint32_t cnt, uint32_t tot); =20 #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -284,6 +310,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vta =3D vext_vta(desc); =20 /* probe every access*/ for (i =3D 0; i < env->vl; i++) { @@ -307,7 +334,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz= ); + clear_elem(vd, vta, env->vl + k * vlmax, + env->vl * esz, vlmax * esz); } } } @@ -385,6 +413,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vta =3D vext_vta(desc); =20 /* probe every access */ probe_pages(env, base, env->vl * nf * msz, ra, access_type); @@ -400,7 +429,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz= ); + clear_elem(vd, vta, env->vl + k * vlmax, + env->vl * esz, vlmax * esz); } } } @@ -512,6 +542,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vta =3D vext_vta(desc); =20 /* probe every access*/ for (i =3D 0; i < env->vl; i++) { @@ -536,7 +567,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz= ); + clear_elem(vd, vta, env->vl + k * vlmax, + env->vl * esz, vlmax * esz); } } } @@ -611,6 +643,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vta =3D vext_vta(desc); target_ulong addr, offset, remain; =20 /* probe every access*/ @@ -670,7 +703,8 @@ ProbeSuccess: return; } for (k =3D 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * vlmax, + env->vl * esz, vlmax * esz); } } =20 @@ -788,6 +822,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, uint32_t wd =3D vext_wd(desc); uint32_t vm =3D vext_vm(desc); uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vta =3D vext_vta(desc); =20 for (i =3D 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -803,7 +838,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, addr =3D get_index_addr(base, i, vs2); noatomic_op(vs3, addr, wd, i, env, ra); } - clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); + clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz); } =20 #define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \ @@ -914,6 +949,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, v= oid *vs2, { uint32_t vlmax =3D vext_maxsz(desc) / esz; uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; =20 @@ -923,7 +959,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, v= oid *vs2, } fn(vd, vs1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate the helpers for OPIVV */ @@ -978,6 +1014,7 @@ static void do_vext_vx(void *vd, void *v0, target_long= s1, void *vs2, { uint32_t vlmax =3D vext_maxsz(desc) / esz; uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; =20 @@ -987,7 +1024,7 @@ static void do_vext_vx(void *vd, void *v0, target_long= s1, void *vs2, } fn(vd, s1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate the helpers for OPIVX */ @@ -1175,6 +1212,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -1184,7 +1222,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, s1, carry); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb) @@ -1204,6 +1242,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t vlmax =3D vext_maxsz(desc) / esz; = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ @@ -1212,7 +1251,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, (ETYPE)(target_long)s1, carry)= ;\ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb) @@ -1353,6 +1392,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(TS1); = \ uint32_t vlmax =3D vext_maxsz(desc) / esz; = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { = \ @@ -1363,7 +1403,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); = \ *((TS1 *)vd + HS1(i)) =3D OP(s2, s1 & MASK); = \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clear= b) @@ -1390,6 +1430,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(TD); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -1399,7 +1440,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ *((TD *)vd + HD(i)) =3D OP(s2, s1 & MASK); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb) @@ -2032,13 +2073,14 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVStat= e *env, \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ *((ETYPE *)vd + H(i)) =3D s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb) @@ -2053,12 +2095,13 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVSt= ate *env, \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ *((ETYPE *)vd + H(i)) =3D (ETYPE)s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb) @@ -2073,13 +2116,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ ETYPE *vt =3D (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) =3D *(vt + H(i)); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb) @@ -2094,6 +2138,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -2102,7 +2147,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) =3D d; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) @@ -2155,6 +2200,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, { uint32_t vlmax =3D vext_maxsz(desc) / esz; uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; =20 switch (env->vxrm) { @@ -2176,7 +2222,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, break; } =20 - clearfn(vd, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate helpers for fixed point instructions with OPIVV format */ @@ -2274,6 +2320,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, { uint32_t vlmax =3D vext_maxsz(desc) / esz; uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; =20 switch (env->vxrm) { @@ -2295,7 +2342,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, break; } =20 - clearfn(vd, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate helpers for fixed point instructions with OPIVX format */ @@ -3177,6 +3224,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ @@ -3186,7 +3234,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ } \ do_##NAME(vd, vs1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \ } =20 RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) @@ -3211,6 +3259,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ @@ -3220,7 +3269,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ } \ do_##NAME(vd, s1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \ } =20 RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) @@ -3781,6 +3830,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ @@ -3793,7 +3843,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ } \ do_##NAME(vd, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \ } =20 RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) @@ -4101,6 +4151,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ { \ uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ \ @@ -4110,7 +4161,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ } \ do_##NAME(vd, vs2, i); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + CLEAR_FN(vd, vta, vl, vl * DSZ, vlmax * DSZ); \ } =20 target_ulong fclass_h(uint64_t frs1) @@ -4186,6 +4237,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -4193,7 +4245,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ *((ETYPE *)vd + H(i)) \ =3D (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + CLEAR_FN(vd, vta, vl, vl * esz, vlmax * esz); \ } =20 GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) @@ -4323,6 +4375,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; \ @@ -4336,7 +4389,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ s1 =3D OP(s1, (TD)s2); \ } \ *((TD *)vd + HD(0)) =3D s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ + CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \ } =20 /* vd[0] =3D sum(vs1[0], vs2[*]) */ @@ -4405,6 +4458,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; \ @@ -4418,7 +4472,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ s1 =3D OP(s1, (TD)s2, &env->fp_status); \ } \ *((TD *)vd + HD(0)) =3D s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ + CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \ } =20 /* Unordered sum */ @@ -4442,6 +4496,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void = *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; @@ -4456,13 +4511,14 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, voi= d *vs1, &env->fp_status); } *((uint32_t *)vd + H4(0)) =3D s1; - clearl(vd, 1, sizeof(uint32_t), tot); + clearl(vd, vta, 1, sizeof(uint32_t), tot); } =20 void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; @@ -4477,7 +4533,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void = *vs1, &env->fp_status); } *((uint64_t *)vd) =3D s1; - clearq(vd, 1, sizeof(uint64_t), tot); + clearq(vd, vta, 1, sizeof(uint64_t), tot); } =20 /* @@ -4625,6 +4681,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPUR= ISCVState *env, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t sum =3D 0; = \ int i; \ @@ -4638,7 +4695,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPUR= ISCVState *env, \ sum++; \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) @@ -4652,6 +4709,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *= env, uint32_t desc) \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ int i; \ \ @@ -4661,7 +4719,7 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *= env, uint32_t desc) \ } \ *((ETYPE *)vd + H(i)) =3D i; = \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb) @@ -4680,6 +4738,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ target_ulong offset =3D s1, i; = \ \ @@ -4689,7 +4748,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] =3D vs2[i] */ @@ -4704,6 +4763,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ target_ulong offset =3D s1, i; = \ \ @@ -4714,7 +4774,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ } \ *((ETYPE *)vd + H(i)) =3D j >=3D vlmax ? 0 : *((ETYPE *)vs2 + H(j)= ); \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+rs1] */ @@ -4729,6 +4789,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -4742,7 +4803,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=3Dx[rs1], vd[i+1] =3D vs2[i] */ @@ -4757,6 +4818,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -4770,7 +4832,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+1], vd[vl-1]=3Dx[rs1]= */ @@ -4786,6 +4848,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t index, i; \ \ @@ -4800,7 +4863,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(index)); = \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vd[i] =3D (vs1[i] >=3D VLMAX) ? 0 : vs2[vs1[i]]; */ @@ -4815,6 +4878,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t index =3D s1, i; = \ \ @@ -4828,7 +4892,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(index)); = \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vd[i] =3D (x[rs1] >=3D VLMAX) ? 0 : vs2[rs1] */ @@ -4843,6 +4907,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t num =3D 0, i; = \ \ @@ -4853,7 +4918,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ *((ETYPE *)vd + H(num)) =3D *((ETYPE *)vs2 + H(i)); = \ num++; \ } \ - CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + CLEAR_FN(vd, vta, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* Compress into vd elements of vs2 where vs1 is enabled */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595409911; cv=none; d=zohomail.com; s=zohoarc; b=NlB/4alCENIpDubsPJ9fzvI4YUZ5dLGSZWGCD548Hgk1upc8FD7EcYSKToMX4MvzbqwsBb2Qx+4fTYdhgCyuuy7TucdEKmpfR7r9t7h+VTGt2qUMb+/h/8fg+2jiRgFvmGeAW5oOtdLxnkdNqO6oq8Xi84zKp7bwqNcY4zEfyeo= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update check functions with RVV 0.9 rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 706 ++++++++++++++++-------- 1 file changed, 474 insertions(+), 232 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 0cbecdd786..13b6098153 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -19,11 +19,79 @@ #include "tcg/tcg-gvec-desc.h" #include "internals.h" =20 +#define NVPR 32 + +static inline bool is_aligned(const unsigned val, const unsigned pos) +{ + return pos ? (val & (pos - 1)) =3D=3D 0 : true; +} + +static inline bool is_overlapped(const int astart, int asize, + const int bstart, int bsize) +{ + asize =3D asize =3D=3D 0 ? 1 : asize; + bsize =3D bsize =3D=3D 0 ? 1 : bsize; + + const int aend =3D astart + asize; + const int bend =3D bstart + bsize; + + return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize; +} + +static inline bool is_overlapped_widen(const int astart, int asize, + const int bstart, int bsize) +{ + asize =3D asize =3D=3D 0 ? 1 : asize; + bsize =3D bsize =3D=3D 0 ? 1 : bsize; + + const int aend =3D astart + asize; + const int bend =3D bstart + bsize; + + if (astart < bstart && + is_overlapped(astart, asize, bstart, bsize) && + !is_overlapped(astart, asize, bstart + bsize, bsize)) { + return false; + } else { + return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize; + } +} + +static bool require_rvv(DisasContext *s) +{ + if (s->mstatus_vs =3D=3D 0) { + return false; + } + return true; +} + +/* Destination vector register group cannot overlap source mask register. = */ +static bool require_vm(int vm, int rd) +{ + return (vm !=3D 0 || rd !=3D 0); +} + +static bool require_align(const unsigned val, const unsigned pos) +{ + return is_aligned(val, pos); +} + +static bool require_noover(const int astart, const int asize, + const int bstart, const int bsize) +{ + return !is_overlapped(astart, asize, bstart, bsize); +} + +static bool require_noover_widen(const int astart, const int asize, + const int bstart, const int bsize) +{ + return !is_overlapped_widen(astart, asize, bstart, bsize); +} + static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) { TCGv s1, s2, dst; =20 - if (!has_ext(ctx, RVV)) { + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { return false; } =20 @@ -56,7 +124,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli= *a) { TCGv s1, s2, dst; =20 - if (!has_ext(ctx, RVV)) { + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { return false; } =20 @@ -101,53 +169,264 @@ static bool vext_check_isa_ill(DisasContext *s) } =20 /* - * There are two rules check here. + * Check function for vector instruction with format: + * single-width result and single-width sources (SEW =3D SEW op SEW) * - * 1. Vector register numbers are multiples of LMUL. (Section 3.2) + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. * - * 2. For all widening instructions, the destination LMUL value must also = be - * a supported LMUL value. (Section 11.2) + * Rules to be checked here: + * 1. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.3.2) + * 3. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.3.2) */ -static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) +static bool vext_check_sss(DisasContext *s, int vd, int vs1, + int vs2, int vm, bool is_vs1) +{ + bool ret =3D require_vm(vm, vd); + if (s->flmul > 1) { + ret &=3D require_align(vd, s->flmul) && + require_align(vs2, s->flmul); + if (is_vs1) { + ret &=3D require_align(vs1, s->flmul); + } + } + return ret; +} + +/* + * Check function for maskable vector instruction with format: + * single-width result and single-width sources (SEW =3D SEW op SEW) + * + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. + * + * Rules to be checked here: + * 1. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.3.2) + * 2. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + */ +static bool vext_check_mss(DisasContext *s, int vd, int vs1, + int vs2, bool is_vs1) { - /* - * The destination vector register group results are arranged as if bo= th - * SEW and LMUL were at twice their current settings. (Section 11.2). - */ - int legal =3D widen ? 2 << s->lmul : 1 << s->lmul; + bool ret =3D require_align(vs2, s->flmul); + if (vd !=3D vs2) { + ret &=3D require_noover(vd, 1, vs2, s->flmul); + } + if (is_vs1) { + if (vd !=3D vs1) { + ret &=3D require_noover(vd, 1, vs1, s->flmul); + } + ret &=3D require_align(vs1, s->flmul); + } + return ret; +} =20 - return !((s->lmul =3D=3D 0x3 && widen) || (reg % legal)); +/* + * Common check function for vector widening instructions + * of double-width result (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * =3D> LMUL < 8. + * =3D> SEW < 64. + * 2. Destination vector register number is multiples of 2 * LMUL. + * (Section 3.3.2, 11.2) + * 3. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_wide_check_common(DisasContext *s, int vd, int vm) +{ + return (s->flmul <=3D 4) && + (s->sew < 3) && + require_align(vd, s->flmul * 2) && + require_vm(vm, vd); } =20 /* - * There are two rules check here. + * Common check function for vector narrowing instructions + * of single-width result (SEW) and double-width source (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * =3D> LMUL < 8. + * =3D> SEW < 64. + * 2. Source vector register number is multiples of 2 * LMUL. + * (Section 3.3.2, 11.3) + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.3.2, 11.3) + * 4. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->flmul <=3D 4) && + (s->sew < 3) && + require_align(vs2, s->flmul * 2) && + require_align(vd, s->flmul) && + require_vm(vm, vd); +} + +/* + * Check function for vector instruction with format: + * double-width result and single-width sources (2*SEW =3D SEW op SEW) * - * 1. The destination vector register group for a masked vector instructio= n can - * only overlap the source mask register (v0) when LMUL=3D1. (Section 5= .3) + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. * - * 2. In widen instructions and some other insturctions, like vslideup.vx, - * there is no need to check whether LMUL=3D1. + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.3.2) + * 3. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) */ -static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm, - bool force) +static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, + int vm, bool is_vs1) { - return (vm !=3D 0 || vd !=3D 0) || (!force && (s->lmul =3D=3D 0)); + bool ret =3D (vext_wide_check_common(s, vd, vm) && + require_align(vs2, s->flmul)); + if (s->flmul < 1) { + ret &=3D require_noover(vd, s->flmul * 2, vs2, s->flmul); + } else { + ret &=3D require_noover_widen(vd, s->flmul * 2, vs2, s->flmul); + } + if (is_vs1) { + ret &=3D require_align(vs1, s->flmul); + if (s->flmul < 1) { + ret &=3D require_noover(vd, s->flmul * 2, vs1, s->flmul); + } else { + ret &=3D require_noover_widen(vd, s->flmul * 2, vs1, s->flmul); + } + } + return ret; } =20 -/* The LMUL setting must be such that LMUL * NFIELDS <=3D 8. (Section 7.8)= */ -static bool vext_check_nf(DisasContext *s, uint32_t nf) +/* + * Check function for vector instruction with format: + * double-width result and double-width source1 and single-width + * source2 (2*SEW =3D 2*SEW op SEW) + * + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. + * + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source 1 (vs2) vector register number is multiples of 2 * LMUL. + * (Section 3.3.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.3.2) + * 4. Destination vector register cannot overlap a source vector + * register (vs1) group. + * (Section 5.2) + */ +static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, + int vm, bool is_vs1) +{ + bool ret =3D (vext_wide_check_common(s, vd, vm) && + require_align(vs2, s->flmul * 2)); + if (is_vs1) { + ret &=3D require_align(vs1, s->flmul); + if (s->flmul < 1) { + ret &=3D require_noover(vd, s->flmul * 2, vs1, s->flmul); + } else { + ret &=3D require_noover_widen(vd, s->flmul * 2, vs1, s->flmul); + } + } + return ret; +} + +/* + * Check function for vector instruction with format: + * single-width result and double-width source 1 and single-width + * source 2 (SEW =3D 2*SEW op SEW) + * + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. + * + * Rules to be checked here: + * 1. All rules in defined in narrow common rules are applied. + * 2. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.3.2) + */ +static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, + int vm, bool is_vs1) { - return (1 << s->lmul) * nf <=3D 8; + bool ret =3D vext_narrow_check_common(s, vd, vs2, vm); + if (vd !=3D vs2) { + ret &=3D require_noover(vd, s->flmul, vs2, s->flmul * 2); + } + if (is_vs1) { + ret &=3D require_align(vs1, s->flmul); + } + return ret; } =20 /* - * The destination vector register group cannot overlap a source vector re= gister - * group of a different element width. (Section 11.2) + * Check function for vector reduction instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.3.2) + * 2. For widening reduction instructions, SEW < 64. + * + * TODO: Check vstart =3D=3D 0 */ -static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int = slen) +static bool vext_check_reduction(DisasContext *s, int vs2, bool is_wide) { - return ((rd >=3D rs + slen) || (rs >=3D rd + dlen)); + bool ret =3D require_align(vs2, s->flmul); + if (is_wide) { + ret &=3D s->sew < 3; + } + return ret; } + +/* + * Check function for vector slide instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.3.2) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.3.2) + * 3. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 4. The destination vector register group for vslideup, vslide1up, + * vfslide1up, cannot overlap the source vector register (vs2) group. + * (Section 5.2, 17.3.1, 17.3.3) + */ +static bool vext_check_slide(DisasContext *s, int vd, int vs2, + int vm, bool is_over) +{ + bool ret =3D require_align(vs2, s->flmul) && + require_align(vd, s->flmul) && + require_vm(vm, vd); + if (is_over) { + ret &=3D (vd !=3D vs2); + } + return ret; +} + +/* + * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. + * So RVV is also be checked in this function. + */ +static bool vext_check_isa_ill(DisasContext *s) +{ + return !s->vill; +} + /* common translation macro */ #define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ @@ -818,11 +1097,9 @@ GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_ch= eck) =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, true); } =20 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, @@ -917,10 +1194,9 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, =20 static bool opivx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, false); } =20 typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, @@ -1119,16 +1395,9 @@ GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) /* OPIVV with WIDEN */ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm, true); } =20 static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, @@ -1175,13 +1444,9 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check) /* OPIVX with WIDEN */ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm, false); } =20 static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, @@ -1212,14 +1477,9 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx) /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm, true); } =20 static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, @@ -1264,11 +1524,9 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv) /* WIDEN OPIVX with WIDEN */ static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm, false); } =20 static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a, @@ -1331,11 +1589,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((a->rd !=3D 0) || (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd !=3D 0) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, true); } =20 GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check) @@ -1347,11 +1604,9 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check) */ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, true); } =20 GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) @@ -1359,10 +1614,10 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check) =20 static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((a->rd !=3D 0) || (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd !=3D 0) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, false); } =20 /* OPIVX without GVEC IR */ @@ -1385,9 +1640,9 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check) =20 static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, false); } =20 GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) @@ -1478,14 +1733,9 @@ GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm, true); } =20 /* OPIVV with NARROW */ @@ -1521,13 +1771,9 @@ GEN_OPIVV_NARROW_TRANS(vnsrl_vv) =20 static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm, false); } =20 /* OPIVX with NARROW */ @@ -1575,13 +1821,11 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) */ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, true); } + GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check) @@ -1591,10 +1835,9 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check) =20 static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, false); } =20 GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) @@ -1673,10 +1916,10 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.v has rs2 =3D 0 and vm =3D 1 */ + vext_check_sss(s, a->rd, a->rs1, 0, 1, true)) { if (s->vl_eq_vlmax) { tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -1705,9 +1948,10 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v= _v *a) typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.x has rs2 =3D 0 and vm =3D 1 */ + vext_check_sss(s, a->rd, a->rs1, 0, 1, false)) { TCGv s1; TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -1750,9 +1994,10 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v= _x *a) =20 static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.i has rs2 =3D 0 and vm =3D 1 */ + vext_check_sss(s, a->rd, a->rs1, 0, 1, false)) { int64_t simm =3D sextract64(a->rs1, 0, 5); if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), @@ -1857,12 +2102,10 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) */ static bool opfvv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, true) && + (s->sew !=3D 0); } =20 /* OPFVV without GVEC IR */ @@ -1929,17 +2172,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, = uint32_t vs2, return true; } =20 -static bool opfvf_check(DisasContext *s, arg_rmrr *a) -{ /* * If the current SEW does not correspond to a supported IEEE floating-poi= nt * type, an illegal instruction exception is raised */ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew !=3D 0)); +static bool opfvf_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + has_ext(s, RVF) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 /* OPFVF without GVEC IR */ @@ -1971,16 +2214,10 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) /* Vector Widening Floating-Point Add/Subtract Instructions */ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm, true) && + (s->sew !=3D 0); } =20 /* OPFVV with WIDEN */ @@ -2016,13 +2253,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) =20 static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 /* OPFVF with WIDEN */ @@ -2050,14 +2284,10 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) =20 static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm, true) && + (s->sew !=3D 0); } =20 /* WIDEN OPFVV with WIDEN */ @@ -2093,11 +2323,10 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) =20 static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 /* WIDEN OPFVF with WIDEN */ @@ -2170,11 +2399,11 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) */ static bool opfv_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV instructions ignore vs1 check */ + vext_check_sss(s, a->rd, 0, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 #define GEN_OPFV_TRANS(NAME, CHECK) \ @@ -2224,13 +2453,10 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) /* Vector Floating-Point Compare Instructions */ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew !=3D 0) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, true) && + (s->sew !=3D 0); } =20 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) @@ -2241,11 +2467,10 @@ GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) =20 static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (s->sew !=3D 0) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul =3D=3D 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2, false) && + (s->sew !=3D 0); } =20 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) @@ -2264,10 +2489,10 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) =20 static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->flmul) && (s->sew !=3D 0)) { - if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); @@ -2313,13 +2538,11 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) */ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV widening instructions ignore vs1 check */ + vext_check_dss(s, a->rd, 0, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 #define GEN_OPFV_WIDEN_TRANS(NAME) \ @@ -2363,13 +2586,11 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) */ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew !=3D 0)); + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sds(s, a->rd, 0, a->rs2, a->vm, false) && + (s->sew !=3D 0); } =20 #define GEN_OPFV_NARROW_TRANS(NAME) \ @@ -2411,7 +2632,9 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) /* Vector Single-Width Integer Reduction Instructions */ static bool reduction_check(DisasContext *s, arg_rmrr *a) { - return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_reduction(s, a->rs2, false); } =20 GEN_OPIVV_TRANS(vredsum_vs, reduction_check) @@ -2424,8 +2647,15 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check) GEN_OPIVV_TRANS(vredxor_vs, reduction_check) =20 /* Vector Widening Integer Reduction Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) -GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) +static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_reduction(s, a->rs2, true); +} + +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) @@ -2474,7 +2704,8 @@ GEN_MM_TRANS(vmxnor_mm) /* Vector mask population count vmpopc */ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2506,7 +2737,8 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) /* vmfirst find-first-set mask bit */ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2567,10 +2799,11 @@ GEN_M_TRANS(vmsof_m) /* Vector Iota Instruction */ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && - (a->vm !=3D 0 || a->rd !=3D 0)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_noover(a->rd, s->flmul, a->rs2, 1) && + require_vm(a->vm, a->rd) && + require_align(a->rd, s->flmul)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2596,9 +2829,10 @@ static bool trans_viota_m(DisasContext *s, arg_viota= _m *a) /* Vector Element Index Instruction */ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_mask(s, a->rd, a->vm, false)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->flmul) && + require_vm(a->vm, a->rd)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2850,41 +3084,48 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfm= v_s_f *a) /* Vector Slide Instructions */ static bool slideup_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd !=3D a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, true); } =20 GEN_OPIVX_TRANS(vslideup_vx, slideup_check) GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) =20 -GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) +static bool slidedown_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, false); +} + +GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) +GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) +GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check) =20 /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd !=3D a->rs2) && (a->rd !=3D a->rs1)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->flmul) && + require_align(a->rs1, s->flmul) && + require_align(a->rs2, s->flmul) && + (a->rd !=3D a->rs2 && a->rd !=3D a->rs1) && + require_vm(a->vm, a->rd); } =20 GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) =20 static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd !=3D a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->flmul) && + require_align(a->rs2, s->flmul) && + (a->rd !=3D a->rs2) && + require_vm(a->vm, a->rd); } =20 /* vrgather.vx vd, vs2, rs1, vm # vd[i] =3D (x[rs1] >=3D VLMAX) ? 0 : vs2[= rs1] */ @@ -2948,11 +3189,12 @@ static bool trans_vrgather_vi(DisasContext *s, arg_= rmrr *a) /* Vector Compress Instruction */ static bool vcompress_vm_check(DisasContext *s, arg_r *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && - (a->rd !=3D a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->flmul) && + require_align(a->rs2, s->flmul) && + (a->rd !=3D a->rs2) && + require_noover(a->rd, s->flmul, a->rs1, 1); } =20 static bool trans_vcompress_vm(DisasContext *s, arg_r *a) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW) bit * IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 120 +++++++++++++++--------- 1 file changed, 78 insertions(+), 42 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 13b6098153..22b4e11a20 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1300,8 +1300,13 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32= _t dofs, uint32_t aofs, =20 GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) =20 +#define IMM_ZX 0 /* Zero-extended */ +#define IMM_SX 1 /* Sign-extended */ +#define IMM_TRUNC_SEW 2 /* Truncate to log(SEW) bits */ +#define IMM_TRUNC_2SEW 3 /* Truncate to log(2*SEW) bits */ + static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t = vm, - gen_helper_opivx *fn, DisasContext *s, int zx) + gen_helper_opivx *fn, DisasContext *s, int imm_mod= e) { TCGv_ptr dest, src2, mask; TCGv src1; @@ -1314,10 +1319,24 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, = uint32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - if (zx) { - src1 =3D tcg_const_tl(imm); - } else { + switch (imm_mode) { + case IMM_ZX: + src1 =3D tcg_const_tl(extract64(imm, 0, 5)); + break; + case IMM_SX: src1 =3D tcg_const_tl(sextract64(imm, 0, 5)); + break; + case IMM_TRUNC_SEW: + src1 =3D tcg_const_tl( + extract64(imm, 0, 5) & ((1 << (s->sew + 3)) - 1) & 0x1f); + break; + case IMM_TRUNC_2SEW: + src1 =3D tcg_const_tl( + extract64(imm, 0, 5) & ((2 << (s->sew + 3)) - 1) & 0x1f); + break; + default: + g_assert_not_reached(); + break; } data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -1346,28 +1365,44 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32= _t, int64_t, =20 static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, - gen_helper_opivx *fn, int zx) + gen_helper_opivx *fn, int imm_mode) { if (!opivx_check(s, a)) { return false; } =20 if (a->vm && s->vl_eq_vlmax) { - if (zx) { + switch (imm_mode) { + case IMM_ZX: gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } else { + break; + case IMM_SX: gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); + break; + case IMM_TRUNC_SEW: + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + extract64(a->rs1, 0, 5) & ((1 << (s->sew + 3)) - 1) & = 0x1f, + MAXSZ(s), MAXSZ(s)); + break; + case IMM_TRUNC_2SEW: + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + extract64(a->rs1, 0, 5) & ((2 << (s->sew + 3)) - 1) & = 0x1f, + MAXSZ(s), MAXSZ(s)); + break; + default: + g_assert_not_reached(); + break; } mark_vs_dirty(s); return true; } - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode); } =20 /* OPIVI with GVEC IR */ -#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \ +#define GEN_OPIVI_GVEC_TRANS(NAME, IMM_MODE, OPIVX, SUF) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ static gen_helper_opivx * const fns[4] =3D { \ @@ -1375,10 +1410,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ - fns[s->sew], ZX); \ + fns[s->sew], IMM_MODE); \ } =20 -GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) +GEN_OPIVI_GVEC_TRANS(vadd_vi, IMM_SX, vadd_vx, addi) =20 static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) @@ -1388,7 +1423,7 @@ static void tcg_gen_gvec_rsubi(unsigned vece, uint32_= t dofs, uint32_t aofs, tcg_temp_free_i64(tmp); } =20 -GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) +GEN_OPIVI_GVEC_TRANS(vrsub_vi, IMM_SX, vrsub_vx, rsubi) =20 /* Vector Widening Integer Add/Subtract */ =20 @@ -1649,7 +1684,7 @@ GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) =20 /* OPIVI without GVEC IR */ -#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \ +#define GEN_OPIVI_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ if (CHECK(s, a)) { \ @@ -1658,13 +1693,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } =20 -GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) +GEN_OPIVI_TRANS(vadc_vim, IMM_SX, vadc_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmadc_vim, IMM_SX, vmadc_vxm, opivx_vmadc_check) =20 /* Vector Bitwise Logical Instructions */ GEN_OPIVV_GVEC_TRANS(vand_vv, and) @@ -1673,9 +1708,9 @@ GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) GEN_OPIVX_GVEC_TRANS(vand_vx, ands) GEN_OPIVX_GVEC_TRANS(vor_vx, ors) GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) -GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) -GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) -GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) +GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, IMM_SX, vxor_vx, xori) =20 /* Vector Single-Width Bit Shift Instructions */ GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv) @@ -1726,9 +1761,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) =20 -GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) =20 /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) @@ -1795,7 +1830,7 @@ GEN_OPIVX_NARROW_TRANS(vnsra_vx) GEN_OPIVX_NARROW_TRANS(vnsrl_vx) =20 /* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \ +#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ if (opivx_narrow_check(s, a)) { \ @@ -1805,13 +1840,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ gen_helper_##OPIVX##_w, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } =20 -GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) +GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx) +GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx) =20 /* Vector Integer Comparison Instructions */ /* @@ -1849,12 +1884,12 @@ GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) =20 -GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check) =20 /* Vector Integer Min/Max Instructions */ GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) @@ -2037,7 +2072,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) =20 GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmerge_vim, IMM_SX, vmerge_vxm, opivx_vadc_check) =20 /* *** Vector Fixed-Point Arithmetic Instructions @@ -2052,8 +2087,8 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) GEN_OPIVX_TRANS(vsadd_vx, opivx_check) GEN_OPIVX_TRANS(vssubu_vx, opivx_check) GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) -GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) =20 /* Vector Single-Width Averaging Add and Subtract */ GEN_OPIVV_TRANS(vaadd_vv, opivv_check) @@ -2080,16 +2115,16 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) GEN_OPIVX_TRANS(vssrl_vx, opivx_check) GEN_OPIVX_TRANS(vssra_vx, opivx_check) -GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) =20 /* Vector Narrowing Fixed-Point Clip Instructions */ GEN_OPIVV_NARROW_TRANS(vnclipu_vv) GEN_OPIVV_NARROW_TRANS(vnclip_vv) GEN_OPIVX_NARROW_TRANS(vnclipu_vx) GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) +GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) +GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) =20 /* *** Vector Float Point Arithmetic Instructions @@ -3091,7 +3126,7 @@ static bool slideup_check(DisasContext *s, arg_rmrr *= a) =20 GEN_OPIVX_TRANS(vslideup_vx, slideup_check) GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) -GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) +GEN_OPIVI_TRANS(vslideup_vi, IMM_ZX, vslideup_vx, slideup_check) =20 static bool slidedown_check(DisasContext *s, arg_rmrr *a) { @@ -3102,7 +3137,7 @@ static bool slidedown_check(DisasContext *s, arg_rmrr= *a) =20 GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check) +GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) =20 /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) @@ -3181,7 +3216,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d }; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:18:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5VzK4FfmnYHyUZyCqlp+i7B88c5pm8MmOilNV0BSO0Y=; b=QklJLJf2nBMImWuvTqWCq3S1nw+R2H/D7+SCjLAX2Wdd3xKsDc3KeOIhuK78NWLeZI wCRvvoADh/KxOlBOeuIhBRxWa+/QQHix1VWdhm9BmxYjlUcZbyacUSI/xzRUyx3SNcnC T5V79NHCdYKVmkGg1JTeOYoJuEouT49e6lo7XqyCpn1lGDPINPbYvwPjripr6eGPNDwC L3F/U5qaawDwGqfk2xJy4N3RVG0ynOm5eCOevDfCudbeqvCBNCtuCUgzJpVuJ4gbZrLY 1ugjq7pNuePuC+TjZDkqDfBi3Lf0BQRE6uOHacvONOUJSAHw6NQHYYx69ySj294Xw9K4 yvcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5VzK4FfmnYHyUZyCqlp+i7B88c5pm8MmOilNV0BSO0Y=; b=BX0trrQjdpFl+oSbbmXgB34VY/YE7+jpWng/7R0O9gR9iWnPsXlwRTN6MighBbI9Nn t3hayU8DoYs+tpYl9msHtzSEVs1FEgvOTPVspuUSxoHuU9orOfBZbzo9z+vsLT9OiV0R ftOM/ZV8zfFmtb53t9zBVkjjl8Rn+vabQnWQK7aM2s59QX+ZmcImWpYpjBEgNXAvaYtt XFcUYFO/tqfWvG6G4eOilOwGzgIgyBQrf01xb+VNnJ5mnwpQdHJWRZf/mZY4cEcpRWC/ AzDwT5mK7Q8SrRPU9TV0UEgqSIz+T6tp/ysvDAqIFFrJKdBUEh2+6wEHUC9/xU3fJ8hS 6Jfw== X-Gm-Message-State: AOAM533ucsaCtTUE+Xt5dtrDSqPLNzAl2Wnmx6Z3SpfrCgtAnxDPtPF3 TGHXWOO20M5oPiMqrMw9b3uIZ0ricMc= X-Google-Smtp-Source: ABdhPJxg/0HDfAYFILQxyLLOPKPhwzLczlhmM7Mr4Bao7uCuBTs4DtcedrTrPY6pcU/o+PSoVxVu2A== X-Received: by 2002:a17:90b:3114:: with SMTP id gc20mr8471985pjb.233.1595409532898; Wed, 22 Jul 2020 02:18:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper Date: Wed, 22 Jul 2020 17:15:42 +0800 Message-Id: <20200722091641.8834-20-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang For floating-point operations, the scalar can be taken from a scalar f register. If FLEN > SEW, the value in the f registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the f register are used, else the canonical NaN value is used. Add helper to generate the correspond NaN-boxed value or the SEW-bit canonical NaN for floating-point operations. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index acc298219d..3cbd66a887 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1150,3 +1150,5 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr= , env, i32) DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_3(narrower_nanbox_fpr, i64, i64, i32, env) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 83e317c500..fb689ab3f9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3207,6 +3207,38 @@ GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl) /* *** Vector Float Point Arithmetic Instructions */ + +/* + * For SEW < FLEN, + * if f is not correctly NaN-boxed for SEW bits, + * canonical SEW-bit NaN is returned. + * Otherwise, original f is returned. + */ +static uint64_t narrower_nanbox_fpr(uint64_t f, uint32_t sew, float_status= *s) +{ + uint64_t mask =3D MAKE_64BIT_MASK(sew, 64 - sew); + if ((f & mask) =3D=3D mask) { + return f; + } else { + switch (sew) { + case 16: + return float16_default_nan(s); + case 32: + return float32_default_nan(s); + case 64: + return float64_default_nan(s); + default: + g_assert_not_reached(); + } + } +} + +uint64_t HELPER(narrower_nanbox_fpr)(uint64_t f, uint32_t sew, + CPURISCVState *env) +{ + return narrower_nanbox_fpr(f, sew, &env->fp_status); +} + /* Vector Single-Width Floating-Point Add/Subtract Instructions */ #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410137; cv=none; d=zohomail.com; s=zohoarc; b=YCCnVExwRQZd1SP5c7840ZyQGU55Yxdt+D9WA0Sa3m4Q9DuO/Krm0UYu/haDuQBq7cisHlXeXjFmVkzew9K6jLFzatYtHsgzCBqugqaDHKr/bSv3rQNeS2yTlBZXynv8Jr4bEDxolqsnCMd2TTvOGhhAU90uv7vWUj+FvSBE5QY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410137; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=6l7ajT+KNolo0CGKboLF/OzzmhcDECUMbbw6mVvJ14o=; b=VepZENY6uvldzqqPTlyzqb7AX+LTBW8IUk1CIyIJ/hDEFIR78jXKo5661VrEG8cPszlejMBxusPfWciw/k5eu1cqs0JhDhkz+m3B2nzxpQEpPJRfeVe5QOcmEF59BjGt/9r0mM0YUsn7Oz23nwMle2GmsmoS3U8LpV69evBOkyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410137987776.1355658675068; Wed, 22 Jul 2020 02:28:57 -0700 (PDT) Received: from localhost ([::1]:55334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB3Y-000320-Id for importer@patchew.org; Wed, 22 Jul 2020 05:28:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAtx-0000Gg-CM for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:01 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:46534) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAtu-0005W2-Ip for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:01 -0400 Received: by mail-pg1-x542.google.com with SMTP id s189so857282pgc.13 for ; Wed, 22 Jul 2020 02:18:58 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6l7ajT+KNolo0CGKboLF/OzzmhcDECUMbbw6mVvJ14o=; b=KOZSJwebz0Y7RyEt60irDwlHYeE/gcbbE7SXN5eHqWuXCJSNftu/iNDsi736pLa5f4 tA9ui0lpHBgYTt0GayuT8uCGaSHhhTPLxMmVC71dJx5Y7DylYc5AR1SHLryYbxXd4gVY aSELJivstDPO65LBIg79Un4YuL465Cv0lNSsbzKpjVfae1wCFAuUnEbKWHgC0eZj8kl+ yb/203ksDEwuXgbGIY0KJBwUSeMQdbyITB8TFu+Y0oomau3CcFtymifFzzoNHOzphkP6 PzWhmGiATCjnFSwmVQg4dya0dRwnVotJvp4VAP50Wfyqj3Jzd4oNzclO8GbhhDP55AXi 5gZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6l7ajT+KNolo0CGKboLF/OzzmhcDECUMbbw6mVvJ14o=; b=bJqyy8xc09MsTZ2fm0D8wcu7CeKrRmwe7JaC9ViNBxJRWQAXJFzOBzUepkdLzyeFYB rhXcbKlNTx+LsfhL2SO/9VG/7l7znO8lAFMzhQVFQO0zawqMwmLVIu0PtHxYwDewtVQn FdI73aCXk9ST6fYTZsUVGOVJEoZjS7nU6z4Jc1dbwLc+625x4gAcUklJl5CArDx9VdqC FB8OTytHeTuWmbsIjkqKALEpioRJRp40IFdWn2a6071tltCLIZGKL9cQKkjzi4baw0q2 kmktI6NAk7Vwu18PsyxU7ZC6VkiDVVLbWuvWSSTOxyHs6myGraY8vATTvtpkUiBXaX9R c3Vg== X-Gm-Message-State: AOAM533IBfD7/EE9RJv6InUrUKFD95TUeUtj6w9KJQqrK7qoz8isKdt1 BY54kevQD/5GKeOHHR9Zrne59bX52tQ= X-Google-Smtp-Source: ABdhPJyOhIcggfbs5DsF5MgqfWnXsbLbJibleSVTqSJRw3v+NVRiIQFp5l6QX4Sg7QOR+48mHaObQg== X-Received: by 2002:a62:1782:: with SMTP id 124mr26899231pfx.204.1595409537051; Wed, 22 Jul 2020 02:18:57 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans Date: Wed, 22 Jul 2020 17:15:43 +0800 Message-Id: <20200722091641.8834-21-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang If SEW < FLEN, call narrower_nanbox_fpr helper to generate the correspond NaN-boxed value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 22b4e11a20..85738ba4f7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2196,7 +2196,18 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, u= int32_t vs2, tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + if ((s->sew < MO_64 && has_ext(s, RVD)) || + (s->sew < MO_32)) { + /* SEW < FLEN */ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i32 sew =3D tcg_const_i32(1 << (s->sew + 3)); + gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[rs1], sew, cpu_env); + fn(dest, mask, t1, src2, cpu_env, desc); + tcg_temp_free_i64(t1); + tcg_temp_free_i32(sew); + } else { + fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + } =20 tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410230; cv=none; d=zohomail.com; s=zohoarc; b=GaBTO5Cq2Uex20jnI4TNxzzLKRC0Q2VzflhfM+KuRLY+/5gqkNsCaVuw51eHSSVK42u5BoNeS1v/dhvTHtOBQ6A2jq5KUvVPArTg8BVzNumNwefja15mYbGO1fy0KjXCkmiJLB+OyjPW5BXmJRqREqyDPThpaVnv2y6jZtcxveE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410230; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=lVeIL6sco3ONh+Bbp+QoLOvs2rU2KjxsD48epcvi0xM=; b=JM4OXs93iSdxnOXHsZyHmOvSLHgs/8HOD1XvGl4aQBXVjeuRQ0eMjCaXTUHk9L3veXpzrLImNDdZYef1XnHNZ2tbq1Wzmv7GnrFXWBcGtROLUvfDtCFkB9Ikuj2TElwj0Yo2RaexatXn91EVxSVvrjzwiRQYKWEkTJAF4hKbIrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159541023063391.04371099121067; Wed, 22 Jul 2020 02:30:30 -0700 (PDT) Received: from localhost ([::1]:35392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB53-0006JG-DY for importer@patchew.org; Wed, 22 Jul 2020 05:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAu1-0000Rf-Ll for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:05 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:45411) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAtz-0005Wb-3d for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:05 -0400 Received: by mail-pg1-x543.google.com with SMTP id l63so858633pge.12 for ; Wed, 22 Jul 2020 02:19:02 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 12 ++++++++---- target/riscv/vector_helper.c | 10 +++++++++- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 85738ba4f7..ca2ae59bb3 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -98,8 +98,10 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *= a) s2 =3D tcg_temp_new(); dst =3D tcg_temp_new(); =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { + if (a->rd =3D=3D 0 && a->rs1 =3D=3D 0) { + s1 =3D tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_const_tl(RV_VLEN_MAX); } else { @@ -131,8 +133,10 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetv= li *a) s2 =3D tcg_const_tl(a->zimm); dst =3D tcg_temp_new(); =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { + if (a->rd =3D=3D 0 && a->rs1 =3D=3D 0) { + s1 =3D tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_const_tl(RV_VLEN_MAX); } else { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fb689ab3f9..9320eeabfd 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -36,7 +36,15 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, bool vill =3D FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { + uint64_t lmul =3D (FIELD_EX64(s2, VTYPE, VFLMUL) << 2) + | FIELD_EX64(s2, VTYPE, VLMUL); + float vflmul =3D flmul_table[lmul]; + + if ((sew > cpu->cfg.elen) + || vill + || vflmul < ((float)sew / cpu->cfg.elen) + || (ediv !=3D 0) + || (reserved !=3D 0)) { /* only set vill bit. */ env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); env->vl =3D 0; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410360; cv=none; d=zohomail.com; s=zohoarc; b=i3mP80ZJhsUfloSUyBsRVhka1OmoUgLXFhTjfggNtlk9j3Eo8c3gvW9cS5pdTbYMP8CifmAwv2DV7KLff+Og0rvCc77XzYxhsYLqh/9R4rc2L+2sx/zFDJ0WEfHxKWGENj5OiwH9z6C3gQP3BAbK8+1O8Q6DEvJaHSrH+xcsRzw= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 129 +++----------- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 214 +++++++++++------------- target/riscv/vector_helper.c | 175 +++++-------------- 4 files changed, 184 insertions(+), 377 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3cbd66a887..db479f92cf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -84,111 +84,30 @@ DEF_HELPER_1(hyp_tlb_flush, void, env) =20 /* Vector functions */ DEF_HELPER_3(vsetvl, tl, env, tl, tl) -DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bdd8563067..012c844f60 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -229,13 +229,26 @@ hfence_vvma 0010001 ..... ..... 000 00000 1110011 @= hfence_vvma # *** RV32V Extension *** =20 # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm -vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm -vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +# Vector unit-stride load/store insns. +vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm +vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm +vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm +vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm +vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm +vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm +vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm + +# Vector strided insns. +vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm +vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm +vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm +vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm +vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm +vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm +vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm +vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm + vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm @@ -243,22 +256,6 @@ vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2= _nfvm vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm -vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm -vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm -vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm - -vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm -vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm -vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm -vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm -vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm -vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm -vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm -vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm -vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm -vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm -vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm =20 vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index ca2ae59bb3..d49891ad26 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -164,8 +164,42 @@ static uint32_t vreg_ofs(DisasContext *s, int reg) /* check functions */ =20 /* - * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. - * So RVV is also be checked in this function. + * Vector unit-stride, strided, unit-stride segment, strided segment + * store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <=3D EMUL <=3D 8. (Section 7.3) + * 2. Destination vector register number is multiples of EMUL. + * (Section 3.3.2, 7.3) + * 3. The EMUL setting must be such that EMUL * NFIELDS =E2=89=A4 8. (Se= ction 7.8) + * 4. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) + */ +static bool vext_check_store(DisasContext *s, int vd, int nf) +{ + uint32_t emul_r =3D s->emul < 1 ? 1 : s->emul; + return (s->emul >=3D 0.125 && s->emul <=3D 8) && + require_align(vd, s->emul) && + ((nf * emul_r) <=3D (NVPR / 4) && + (vd + nf * emul_r) <=3D NVPR); +} + +/* + * Vector unit-stride, strided, unit-stride segment, strided segment + * load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_check_load(DisasContext *s, int vd, int nf, int vm) +{ + return vext_check_store(s, vd, nf) && require_vm(vm, vd); +} + */ static bool vext_check_isa_ill(DisasContext *s) { @@ -432,13 +466,15 @@ static bool vext_check_isa_ill(DisasContext *s) } =20 /* common translation macro */ -#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ -{ \ - if (CHECK(s, a)) { \ - return OP(s, a, SEQ); \ - } \ - return false; \ +#define GEN_VEXT_TRANS(NAME, EEW, SEQ, ARGTYPE, OP, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ +{ \ + s->eew =3D EEW; \ + s->emul =3D (float)EEW / (1 << (s->sew + 3)) * s->flmul; \ + if (CHECK(s, a)) { \ + return OP(s, a, SEQ); \ + } \ + return false; \ } =20 /* @@ -492,40 +528,16 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, = uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][7][4] =3D { + static gen_helper_ldst_us * const fns[2][4] =3D { /* masked unit stride load */ - { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask, - gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask }, - { NULL, gen_helper_vlh_v_h_mask, - gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask }, - { NULL, NULL, - gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask }, - { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask, - gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask }, - { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask, - gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask }, - { NULL, gen_helper_vlhu_v_h_mask, - gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask }, - { NULL, NULL, - gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } }, + { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask, + gen_helper_vle32_v_mask, gen_helper_vle64_v_mask }, /* unmasked unit stride load */ - { { gen_helper_vlb_v_b, gen_helper_vlb_v_h, - gen_helper_vlb_v_w, gen_helper_vlb_v_d }, - { NULL, gen_helper_vlh_v_h, - gen_helper_vlh_v_w, gen_helper_vlh_v_d }, - { NULL, NULL, - gen_helper_vlw_v_w, gen_helper_vlw_v_d }, - { gen_helper_vle_v_b, gen_helper_vle_v_h, - gen_helper_vle_v_w, gen_helper_vle_v_d }, - { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h, - gen_helper_vlbu_v_w, gen_helper_vlbu_v_d }, - { NULL, gen_helper_vlhu_v_h, - gen_helper_vlhu_v_w, gen_helper_vlhu_v_d }, - { NULL, NULL, - gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } } + { gen_helper_vle8_v, gen_helper_vle16_v, + gen_helper_vle32_v, gen_helper_vle64_v } }; =20 - fn =3D fns[a->vm][seq][s->sew]; + fn =3D fns[a->vm][seq]; if (fn =3D=3D NULL) { return false; } @@ -541,46 +553,30 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, = uint8_t seq) =20 static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm); } =20 -GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle8_v, 8, 0, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle16_v, 16, 1, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle32_v, 32, 2, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle64_v, 64, 3, r2nfvm, ld_us_op, ld_us_check) =20 static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][4][4] =3D { - /* masked unit stride load and store */ - { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask, - gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask }, - { NULL, gen_helper_vsh_v_h_mask, - gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask }, - { NULL, NULL, - gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask }, - { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask, - gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } }, + static gen_helper_ldst_us * const fns[2][4] =3D { + /* masked unit stride store */ + { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask, + gen_helper_vse32_v_mask, gen_helper_vse64_v_mask }, /* unmasked unit stride store */ - { { gen_helper_vsb_v_b, gen_helper_vsb_v_h, - gen_helper_vsb_v_w, gen_helper_vsb_v_d }, - { NULL, gen_helper_vsh_v_h, - gen_helper_vsh_v_w, gen_helper_vsh_v_d }, - { NULL, NULL, - gen_helper_vsw_v_w, gen_helper_vsw_v_d }, - { gen_helper_vse_v_b, gen_helper_vse_v_h, - gen_helper_vse_v_w, gen_helper_vse_v_d } } + { gen_helper_vse8_v, gen_helper_vse16_v, + gen_helper_vse32_v, gen_helper_vse64_v } }; =20 - fn =3D fns[a->vm][seq][s->sew]; + fn =3D fns[a->vm][seq]; if (fn =3D=3D NULL) { return false; } @@ -596,15 +592,15 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, = uint8_t seq) =20 static bool st_us_check(DisasContext *s, arg_r2nfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf); } =20 -GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse8_v, 8, 0, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse16_v, 16, 1, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse32_v, 32, 2, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse64_v, 64, 3, r2nfvm, st_us_op, st_us_check) =20 /* *** stride load and store @@ -652,24 +648,12 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *= a, uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[7][4] =3D { - { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h, - gen_helper_vlsb_v_w, gen_helper_vlsb_v_d }, - { NULL, gen_helper_vlsh_v_h, - gen_helper_vlsh_v_w, gen_helper_vlsh_v_d }, - { NULL, NULL, - gen_helper_vlsw_v_w, gen_helper_vlsw_v_d }, - { gen_helper_vlse_v_b, gen_helper_vlse_v_h, - gen_helper_vlse_v_w, gen_helper_vlse_v_d }, - { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h, - gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d }, - { NULL, gen_helper_vlshu_v_h, - gen_helper_vlshu_v_w, gen_helper_vlshu_v_d }, - { NULL, NULL, - gen_helper_vlswu_v_w, gen_helper_vlswu_v_d }, + static gen_helper_ldst_stride * const fns[4] =3D { + gen_helper_vlse8_v, gen_helper_vlse16_v, + gen_helper_vlse32_v, gen_helper_vlse64_v }; =20 - fn =3D fns[seq][s->sew]; + fn =3D fns[seq]; if (fn =3D=3D NULL) { return false; } @@ -685,34 +669,24 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *= a, uint8_t seq) =20 static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm); } =20 -GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse8_v, 8, 0, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse16_v, 16, 1, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse32_v, 32, 2, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse64_v, 64, 3, rnfvm, ld_stride_op, ld_stride_check) =20 static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[4][4] =3D { + static gen_helper_ldst_stride * const fns[4] =3D { /* masked stride store */ - { gen_helper_vssb_v_b, gen_helper_vssb_v_h, - gen_helper_vssb_v_w, gen_helper_vssb_v_d }, - { NULL, gen_helper_vssh_v_h, - gen_helper_vssh_v_w, gen_helper_vssh_v_d }, - { NULL, NULL, - gen_helper_vssw_v_w, gen_helper_vssw_v_d }, - { gen_helper_vsse_v_b, gen_helper_vsse_v_h, - gen_helper_vsse_v_w, gen_helper_vsse_v_d } + gen_helper_vsse8_v, gen_helper_vsse16_v, + gen_helper_vsse32_v, gen_helper_vsse64_v }; =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -721,7 +695,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t seq) data =3D FIELD_DP32(data, VDATA, VTA, s->vta); data =3D FIELD_DP32(data, VDATA, VMA, s->vma); data =3D FIELD_DP32(data, VDATA, NF, a->nf); - fn =3D fns[seq][s->sew]; + fn =3D fns[seq]; if (fn =3D=3D NULL) { return false; } @@ -731,15 +705,15 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *= a, uint8_t seq) =20 static bool st_stride_check(DisasContext *s, arg_rnfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf); } =20 -GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse8_v, 8, 0, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse16_v, 16, 1, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse32_v, 32, 2, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse64_v, 64, 3, rnfvm, st_stride_op, st_stride_check) =20 /* *** index load and store diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9320eeabfd..74a22fb607 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -249,38 +249,20 @@ typedef void vext_ldst_elem_fn(CPURISCVState *env, ta= rget_ulong addr, typedef void clear_fn(void *vd, uint32_t vta, uint32_t idx, uint32_t cnt, uint32_t tot); =20 -#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ +#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr)\ { \ - MTYPE data; \ + ETYPE data; \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ data =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ *cur =3D data; \ } \ =20 -GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb) -GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb) -GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb) -GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw) -GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw) -GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl) -GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq) -GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub) -GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub) -GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub) -GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw) -GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw) -GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl) +GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -290,15 +272,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, = \ cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } =20 -GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb) -GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb) -GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb) -GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb) -GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw) -GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw) -GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw) -GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl) -GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl) GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) @@ -312,8 +285,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); @@ -325,7 +297,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, base + stride * i, nf * msz, ra, access_type); + probe_pages(env, base + stride * i, nf * esz, ra, access_type); } /* do real access */ for (i =3D 0; i < env->vl; i++) { @@ -334,7 +306,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - target_ulong addr =3D base + stride * i + k * msz; + target_ulong addr =3D base + stride * i + k * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -348,64 +320,37 @@ vext_ldst_stride(void *vd, void *v0, target_ulong bas= e, } } =20 -#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN, CLEAR_FN) \ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + CLEAR_FN, sizeof(ETYPE), \ GETPC(), MMU_DATA_LOAD); \ } =20 -GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq) - -#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \ +GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b, clearb) +GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h, clearh) +GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w, clearl) +GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d, clearq) + +#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ + NULL, sizeof(ETYPE), \ GETPC(), MMU_DATA_STORE); \ } =20 -GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b) -GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b) -GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) +GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) +GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h) +GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) +GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) =20 /* *** unit-stride: access elements stored contiguously in memory @@ -415,8 +360,7 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); @@ -424,12 +368,12 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVSta= te *env, uint32_t desc, uint32_t vta =3D vext_vta(desc); =20 /* probe every access */ - probe_pages(env, base, env->vl * nf * msz, ra, access_type); + probe_pages(env, base, env->vl * nf * esz, ra, access_type); /* load bytes from guest memory */ for (i =3D 0; i < env->vl; i++) { k =3D 0; while (k < nf) { - target_ulong addr =3D base + (i * nf + k) * msz; + target_ulong addr =3D base + (i * nf + k) * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -448,13 +392,13 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVSta= te *env, uint32_t desc, * stride =3D NF * sizeof (MTYPE) */ =20 -#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN, CLEAR_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride =3D vext_nf(desc) * sizeof(MTYPE); \ + uint32_t stride =3D vext_nf(desc) * sizeof(ETYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + CLEAR_FN, sizeof(ETYPE), \ GETPC(), MMU_DATA_LOAD); \ } \ \ @@ -462,39 +406,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \ -} - -GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq) - -#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ +} + +GEN_VEXT_LD_US(vle8_v, int8_t, lde_b, clearb) +GEN_VEXT_LD_US(vle16_v, int16_t, lde_h, clearh) +GEN_VEXT_LD_US(vle32_v, int32_t, lde_w, clearl) +GEN_VEXT_LD_US(vle64_v, int64_t, lde_d, clearq) + +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride =3D vext_nf(desc) * sizeof(MTYPE); \ + uint32_t stride =3D vext_nf(desc) * sizeof(ETYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ + NULL, sizeof(ETYPE), \ GETPC(), MMU_DATA_STORE); \ } \ \ @@ -502,22 +428,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\ -} - -GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b) -GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b) -GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d) + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ +} + +GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) +GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) +GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) +GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) =20 /* *** index: access vector element from indexed memory --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410448; cv=none; d=zohomail.com; s=zohoarc; b=dik89zGznDSS1AVxMri3amdi83FSkRMcGNeke4cR5aFJ+OdTsNBwmDFDwv/oZpeJl3skfLk+5RopzpNeMON/AVbOY0qPnEthom3Xb0XsniQ85Neeuj7AHu0QzRmXcqrjVtDY+VBIcpEOYevxCnf6FrrxXOJc4ye4p00+WCR9vA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410448; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 67 +++++---- target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.inc.c | 177 +++++++++++++++++------- target/riscv/vector_helper.c | 84 ++++++----- 4 files changed, 206 insertions(+), 143 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index db479f92cf..4890b2aa02 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -108,41 +108,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i3= 2) DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 012c844f60..46542d162e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -257,18 +257,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r= 2_nfvm vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm =20 -vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm -vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm -vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm +# Vector indexed load insns. +vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm +vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm +vlxei32_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm +vlxei64_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm + # Vector ordered-indexed and unordered-indexed store insns. -vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm -vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm -vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm -vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm +vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm +vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm +vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm +vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm =20 #*** Vector AMO operations are encoded under the standard AMO major opcode= *** vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index d49891ad26..b902462741 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -200,12 +200,69 @@ static bool vext_check_load(DisasContext *s, int vd, = int nf, int vm) return vext_check_store(s, vd, nf) && require_vm(vm, vd); } =20 +/* + * Vector indexed, indexed segment store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <=3D EMUL <=3D 8. (Section 7.3) + * 2. Index vector register number is multiples of EMUL. + * (Section 3.3.2, 7.3) + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.3.2, 7.3) + * 4. The EMUL setting must be such that EMUL * NFIELDS =E2=89=A4 8. (Se= ction 7.8) + * 5. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) */ -static bool vext_check_isa_ill(DisasContext *s) +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf) { - return !s->vill; + uint32_t flmul_r =3D s->flmul < 1 ? 1 : s->flmul; + return (s->emul >=3D 0.125 && s->emul <=3D 8) && + require_align(vs2, s->emul) && + require_align(vd, s->flmul) && + ((nf * flmul_r) <=3D (NVPR / 4) && + (vd + nf * flmul_r) <=3D NVPR); +} + +/* + * Vector indexed, indexed segment load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 3. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 4. Destination vector register groups cannot overlap + * the source vector register (vs2) group for + * indexed segment load instructions. (Section 7.8.3) + */ +static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, + int nf, int vm) +{ + bool ret =3D vext_check_st_index(s, vd, vs2, nf) && + require_vm(vm, vd); + if (s->eew > (1 << (s->sew + 3))) { + if (vd !=3D vs2) { + ret &=3D require_noover(vd, s->flmul, vs2, s->emul); + } + } else if (s->eew < (1 << (s->sew + 3))) { + if (s->emul < 1) { + ret &=3D require_noover(vd, s->flmul, vs2, s->emul); + } else { + ret &=3D require_noover_widen(vd, s->flmul, vs2, s->emul); + } + } + if (nf > 1) { + ret &=3D (require_noover(vd, s->flmul, vs2, s->emul) && + require_noover(vd, nf, vs2, 1)); + } + return ret; } =20 + /* * Check function for vector instruction with format: * single-width result and single-width sources (SEW =3D SEW op SEW) @@ -761,27 +818,34 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_index *fn; - static gen_helper_ldst_index * const fns[7][4] =3D { - { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h, - gen_helper_vlxb_v_w, gen_helper_vlxb_v_d }, - { NULL, gen_helper_vlxh_v_h, - gen_helper_vlxh_v_w, gen_helper_vlxh_v_d }, - { NULL, NULL, - gen_helper_vlxw_v_w, gen_helper_vlxw_v_d }, - { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h, - gen_helper_vlxe_v_w, gen_helper_vlxe_v_d }, - { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h, - gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d }, - { NULL, gen_helper_vlxhu_v_h, - gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d }, - { NULL, NULL, - gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d }, + static gen_helper_ldst_index * const fns[4][4] =3D { + /* + * offset vector register group EEW =3D 8, + * data vector register group EEW =3D SEW + */ + { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v, + gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v }, + /* + * offset vector register group EEW =3D 16, + * data vector register group EEW =3D SEW + */ + { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v, + gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v }, + /* + * offset vector register group EEW =3D 32, + * data vector register group EEW =3D SEW + */ + { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v, + gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v }, + /* + * offset vector register group EEW =3D 64, + * data vector register group EEW =3D SEW + */ + { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v, + gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v } }; =20 - fn =3D fns[seq][s->sew]; - if (fn =3D=3D NULL) { - return false; - } + fn =3D fns[seq][s->sew]; =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -794,40 +858,48 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t seq) =20 static bool ld_index_check(DisasContext *s, arg_rnfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm); } =20 -GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei8_v, 8, 0, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei16_v, 16, 1, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei32_v, 32, 2, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei64_v, 64, 3, rnfvm, ld_index_op, ld_index_check) =20 static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) { uint32_t data =3D 0; gen_helper_ldst_index *fn; static gen_helper_ldst_index * const fns[4][4] =3D { - { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h, - gen_helper_vsxb_v_w, gen_helper_vsxb_v_d }, - { NULL, gen_helper_vsxh_v_h, - gen_helper_vsxh_v_w, gen_helper_vsxh_v_d }, - { NULL, NULL, - gen_helper_vsxw_v_w, gen_helper_vsxw_v_d }, - { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h, - gen_helper_vsxe_v_w, gen_helper_vsxe_v_d } + /* + * offset vector register group EEW =3D 8, + * data vector register group EEW =3D SEW + */ + { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v, + gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v }, + /* + * offset vector register group EEW =3D 16, + * data vector register group EEW =3D SEW + */ + { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v, + gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v }, + /* + * offset vector register group EEW =3D 32, + * data vector register group EEW =3D SEW + */ + { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v, + gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v }, + /* + * offset vector register group EEW =3D 64, + * data vector register group EEW =3D SEW + */ + { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v, + gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v } }; =20 - fn =3D fns[seq][s->sew]; - if (fn =3D=3D NULL) { - return false; - } + fn =3D fns[seq][s->sew]; =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -840,16 +912,15 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t seq) =20 static bool st_index_check(DisasContext *s, arg_rnfvm* a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_st_index(s, a->rd, a->rs2, a->nf); } =20 -GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei8_v, 8, 0, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei16_v, 16, 1, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei32_v, 32, 2, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei64_v, 64, 3, rnfvm, st_index_op, st_index_check) =20 /* *** unit stride fault-only-first load diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 74a22fb607..13634be66a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -459,8 +459,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_ldst_elem_fn *ldst_elem, - clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, + clear_fn *clear_elem, uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; @@ -474,7 +473,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, + probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra, access_type); } /* load bytes from guest memory */ @@ -484,7 +483,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - abi_ptr addr =3D get_index_addr(base, i, vs2) + k * msz; + abi_ptr addr =3D get_index_addr(base, i, vs2) + k * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -498,60 +497,57 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } } =20 -#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN)= \ +#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) = \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, = \ void *vs2, CPURISCVState *env, uint32_t desc) = \ { = \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, = \ - LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), = \ + LOAD_FN, CLEAR_FN, sizeof(ETYPE), = \ GETPC(), MMU_DATA_LOAD); = \ } =20 -GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb) -GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh) -GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl) -GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq) -GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh) -GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl) -GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq) -GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl) -GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq) -GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb) -GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh) -GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl) -GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq) -GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb) -GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh) -GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl) -GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq) -GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh) -GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl) -GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq) -GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl) -GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq) - -#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ +GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b, clearb) +GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h, clearh) +GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w, clearl) +GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d, clearq) +GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b, clearb) +GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h, clearh) +GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w, clearl) +GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d, clearq) +GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b, clearb) +GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h, clearh) +GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w, clearl) +GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d, clearq) +GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b, clearb) +GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h, clearh) +GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w, clearl) +GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d, clearq) + +#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\ + STORE_FN, NULL, sizeof(ETYPE), \ GETPC(), MMU_DATA_STORE); \ } =20 -GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b) -GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h) -GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w) -GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d) -GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h) -GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w) -GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d) -GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w) -GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d) -GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b) -GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h) -GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w) -GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d) +GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b) +GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h) +GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w) +GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d) +GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b) +GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h) +GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w) +GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d) +GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b) +GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h) +GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w) +GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d) +GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b) +GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h) +GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) +GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) =20 /* *** unit-stride fault-only-fisrt load instructions --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t2sySwVAYzBgFbUWGNCph7loGGmEs8LojJHT2BEgias=; b=XXyGIhqrBdD6fi+0eDuLGFcejzSU/BUvO8w67CO2ZV+VSjnMxRAC6v1eGRgqsFM3q2 QfEqlgmhKR0QAyq6QGNguQjZoHqEe6L0Y4CrAtRo6EHJ28JdwTWtJvefYeN/y2CwDTgb tISHqjAcOXhp6n0ehXGORwGqyHRvnkoSL6/pj2pCfG8R0LRFKG3DXl/kRDk+mA0xsLq8 k2Go2c4ct0AySLqPSJmwWJPMh5cMlTg9B1R55xFNEI3XYSJgnBGkYF+0o1AL0dCr/omG Yd5a51CMBpxkoW5mVp9BZeiadsgdFz+zqr5a+kK+iez9kM0AOJ3PJOkdQ4JgwqTZHqN7 ya/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t2sySwVAYzBgFbUWGNCph7loGGmEs8LojJHT2BEgias=; b=um9JhcwEzi3g1r8T0nLv1GQTF/gnrM3uAoG6z8iH/v7/4STh5VvXfOqBR+BJKw68bt oeS9SH+biyEMWMO5te+po688iMTpVkWxwmuvaIkFZ8FxR995sd7MTcSdXqTkcvd1UsCB nFjpOLfqjM69oGCzo6AVAkeb/fxNs7yx1L+WtActg+fl/SK6lzEagzv6Gyd625RN23rE heVwtJq9F7Mfpy32tU3DLE5szSpt7ZoFBm1OWFHS7L66FNyLjVEc7o5GVJCku5+sVr02 V2/z1KTfYmCBb1k1jQFFlD0SG44JTykUS1JXtB2GLnQr1YapGEiadGmjkF/VV/0sYUe9 UH5w== X-Gm-Message-State: AOAM530Ve+kymh7Tqy8ldAv1qInYpVMR1ed/qhsLo1Xaq3fOG+nB93Ae on7IcAl1VKckt8IjVxXBs9XolZZirRQ= X-Google-Smtp-Source: ABdhPJxs7SuZ07/HcM+uwTVeCJ1zCs2ziXosnUbE1NJq5LdHXr/h1wnk8FFojGZYZO4cOY20cxMBpQ== X-Received: by 2002:a17:90a:8c91:: with SMTP id b17mr9343086pjo.74.1595409555109; Wed, 22 Jul 2020 02:19:15 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns Date: Wed, 22 Jul 2020 17:15:47 +0800 Message-Id: <20200722091641.8834-25-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 13634be66a..1c4aba21c6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -449,10 +449,10 @@ static target_ulong NAME(target_ulong base, = \ return (base + *((ETYPE *)vs2 + H(idx))); \ } =20 -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2) -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4) -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8) +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1) +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2) +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4) +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8) =20 static inline void vext_ldst_index(void *vd, void *v0, target_ulong base, --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410213; cv=none; d=zohomail.com; s=zohoarc; b=EAXpIKHQYNX2cVnknhCAs3KT8NXlBQEfqnVCZ65bnuXI5qLYljUTXigUJi4dOzjahL9W3FMYnWJZ4ch0yZqU+VOr4Hh1bD+L0TIVAm4zcHYHD7zTM3Wj4uP8ouUd6A6Y/ZtTHYiPERIOAkBHeF0CTjy2izCR2JlR9bvRGlBTSjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410213; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Zaz1YKMLbjDLooDJEehaxTfgg40pu4GNpEuVJmdgSH4=; b=VJ5w7EGa6vgiWP6AHl0a0v63Ulvl6r44yk+BM1iRR2enB2Cvv4W7swaZemdBCcjYct3Zww1pUh1GpUAkoP/Pzh+JBa/ZEwIQvTU40d2rfbf+iGpjftSx6GSz+6ZtjOTTaLFKO8wWH8vbV6qI9eNjM0tKhB7DJC/lkxziMDIWdC8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410213557712.8483238261016; Wed, 22 Jul 2020 02:30:13 -0700 (PDT) Received: from localhost ([::1]:33786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB4m-0005g5-4z for importer@patchew.org; Wed, 22 Jul 2020 05:30:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAuK-00012J-Lv for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:24 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:36037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAuI-0005Yk-2m for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:24 -0400 Received: by mail-pg1-x52d.google.com with SMTP id p3so880504pgh.3 for ; Wed, 22 Jul 2020 02:19:21 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 27 +++--------- target/riscv/insn32.decode | 14 +++---- target/riscv/insn_trans/trans_rvv.inc.c | 31 ++++---------- target/riscv/vector_helper.c | 56 +++++++++---------------- 4 files changed, 38 insertions(+), 90 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4890b2aa02..db032fd47f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -140,28 +140,11 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) + #ifdef TARGET_RISCV64 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 46542d162e..b0aaa186b8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -249,14 +249,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r= _nfvm vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm =20 -vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm -vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm - # Vector indexed load insns. vlxei8_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm vlxei16_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm @@ -269,6 +261,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 = @r_nfvm vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm =20 +# Vector unit-stride fault-only-first load insns. +vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm +vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm +vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm +vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm + #*** Vector AMO operations are encoded under the standard AMO major opcode= *** vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index b902462741..19c6866838 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -959,24 +959,12 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, u= int8_t seq) { uint32_t data =3D 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[7][4] =3D { - { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, - gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, - { NULL, gen_helper_vlhff_v_h, - gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, - { NULL, NULL, - gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, - { gen_helper_vleff_v_b, gen_helper_vleff_v_h, - gen_helper_vleff_v_w, gen_helper_vleff_v_d }, - { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, - gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, - { NULL, gen_helper_vlhuff_v_h, - gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, - { NULL, NULL, - gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } + static gen_helper_ldst_us * const fns[4] =3D { + gen_helper_vle8ff_v, gen_helper_vle16ff_v, + gen_helper_vle32ff_v, gen_helper_vle64ff_v }; =20 - fn =3D fns[seq][s->sew]; + fn =3D fns[seq]; if (fn =3D=3D NULL) { return false; } @@ -990,13 +978,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, u= int8_t seq) return ldff_trans(a->rd, a->rs1, data, fn, s); } =20 -GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle8ff_v, 8, 0, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check) =20 /* *** vector atomic operation diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1c4aba21c6..35ce006698 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -557,7 +557,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra) + uint32_t esz, uintptr_t ra) { void *host; uint32_t i, k, vl =3D 0; @@ -572,24 +572,24 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - addr =3D base + nf * i * msz; + addr =3D base + nf * i * esz; if (i =3D=3D 0) { - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); } else { /* if it triggers an exception, no need to check watchpoint */ - remain =3D nf * msz; + remain =3D nf * esz; while (remain > 0) { offset =3D -(addr | TARGET_PAGE_MASK); host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, nf * esz, PAGE_READ) < 0) { vl =3D i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); #endif } else { vl =3D i; @@ -614,7 +614,7 @@ ProbeSuccess: continue; } while (k < nf) { - target_ulong addr =3D base + (i * nf + k) * msz; + target_ulong addr =3D base + (i * nf + k) * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -629,36 +629,18 @@ ProbeSuccess: } } =20 -#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ -} - -GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq) +#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \ + sizeof(ETYPE), GETPC()); \ +} + +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b, clearb) +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh) +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl) +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq) =20 /* *** Vector AMO Operations (Zvamo) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410654; cv=none; d=zohomail.com; s=zohoarc; b=c9MTB92YgPnaTpyS3YlBDTtS14yNawHaYB4mrOqHenptfzhI2OfNs4uoPYqaQf27wLthzkqdaMlzSt1NcVDRV9oQUro3V9WponMCZZ8tqNXlYjznmpOGqw2ZE5GNWH/z1czVEPgOeHc0s3Y66dBLErL8judvB6QqF0s5Pne2q9Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410654; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=KVxDKWjVz4Zva3Fp7UMB08Qi7DJsUHimuZ64cCy4XnY=; b=KvR3VdYaB8Z8qTcw15J/qhMsPeR4V4vlOat9aOMlVPbANlDCMeU8en2mJ1d5xelvU4mr/8VpoUVpGjROaq0wTxVtum2oR8Ji3Rn1DXl0TWmk1WJXzoqc9KyCsZ5V3FF6zKs7HqwuDfiWqcMwPMa185pmWStksV9mbbfz3+5kg8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410654605781.2665747218624; Wed, 22 Jul 2020 02:37:34 -0700 (PDT) Received: from localhost ([::1]:42932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBBt-0003vC-9Y for importer@patchew.org; Wed, 22 Jul 2020 05:37:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAuR-0001M1-Ud for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:31 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:45293) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAuO-0005aS-Oz for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:31 -0400 Received: by mail-pl1-x62f.google.com with SMTP id k4so640086pld.12 for ; Wed, 22 Jul 2020 02:19:28 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 100 ++++++++--- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.inc.c | 212 +++++++++++++++------- target/riscv/vector_helper.c | 228 ++++++++++++++++-------- 5 files changed, 409 insertions(+), 185 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index db032fd47f..808f88fbeb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -145,36 +145,80 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) =20 +DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei32_64_v, void, ptr, ptr, tl, ptr, env, i32) #ifdef TARGET_RISCV64 -DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuei64_64_v, void, ptr, ptr, tl, ptr, env, i32) #endif -DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32) - DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 86153d93fa..c3283a5530 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -58,15 +58,15 @@ amominu_d 11000 . . ..... ..... 011 ..... 0101111 @ato= m_st amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st =20 #*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoswapei64_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoaddei64_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoxorei64_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoandei64_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoorei64_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamominei64_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxei64_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamominuei64_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxuei64_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm =20 # *** RV64F Standard Extension (in addition to RV32F) *** fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b0aaa186b8..6a9cf6ad53 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -268,15 +268,33 @@ vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111= @r2_nfvm vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm =20 #*** Vector AMO operations are encoded under the standard AMO major opcode= *** -vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamoswapei32_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamoaddei8_v 00000 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamoaddei16_v 00000 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamoaddei32_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamoxorei8_v 00100 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamoxorei16_v 00100 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamoxorei32_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamoandei8_v 01100 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamoandei16_v 01100 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamoandei32_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamoorei8_v 01000 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamoorei16_v 01000 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamoorei32_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamominei8_v 10000 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamominei16_v 10000 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamominei32_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamomaxei8_v 10100 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamomaxei16_v 10100 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamomaxei32_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamominuei8_v 11000 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamominuei16_v 11000 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamominuei32_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm +vamomaxuei8_v 11100 . . ..... ..... 000 ..... 0101111 @r_wdvm +vamomaxuei16_v 11100 . . ..... ..... 101 ..... 0101111 @r_wdvm +vamomaxuei32_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm =20 # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 19c6866838..fb6d092539 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -262,6 +262,53 @@ static bool vext_check_ld_index(DisasContext *s, int v= d, int vs2, return ret; } =20 +/* + * Vector AMO check function. + * + * Rules to be checked here: + * 1. RVA must supported. + * 2. AMO can either operations on 64-bit (RV64 only) or 32-bit words + * in memory: + * For RV32: 32 <=3D SEW <=3D 32. + * For RV64: 32 <=3D SEW <=3D 64. + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.3.2, 8) + * 4. Address vector register number is multiples of EMUL. + * (Section 3.3.2, 8) + * 5. EMUL must within the range: 1/8 <=3D EMUL <=3D 8. (Section 7.3) + * 6. If wd =3D 1: + * 6.1. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 6.2. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + */ +static bool vext_check_amo(DisasContext *s, int vd, int vs2, + int wd, int vm) +{ + bool ret =3D has_ext(s, RVA) && + (1 << s->sew >=3D 4) && + (1 << s->sew <=3D sizeof(target_ulong)) && + require_align(vd, s->flmul) && + require_align(vs2, s->emul) && + (s->emul >=3D 0.125 && s->emul <=3D 8); + if (wd) { + ret &=3D require_vm(vm, vd); + if (s->eew > (1 << (s->sew + 3))) { + if (vd !=3D vs2) { + ret &=3D require_noover(vd, s->flmul, vs2, s->emul); + } + } else if (s->eew < (1 << (s->sew + 3))) { + if (s->emul < 1) { + ret &=3D require_noover(vd, s->flmul, vs2, s->emul); + } else { + ret &=3D require_noover_widen(vd, s->flmul, vs2, s->emul); + } + } + } + return ret; +} =20 /* * Check function for vector instruction with format: @@ -1026,38 +1073,48 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, u= int8_t seq) { uint32_t data =3D 0; gen_helper_amo *fn; - static gen_helper_amo *const fnsw[9] =3D { + static gen_helper_amo *const fns[27][2] =3D { /* no atomic operation */ - gen_helper_vamoswapw_v_w, - gen_helper_vamoaddw_v_w, - gen_helper_vamoxorw_v_w, - gen_helper_vamoandw_v_w, - gen_helper_vamoorw_v_w, - gen_helper_vamominw_v_w, - gen_helper_vamomaxw_v_w, - gen_helper_vamominuw_v_w, - gen_helper_vamomaxuw_v_w + { gen_helper_vamoswapei8_32_v, gen_helper_vamoswapei8_64_v }, + { gen_helper_vamoswapei16_32_v, gen_helper_vamoswapei16_64_v }, + { gen_helper_vamoswapei32_32_v, gen_helper_vamoswapei32_64_v }, + { gen_helper_vamoaddei8_32_v, gen_helper_vamoaddei8_64_v }, + { gen_helper_vamoaddei16_32_v, gen_helper_vamoaddei16_64_v }, + { gen_helper_vamoaddei32_32_v, gen_helper_vamoaddei32_64_v }, + { gen_helper_vamoxorei8_32_v, gen_helper_vamoxorei8_64_v }, + { gen_helper_vamoxorei16_32_v, gen_helper_vamoxorei16_64_v }, + { gen_helper_vamoxorei32_32_v, gen_helper_vamoxorei32_64_v }, + { gen_helper_vamoandei8_32_v, gen_helper_vamoandei8_64_v }, + { gen_helper_vamoandei16_32_v, gen_helper_vamoandei16_64_v }, + { gen_helper_vamoandei32_32_v, gen_helper_vamoandei32_64_v }, + { gen_helper_vamoorei8_32_v, gen_helper_vamoorei8_64_v }, + { gen_helper_vamoorei16_32_v, gen_helper_vamoorei16_64_v }, + { gen_helper_vamoorei32_32_v, gen_helper_vamoorei32_64_v }, + { gen_helper_vamominei8_32_v, gen_helper_vamominei8_64_v }, + { gen_helper_vamominei16_32_v, gen_helper_vamominei16_64_v }, + { gen_helper_vamominei32_32_v, gen_helper_vamominei32_64_v }, + { gen_helper_vamomaxei8_32_v, gen_helper_vamomaxei8_64_v }, + { gen_helper_vamomaxei16_32_v, gen_helper_vamomaxei16_64_v }, + { gen_helper_vamomaxei32_32_v, gen_helper_vamomaxei32_64_v }, + { gen_helper_vamominuei8_32_v, gen_helper_vamominuei8_64_v }, + { gen_helper_vamominuei16_32_v, gen_helper_vamominuei16_64_v }, + { gen_helper_vamominuei32_32_v, gen_helper_vamominuei32_64_v }, + { gen_helper_vamomaxuei8_32_v, gen_helper_vamomaxuei8_64_v }, + { gen_helper_vamomaxuei16_32_v, gen_helper_vamomaxuei16_64_v }, + { gen_helper_vamomaxuei32_32_v, gen_helper_vamomaxuei32_64_v } }; + #ifdef TARGET_RISCV64 - static gen_helper_amo *const fnsd[18] =3D { - gen_helper_vamoswapw_v_d, - gen_helper_vamoaddw_v_d, - gen_helper_vamoxorw_v_d, - gen_helper_vamoandw_v_d, - gen_helper_vamoorw_v_d, - gen_helper_vamominw_v_d, - gen_helper_vamomaxw_v_d, - gen_helper_vamominuw_v_d, - gen_helper_vamomaxuw_v_d, - gen_helper_vamoswapd_v_d, - gen_helper_vamoaddd_v_d, - gen_helper_vamoxord_v_d, - gen_helper_vamoandd_v_d, - gen_helper_vamoord_v_d, - gen_helper_vamomind_v_d, - gen_helper_vamomaxd_v_d, - gen_helper_vamominud_v_d, - gen_helper_vamomaxud_v_d + static gen_helper_amo *const fns64[9][2] =3D { + { gen_helper_vamoswapei64_32_v, gen_helper_vamoswapei64_64_v }, + { gen_helper_vamoaddei64_32_v, gen_helper_vamoaddei64_64_v }, + { gen_helper_vamoxorei64_32_v, gen_helper_vamoxorei64_64_v }, + { gen_helper_vamoandei64_32_v, gen_helper_vamoandei64_64_v }, + { gen_helper_vamoorei64_32_v, gen_helper_vamoorei64_64_v }, + { gen_helper_vamominei64_32_v, gen_helper_vamominei64_64_v }, + { gen_helper_vamomaxei64_32_v, gen_helper_vamomaxei64_64_v }, + { gen_helper_vamominuei64_32_v, gen_helper_vamominuei64_64_v }, + { gen_helper_vamomaxuei64_32_v, gen_helper_vamomaxuei64_64_v } }; #endif =20 @@ -1066,15 +1123,25 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, u= int8_t seq) s->base.is_jmp =3D DISAS_NORETURN; return true; } else { - if (s->sew =3D=3D 3) { + if (s->eew =3D=3D 64) { #ifdef TARGET_RISCV64 - fn =3D fnsd[seq]; + /* EEW =3D=3D 64. */ + fn =3D fns64[seq][s->sew - 2]; +#else + /* RV32 does not support EEW =3D 64 AMO insns. */ + g_assert_not_reached(); +#endif + } else if (s->sew =3D=3D 3) { +#ifdef TARGET_RISCV64 + /* EEW <=3D 32 && SEW =3D=3D 64. */ + fn =3D fns[seq][s->sew - 2]; #else /* Check done in amo_check(). */ g_assert_not_reached(); #endif } else { - fn =3D fnsw[seq]; + /* EEW <=3D 32 && SEW =3D=3D 32. */ + fn =3D fns[seq][s->sew - 2]; } } =20 @@ -1086,42 +1153,57 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, u= int8_t seq) data =3D FIELD_DP32(data, VDATA, WD, a->wd); return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); } -/* - * There are two rules check here. - * - * 1. SEW must be at least as wide as the AMO memory element size. - * - * 2. If SEW is greater than XLEN, an illegal instruction exception is rai= sed. - */ + + static bool amo_check(DisasContext *s, arg_rwdvm* a) { - return (!s->vill && has_ext(s, RVA) && - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <=3D sizeof(target_ulong)) && - ((1 << s->sew) >=3D 4)); -} - -GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_amo(s, a->rd, a->rs2, a->wd, a->vm); +} + +GEN_VEXT_TRANS(vamoswapei8_v, 8, 0, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoswapei16_v, 16, 1, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoswapei32_v, 32, 2, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddei8_v, 8, 3, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddei16_v, 16, 4, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddei32_v, 32, 5, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxorei8_v, 8, 6, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxorei16_v, 16, 7, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxorei32_v, 32, 8, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandei8_v, 8, 9, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandei16_v, 16, 10, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandei32_v, 32, 11, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoorei8_v, 8, 12, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoorei16_v, 16, 13, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoorei32_v, 32, 14, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominei8_v, 8, 15, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominei16_v, 16, 16, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominei32_v, 32, 17, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxei8_v, 8, 18, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxei16_v, 16, 19, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxei32_v, 32, 20, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominuei8_v, 8, 21, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominuei16_v, 16, 22, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominuei32_v, 32, 23, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxuei8_v, 8, 24, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxuei16_v, 16, 25, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxuei32_v, 32, 26, rwdvm, amo_op, amo_check) + +/* + * Index EEW cannot be greater than XLEN, + * else an illegal instruction is raised (Section 8) + */ #ifdef TARGET_RISCV64 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoswapei64_v, 64, 0, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddei64_v, 64, 1, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxorei64_v, 64, 2, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandei64_v, 64, 3, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoorei64_v, 64, 4, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominei64_v, 64, 5, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxei64_v, 64, 6, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominuei64_v, 64, 7, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op, amo_check) #endif =20 /* diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 35ce006698..f49af084ef 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -649,23 +649,22 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_u= long addr, uint32_t wd, uint32_t idx, CPURISCVState= *env, uintptr_t retaddr); =20 -/* no atomic opreation for vector atomic insructions */ +/* no atomic operation for vector atomic instructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M) #define DO_OR(N, M) (N | M) #define DO_ADD(N, M) (N + M) +#define DO_MAX(N, M) ((N) >=3D (M) ? (N) : (M)) +#define DO_MIN(N, M) ((N) >=3D (M) ? (M) : (N)) =20 -#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \ +#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, MTYPE, H, DO_OP, SUF) \ static void \ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ uint32_t wd, uint32_t idx, \ CPURISCVState *env, uintptr_t retaddr)\ { \ - typedef int##ESZ##_t ETYPE; \ - typedef int##MSZ##_t MTYPE; \ - typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \ - ETYPE *pe3 =3D (ETYPE *)vs3 + H(idx); \ + MTYPE *pe3 =3D (MTYPE *)vs3 + H(idx); \ MTYPE a =3D cpu_ld##SUF##_data(env, addr), b =3D *pe3; \ \ cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \ @@ -674,42 +673,79 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong add= r, \ } \ } =20 -/* Signed min/max */ -#define DO_MAX(N, M) ((N) >=3D (M) ? (N) : (M)) -#define DO_MIN(N, M) ((N) >=3D (M) ? (M) : (N)) - -/* Unsigned min/max */ -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) - -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_32_v, uint32_t, H4, DO_SWAP, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_64_v, uint64_t, H8, DO_SWAP, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_32_v, uint32_t, H4, DO_SWAP, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_64_v, uint64_t, H8, DO_SWAP, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_32_v, uint32_t, H4, DO_SWAP, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_64_v, uint64_t, H8, DO_SWAP, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_32_v, uint32_t, H4, DO_ADD, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_64_v, uint64_t, H8, DO_ADD, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_32_v, uint32_t, H4, DO_ADD, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_64_v, uint64_t, H8, DO_ADD, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_32_v, uint32_t, H4, DO_ADD, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_64_v, uint64_t, H8, DO_ADD, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_32_v, uint32_t, H4, DO_XOR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_64_v, uint64_t, H8, DO_XOR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_32_v, uint32_t, H4, DO_XOR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_64_v, uint64_t, H8, DO_XOR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_32_v, uint32_t, H4, DO_XOR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_64_v, uint64_t, H8, DO_XOR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_32_v, uint32_t, H4, DO_AND, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_64_v, uint64_t, H8, DO_AND, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_32_v, uint32_t, H4, DO_AND, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_64_v, uint64_t, H8, DO_AND, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_32_v, uint32_t, H4, DO_AND, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_64_v, uint64_t, H8, DO_AND, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_32_v, uint32_t, H4, DO_OR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_64_v, uint64_t, H8, DO_OR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_32_v, uint32_t, H4, DO_OR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_64_v, uint64_t, H8, DO_OR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_32_v, uint32_t, H4, DO_OR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_64_v, uint64_t, H8, DO_OR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_32_v, int32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_64_v, int64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_32_v, int32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_64_v, int64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_32_v, int32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_64_v, int64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_32_v, int32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_64_v, int64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_32_v, int32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_64_v, int64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_32_v, int32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_64_v, int64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_32_v, uint32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_64_v, uint64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_32_v, uint32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_64_v, uint64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_32_v, uint32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_64_v, uint64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_32_v, uint32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_64_v, uint64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_32_v, uint32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_64_v, uint64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_32_v, uint32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_64_v, uint64_t, H8, DO_MAX, q) #ifdef TARGET_RISCV64 -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_32_v, uint32_t, H4, DO_SWAP, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_64_v, uint64_t, H8, DO_SWAP, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_32_v, uint32_t, H4, DO_ADD, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_64_v, uint64_t, H8, DO_ADD, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_32_v, uint32_t, H4, DO_XOR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_64_v, uint64_t, H8, DO_XOR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_32_v, uint32_t, H4, DO_AND, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_64_v, uint64_t, H8, DO_AND, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_32_v, uint32_t, H4, DO_OR, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_64_v, uint64_t, H8, DO_OR, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_32_v, int32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_64_v, int64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_32_v, int32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_64_v, int64_t, H8, DO_MAX, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_32_v, uint32_t, H4, DO_MIN, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_64_v, uint64_t, H8, DO_MIN, q) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_32_v, uint32_t, H4, DO_MAX, l) +GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_64_v, uint64_t, H8, DO_MAX, q) #endif =20 static inline void @@ -717,8 +753,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_amo_noatomic_fn *noatomic_op, - clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra) + clear_fn *clear_elem, uint32_t esz, uintptr_t ra) { uint32_t i; target_long addr; @@ -731,8 +766,8 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_L= OAD); - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_S= TORE); + probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_L= OAD); + probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_S= TORE); } for (i =3D 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -744,45 +779,90 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong b= ase, clear_elem(vs3, vta, env->vl, env->vl * esz, vlmax * esz); } =20 -#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \ +#define GEN_VEXT_AMO(NAME, ETYPE, INDEX_FN, CLEAR_FN) \ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \ INDEX_FN, vext_##NAME##_noatomic_op, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + CLEAR_FN, sizeof(ETYPE), \ GETPC()); \ } =20 +GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamoswapei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamoswapei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamoswapei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamoswapei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoswapei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamoaddei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamoaddei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamoaddei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamoaddei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamoaddei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoaddei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamoxorei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamoxorei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamoxorei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamoxorei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamoxorei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoxorei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamoandei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamoandei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamoandei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamoandei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamoandei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoandei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamoorei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamoorei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamoorei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamoorei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamoorei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoorei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamominei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamominei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamominei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamominei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamominei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamominei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamomaxei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamomaxei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamomaxei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamomaxei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamomaxei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamomaxei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamominuei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamominuei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamominuei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamominuei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamominuei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamominuei32_64_v, int64_t, idx_w, clearq) +GEN_VEXT_AMO(vamomaxuei8_32_v, int32_t, idx_b, clearl) +GEN_VEXT_AMO(vamomaxuei8_64_v, int64_t, idx_b, clearq) +GEN_VEXT_AMO(vamomaxuei16_32_v, int32_t, idx_h, clearl) +GEN_VEXT_AMO(vamomaxuei16_64_v, int64_t, idx_h, clearq) +GEN_VEXT_AMO(vamomaxuei32_32_v, int32_t, idx_w, clearl) +GEN_VEXT_AMO(vamomaxuei32_64_v, int64_t, idx_w, clearq) #ifdef TARGET_RISCV64 -GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) +GEN_VEXT_AMO(vamoswapei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamoswapei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamoaddei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamoaddei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamoxorei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamoxorei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamoandei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamoandei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamoorei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamoorei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamominei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamominei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamomaxei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamomaxei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamominuei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamominuei64_64_v, int64_t, idx_d, clearq) +GEN_VEXT_AMO(vamomaxuei64_32_v, int32_t, idx_d, clearl) +GEN_VEXT_AMO(vamomaxuei64_64_v, int64_t, idx_d, clearq) #endif -GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) =20 /* *** Vector Integer Arithmetic Instructions --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410327; cv=none; d=zohomail.com; s=zohoarc; b=YpWwzz0zoE0vG/Ag5vf4KTifCT9tRlffQy+6G9t2bJKMaFhjNb61BMjSv1V5JSQ0+LZiAoyucCGy+plscjl2IxsniizwWS1DtuOUH5L/Fns3RZpEDedv8DbOMbqtaJWiuIxzM7w2oQBpG1csiqqH7rTlvEc5f8gJYLHSfxr/PKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410327; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=65H2nOM6Zv+jL3nuWxhgnkDNOjW7kakLBlArAff0dV0=; b=G7P1buDVN0d8pjSI7vqvYDgbTtKzCuY/e1R3o6qruNqUYrz+3OC0gFi80fq2+e+/0c I1NGI7ritFuJY1naPC36Xgtt9twtifwo37RYqnkSGCG2NRsyK6ORjqPsqg3wJWrupOZj B4B6Esufpc3dVY5BLAip8F5xQ1M4opv5cBGrlevCi58Zs+Ki6cN7bPohjIRdo3OHPS7x EyzCLV9CLRfTcqhHfftRAaBnPanGR2yVpaNAxrI0wqPnpd6gbyOE71RtOzbNWzI96Z6+ q/CM1+9XHXimeP3Xxg3Lqu2RpHW6U6zk+BYd+p1ahz2XdP08J9WsZFMBmxfwXBD+gEen eHpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=65H2nOM6Zv+jL3nuWxhgnkDNOjW7kakLBlArAff0dV0=; b=dfce9RaFnYc9flD0HMbk6udc/2+Lt2ZqLF7/ApIFj/VddaKEUCsp8uc2nKTp54xTdz Z0CbKnjQcbCUVhv+uOGJr7O6u5mRaMbktND+P0a1pW/YU0NYhx4GTcyuwKDi9ksnOT4Y SgLpfE9Fz3FcfJzYdXOtxVfKJXNCdWf7P7zBY0X28hdB1ctD6enkTVvFe6ddinRxYY2T zRD90zBasiJNfzExOth0kNaGpznH5RyjpMpPuaizWG713H1zMICgFJmVgTlQxd7BOfGp /MhZczdVE9LzpWS15xOaUG1eJ0CR5gmRyefHLh+LfDQ5Dx3oNdzzUnWkt8pNInOU+TpT on+g== X-Gm-Message-State: AOAM531E4zIJ7XpPdn4YVC9R4KQjq9T5ycMnSXuQ+fMmTa4gWaCEtDw+ EY7rsIxwMd+KH5bVBov8uVd6pjouofI= X-Google-Smtp-Source: ABdhPJxd/hABcyKYPaLagYppy+5ZBz6tj69h8VJ/Pao3lQ29S8OwK5BGSu0BxL+DdnGrmYbdKPoE/A== X-Received: by 2002:a17:902:c211:: with SMTP id 17mr25364314pll.302.1595409571573; Wed, 22 Jul 2020 02:19:31 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions Date: Wed, 22 Jul 2020 17:15:50 +0800 Message-Id: <20200722091641.8834-28-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vl1r.v * vs1r.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvv.inc.c | 61 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 47 +++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 808f88fbeb..8cf5c4c065 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -145,6 +145,9 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) =20 +DEF_HELPER_4(vl1r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32) + DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6a9cf6ad53..e3f0fba912 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -267,6 +267,10 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 = @r2_nfvm vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm =20 +# Vector whole register insns +vl1r_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 +vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 + #*** Vector AMO operations are encoded under the standard AMO major opcode= *** vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index fb6d092539..4274daf08e 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1030,6 +1030,67 @@ GEN_VEXT_TRANS(vle16ff_v, 16, 1, r2nfvm, ldff_op, ld= _us_check) GEN_VEXT_TRANS(vle32ff_v, 32, 2, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vle64ff_v, 64, 3, r2nfvm, ldff_op, ld_us_check) =20 +/* + * load and store whole register instructions + */ +typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); + +static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t data, + gen_helper_ldst_whole *fn, DisasContext *s, + bool is_store) +{ + TCGv_ptr dest; + TCGv base; + TCGv_i32 desc; + + dest =3D tcg_temp_new_ptr(); + base =3D tcg_temp_new(); + desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + + fn(dest, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + if (!is_store) { + mark_vs_dirty(s); + } + return true; +} + +/* + * load and store whole register instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 7.9) + */ +#define GEN_LDST_WHOLE_TRANS(NAME, EEW, SEQ, ARGTYPE, ARG_NF, IS_STORE) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ +{ \ + s->eew =3D EEW; \ + s->emul =3D (float)EEW / (1 << (s->sew + 3)) * s->flmul; \ + \ + if (!require_rvv(s)) { \ + return false; \ + } \ + \ + uint32_t data =3D 0; \ + bool ret; \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, SEW, s->sew); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + data =3D FIELD_DP32(data, VDATA, NF, ARG_NF); \ + ret =3D ldst_whole_trans(a->rd, a->rs1, data, gen_helper_##NAME, \ + s, IS_STORE); \ + return ret; \ +} + +GEN_LDST_WHOLE_TRANS(vl1r_v, 8, 0, vl1r_v, 1, false) + +GEN_LDST_WHOLE_TRANS(vs1r_v, 8, 1, vs1r_v, 1, true) + /* *** vector atomic operation */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f49af084ef..995e873549 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -642,6 +642,53 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h, clearh) GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w, clearl) GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d, clearq) =20 +/* + *** load and store whole register instructions + */ +static void +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra, + MMUAccessType access_type) +{ + uint32_t i, k; + uint32_t nf =3D vext_nf(desc); + uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + + /* probe every access */ + probe_pages(env, base, vlenb * nf * esz, ra, access_type); + + /* load bytes from guest memory */ + for (i =3D 0; i < vlenb; i++) { + k =3D 0; + while (k < nf) { + target_ulong addr =3D base + (i * nf + k) * esz; + ldst_elem(env, addr, i + k * vlmax, vd, ra); + k++; + } + } +} + +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, LOAD_FN, \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ +} + +GEN_VEXT_LD_WHOLE(vl1r_v, int8_t, lde_b) + +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, STORE_FN, \ + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ +} + +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b) + /* *** Vector AMO Operations (Zvamo) */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410425; cv=none; d=zohomail.com; s=zohoarc; b=hKh0vFl8oPok2c0eRIB7DG8RGTa8nS0C9i6mtJ9YURvFLgS2a10hyD8vriHiLVGtONaIOBRXMXjkXcXKC4vvd6J0nhrCaj09zrWHfJLeYF2l8zsxaPNa7apEXb+FdzmPBJzMX0ihrO7fYZko1ObB21rNmGPRcLcItu6Pl0Q/yuY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410425; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=5Wcnm8IqhkmajVRLy3EPsUykg3HluDMA8Ajti6zvwSg=; b=UxQ63LznOCpuaHlAuKxCAru83MYZphx0UO5iseZfrV3R/LYyLoxX3zq+E1ewSOH6Sj32iycK+JKYnagIvwZ8uIWWHydSPCX0vFiH4qLyyW7UfgGOvhPvUUP00cUKdPDMcM6ZEPsaswmlCJtk3xBKk1SIOp5biLFYY5ZzpN/o3q0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410425024374.8759697398426; Wed, 22 Jul 2020 02:33:45 -0700 (PDT) Received: from localhost ([::1]:51156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB8B-0004GY-Hw for importer@patchew.org; Wed, 22 Jul 2020 05:33:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAuf-0001oi-U9 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:45 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46540) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAua-0005bk-Co for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:45 -0400 Received: by mail-pg1-x541.google.com with SMTP id s189so858230pgc.13 for ; Wed, 22 Jul 2020 02:19:40 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Unlike other vector instructions, load/store vector instructions return the maximum vector size calculated with EMUL. For other vector instructions, return VLMAX as the maximum vector size. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 118 ++++++++++++++++++++--------------- 1 file changed, 68 insertions(+), 50 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 995e873549..53867a6a2d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -121,14 +121,32 @@ static inline uint32_t vext_vma(uint32_t desc) } =20 /* - * Get vector group length in bytes. Its range is [64, 2048]. - * - * As simd_desc support at most 256, the max vlen is 512 bits. - * So vlen in bytes is encoded as maxsz. + * Get the maximum number of elements can be operated. */ -static inline uint32_t vext_maxsz(uint32_t desc) +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz, bool is= _ldst) { - return simd_maxsz(desc) << vext_lmul(desc); + /* + * As simd_desc support at most 256, the max vlen is 512 bits, + * so vlen in bytes (vlenb) is encoded as maxsz. + */ + uint32_t vlenb =3D simd_maxsz(desc); + + if (is_ldst) { + /* + * Vector load/store instructions have the EEW encoded + * directly in the instructions. The maximum vector size is + * calculated with EMUL rather than LMUL. + */ + uint32_t eew =3D esz << 3; + uint32_t sew =3D vext_sew(desc); + float flmul =3D vext_vflmul(desc); + float emul =3D (float)eew / sew * flmul; + uint32_t emul_r =3D emul < 1 ? 1 : emul; + return vlenb * emul_r / esz; + } else { + /* Return VLMAX */ + return vlenb * vext_vflmul(desc) / esz; + } } =20 /* @@ -289,7 +307,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, { uint32_t i, k; uint32_t nf =3D vext_nf(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t max_elems =3D vext_max_elems(desc, esz, true); uint32_t vta =3D vext_vta(desc); =20 /* probe every access*/ @@ -307,15 +325,15 @@ vext_ldst_stride(void *vd, void *v0, target_ulong bas= e, } while (k < nf) { target_ulong addr =3D base + stride * i + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -364,7 +382,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, { uint32_t i, k; uint32_t nf =3D vext_nf(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t max_elems =3D vext_max_elems(desc, esz, true); uint32_t vta =3D vext_vta(desc); =20 /* probe every access */ @@ -374,15 +392,15 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVSta= te *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -465,7 +483,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t max_elems =3D vext_max_elems(desc, esz, true); uint32_t vta =3D vext_vta(desc); =20 /* probe every access*/ @@ -484,15 +502,15 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } while (k < nf) { abi_ptr addr =3D get_index_addr(base, i, vs2) + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k =3D 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -563,7 +581,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t i, k, vl =3D 0; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t max_elems =3D vext_max_elems(desc, esz, true); uint32_t vta =3D vext_vta(desc); target_ulong addr, offset, remain; =20 @@ -615,7 +633,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr =3D base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -624,8 +642,8 @@ ProbeSuccess: return; } for (k =3D 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } =20 @@ -652,7 +670,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, { uint32_t i, k; uint32_t nf =3D vext_nf(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t max_elems =3D vext_max_elems(desc, esz, true); uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; =20 /* probe every access */ @@ -663,7 +681,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -806,7 +824,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, target_long addr; uint32_t wd =3D vext_wd(desc); uint32_t vm =3D vext_vm(desc); - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlmax =3D vext_max_elems(desc, esz, false); uint32_t vta =3D vext_vta(desc); =20 for (i =3D 0; i < env->vl; i++) { @@ -977,7 +995,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, v= oid *vs2, uint32_t esz, uint32_t dsz, opivv2_fn *fn, clear_fn *clearfn) { - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlmax =3D vext_max_elems(desc, esz, false); uint32_t vm =3D vext_vm(desc); uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; @@ -989,7 +1007,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, = void *vs2, } fn(vd, vs1, vs2, i); } - clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate the helpers for OPIVV */ @@ -1042,7 +1060,7 @@ static void do_vext_vx(void *vd, void *v0, target_lon= g s1, void *vs2, uint32_t esz, uint32_t dsz, opivx2_fn fn, clear_fn *clearfn) { - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlmax =3D vext_max_elems(desc, esz, false); uint32_t vm =3D vext_vm(desc); uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; @@ -1054,7 +1072,7 @@ static void do_vext_vx(void *vd, void *v0, target_lon= g s1, void *vs2, } fn(vd, s1, vs2, i); } - clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } =20 /* generate the helpers for OPIVX */ @@ -1241,7 +1259,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -1271,7 +1289,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(ETYPE); = \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; = \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); = \ uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ @@ -1333,7 +1351,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false);\ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -1421,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t esz =3D sizeof(TS1); = \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; = \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); = \ uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ @@ -1459,7 +1477,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(TD); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -2102,7 +2120,7 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ { \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -2124,7 +2142,7 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVStat= e *env, \ { \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -2145,7 +2163,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -2167,7 +2185,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ { \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -2228,7 +2246,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, uint32_t desc, uint32_t esz, uint32_t dsz, opivv2_rm_fn *fn, clear_fn *clearfn) { - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlmax =3D vext_max_elems(desc, esz, false); uint32_t vm =3D vext_vm(desc); uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; @@ -2348,7 +2366,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, uint32_t desc, uint32_t esz, uint32_t dsz, opivx2_rm_fn *fn, clear_fn *clearfn) { - uint32_t vlmax =3D vext_maxsz(desc) / esz; + uint32_t vlmax =3D vext_max_elems(desc, esz, false); uint32_t vm =3D vext_vm(desc); uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; @@ -3284,7 +3302,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ + uint32_t vlmax =3D vext_max_elems(desc, ESZ, false); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ @@ -3319,7 +3337,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ + uint32_t vlmax =3D vext_max_elems(desc, ESZ, false); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ @@ -3890,7 +3908,7 @@ static void do_##NAME(void *vd, void *vs2, int i, = \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ + uint32_t vlmax =3D vext_max_elems(desc, ESZ, false); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ @@ -4067,7 +4085,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -4211,7 +4229,7 @@ static void do_##NAME(void *vd, void *vs2, int i) = \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D vext_maxsz(desc) / ESZ; \ + uint32_t vlmax =3D vext_max_elems(desc, ESZ, false); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ @@ -4298,7 +4316,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t esz =3D sizeof(ETYPE); \ - uint32_t vlmax =3D vext_maxsz(desc) / esz; \ + uint32_t vlmax =3D vext_max_elems(desc, esz, false); \ uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ @@ -4798,7 +4816,7 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ @@ -4908,7 +4926,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H= 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ @@ -4938,7 +4956,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, cle= arq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ @@ -4968,7 +4986,7 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, cle= arq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tzS1NhxcZynnC3BiJPnOg5ltt6hy7hD1fUmF5Dof7xY=; b=i/qst5NB3gpcKwigmmRG8UBZDn+3ciJVdwAhIxCrmYHsBKD13BM5d1UpyV4yX3uW6i YwcwyfFSyzQOGEn+hhXJiaf0JTZ2CDD+twqnQ5tWhs0T5ZfPjIMBJwfu5o56fblvv0LI J77bX1HDwl9vfei6ED7NXg5K5JBWqL4rGAwiHYa5/2itJI9jluqRfq1jLQq2Sqp93xag B0zpQTrjGCshVvxtQ01mx6bwEngu8gdqKwfo7n81lOdEVhCrRgm/eFmhGQ3aHBRtUUww FkR2LwXBQY4SG0iPqi7okac2+EheRBVBkNLXz/FffFXZ1x2AAcoJEJ4leHTChoPCUXR9 2XtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tzS1NhxcZynnC3BiJPnOg5ltt6hy7hD1fUmF5Dof7xY=; b=lFBprkDFuSDI2RpLUlKEOdvAhirYtYVcBHz4eqOqkEWNOntIn9RQBiagvDT81w9Oww 7r5gdQWZboH5ykQLUPy8A03jy/skigQFptGtKkdaTF728uD0/hCD0EygFHNb2dQYB/pt JVPPGt2pCGG2fcev2yQqyytcXUW4CExYl7IxotKsf54QJal1xYuq4n3fzl30Mz8TdlBv +6ECAnqCvlhdXSho5RwYGUQShiNpoa6aimZshj8WKscgICv7dwzsb4e9Yu7cG8Iy1f6i iHPOR+72akIVmo6C0mVUGFroJ5Mzy0vw+CpZa0MCRxYyssMo4Kb8yG3EiZihtVKCctg0 ZVcw== X-Gm-Message-State: AOAM5302whtER8UDGaI0V7niSJoczE0YMdtXET/c15f47NzWqL+1H4Fo YZYuT08XdO+v3M77335IPwSNIKH9X1Y= X-Google-Smtp-Source: ABdhPJxMdS6cWMWKiBf1UK/uCt6dzGE47WB/MNcPgyXBErNe45ULB9WKJKk8w3Csj9zmoSA+2zQ7QQ== X-Received: by 2002:aa7:8005:: with SMTP id j5mr26374609pfi.142.1595409583246; Wed, 22 Jul 2020 02:19:43 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation Date: Wed, 22 Jul 2020 17:15:52 +0800 Message-Id: <20200722091641.8834-30-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 32 +++++++++++++++---------- target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++- 2 files changed, 29 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a650df0441..446ce1a667 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,8 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 +#include "internals.h" + #define TCG_GUEST_DEFAULT_MO 0 =20 #define TYPE_RISCV_CPU "riscv-cpu" @@ -379,20 +381,14 @@ FIELD(TB_FLAGS, VMA, 12, 1) /* Skip MSTATUS_FS (0x6000) fields */ FIELD(TB_FLAGS, VILL, 15, 1) =20 -/* - * A simplification for VLMAX - * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * =3D (VLEN << LMUL) / (8 << SEW) - * =3D (VLEN << LMUL) >> (SEW + 3) - * =3D VLEN >> (SEW + 3 - LMUL) - */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { uint8_t sew, lmul; - sew =3D FIELD_EX64(vtype, VTYPE, VSEW); - lmul =3D FIELD_EX64(vtype, VTYPE, VLMUL); - return cpu->cfg.vlen >> (sew + 3 - lmul); + lmul =3D (FIELD_EX64(vtype, VTYPE, VFLMUL) << 2) + | FIELD_EX64(vtype, VTYPE, VLMUL); + float flmul =3D flmul_table[lmul]; + return cpu->cfg.vlen * flmul / (1 << (sew + 3)); } =20 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *= pc, @@ -404,13 +400,23 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax * (1 << sew); + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) + && (maxsz >=3D 8); =20 flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2) | FIELD_EX64(env->vtype, VTYPE, VLMUL)); diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 4274daf08e..89209a5d18 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1270,7 +1270,16 @@ GEN_VEXT_TRANS(vamomaxuei64_v, 64, 8, rwdvm, amo_op= , amo_check) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + return (s->vlen >> 3) * s->flmul; +} =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) { --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410744; cv=none; d=zohomail.com; s=zohoarc; b=ML0Y8uFCKjd+CfH7z3rEvT4uzTPaiffeIyNcvUSFdwH+YS1LGX2eYf/usW41tobaJ3PZ/z5aW3sB5yYzH4QSfwOuqIGPEKsqgBZ6pIchT0gWm1xiRK8yIkai8PaowcnwGn4CvEoM0fh9xBBCSzvaAhr+qUoJW5MXqHFbt9VCtMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410744; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=mGnKSMkKMtsxEVb7JFS0nY27EekRK3d4wsP51kVAl90=; b=IgK49w3xwrxKC3EYx/1EZvAmPZOTs9uS/X+j2joGPhPczuAcqQzqqD50RCe3fnFJ1lazC1S52cYmSI87d7LFs242xkS9ANIkAs8wbb+LfPjhlYQvWtrTO/M//QBQB8WHfFRKYIatFSEC8i9ytGK3zR1KqbAG2FqvGUABg3mz38I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410744666335.6046815469514; Wed, 22 Jul 2020 02:39:04 -0700 (PDT) Received: from localhost ([::1]:52080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBDL-0007ZA-Bs for importer@patchew.org; Wed, 22 Jul 2020 05:39:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAum-0001wh-MV for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:52 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:41161) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAuk-0005cw-FD for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:52 -0400 Received: by mail-pf1-x42d.google.com with SMTP id w126so698958pfw.8 for ; Wed, 22 Jul 2020 02:19:50 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e3f0fba912..1d34fa647b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -509,7 +509,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 = @r_vm vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm -vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm +vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410520; cv=none; d=zohomail.com; s=zohoarc; b=eQBgUSyGe173O/9ztlvsXCQ+5vTLGoChUG+3BpRJE17WURu7UhKIMBfbywHJDCJz8SD2eJbbY2n+r/BKCb1RfCN0frxWt1pB9Jl1eeyXFokbphGcwocKomWQBY39mBvF3IcYtkM7MEGJSVyduJQVlXgmpzow8UKpvI9Vk044kXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410520; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=4piOJT33/Ks8zF+9lTjhNZDrDdEfFTDr1vcWWDQC6yw=; b=fz4MaTYUqTjcqSHpmPGOKyNBD6qiJqMRPK/xA5i1W3PqczW8FRohq7HPIXzIRm5WilPtbxclkiJUNxpflM7CTZm/zLD40DXFEuTS0dMmtGeY+fq+DPP7CMShDyWL1XX4eNPNh7HD4kz25GFFhHL+wfiyL+vlv0ZkFPK8sg1x8MI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410519955834.4534053608936; Wed, 22 Jul 2020 02:35:19 -0700 (PDT) Received: from localhost ([::1]:59652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB9i-0007eY-Hp for importer@patchew.org; Wed, 22 Jul 2020 05:35:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAur-00021B-3m for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:57 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:36265) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAuo-0005dS-7I for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:56 -0400 Received: by mail-pl1-x62a.google.com with SMTP id t6so658784plo.3 for ; Wed, 22 Jul 2020 02:19:53 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4piOJT33/Ks8zF+9lTjhNZDrDdEfFTDr1vcWWDQC6yw=; b=C1uNwpcn6DVXbFosicjBeiHqTCuaxM5YkcRemZVJjGjBew1JJzG8e++v3GiVL0w/aA ahtMlU/hlI2QoVjuxBfgkhXJdLK37WqRICOwVCpDswK0FpkXfkwHyWzPZH6vfOPoXEIV rG0EcH1icZgQ58y/tiIVuPizuk98bXY4VIPqNZWTtGpOf4THJBTfCGnZOYV5+H1a050j /vaL3IAcnd62WdSf5ffM8shoQJB8U/w5EbjOh/Crk898A0Fu+XQOW5f8MJ/cmq+cHdju btzYuGBUGXdWfeTzWVMEEeAdHlq/3j7gxkPvETF2GxKemR3Rftk6sA3QT4R+FwPbpn9d xWEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4piOJT33/Ks8zF+9lTjhNZDrDdEfFTDr1vcWWDQC6yw=; b=id8gRxflJCZK4vm3ZV+A84FJZcT9SVOshZl4v6zgifKOJ8pEspZtqMw6vDk4isfk+O wCoYxZGjYiX4LjH5gsySuIXE+L5MRL3TA+LW21wFYBzWF7yDRC02RSFoQkqRPjfvN/X+ E+vucfUdm+bpfCXGazG1a6gdgmQsUdIvLSt4Qdd8eY1RGJ6pOlSJq5ZqMMsEU95DQUpj /NQosshawqjylamrudCeMbyWBLADUBFJTPaRg5aMOuM5YBlFLpIW2KW9G8jN+HjCvA8C Th/jpY5tk57GVn43rT1bd1nrHXn0QfLGdiGf/eVn+2gzZvoxhazKK8q4K2jVLUvRr5CX 40RA== X-Gm-Message-State: AOAM5331F778+Lcgv2O0rrQwlC5UVlvd2bRt+gIoUgW2c7eP5Ffvn3/4 zPYIsNrT0uJ3YPN147Hv/1TPicd3RSw= X-Google-Smtp-Source: ABdhPJyayt+RE2BbcPL5Qbk+24xYDL0+o4vI1yRNlbnIekYyi/8DMIRymJkUzgSrUkugz/kmdNgxDA== X-Received: by 2002:a17:902:7292:: with SMTP id d18mr9103648pll.137.1595409592826; Wed, 22 Jul 2020 02:19:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions Date: Wed, 22 Jul 2020 17:15:54 +0800 Message-Id: <20200722091641.8834-32-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1d34fa647b..7ad936e605 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -532,7 +532,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 = @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm -vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm +vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410592; cv=none; d=zohomail.com; s=zohoarc; b=XhhoHWbnKXbbnMzxCE9+Em1BQARC+n8eNKZK5biNAoe8/IHRkqdRYz9TnX6fwV1sBp4mPOqU//IIplJW4vdDpBkLBlvsWn4ix5yCNWqXXUPt9ghT1OAvXH6VpHLoLCw4oC6Yevsjc+bQ6UL8lh91tADl+FzwEosKRLSOzvCsBK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410592; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=CQyiOAp6zSE2OTRbXxeepqY8bKy5Uz4AiqvMqjbMfOM=; b=BEaBVeoUR3wFPeqz9QLBpCcHt2G4bHWrjfdBsV+rtt2xMTpLZlUxTh8gGAjsGMJg5Shz5EB2/sFc2eIGTsW/2fWgP+oSXgtCDZKLNT4yKvyyJwF2tIiT5PCfSNzTXpR51BpgXcQPSONDeGI2KPDLQLI+7qp/K+pwBApxQxpz4oE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410592379919.1512364229931; Wed, 22 Jul 2020 02:36:32 -0700 (PDT) Received: from localhost ([::1]:36646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBAt-0001PF-59 for importer@patchew.org; Wed, 22 Jul 2020 05:36:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAuu-00029i-3o for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:00 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:41165) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAus-0005dz-HY for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:19:59 -0400 Received: by mail-pf1-x431.google.com with SMTP id w126so699129pfw.8 for ; Wed, 22 Jul 2020 02:19:58 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CQyiOAp6zSE2OTRbXxeepqY8bKy5Uz4AiqvMqjbMfOM=; b=c7H16sQNWt6UJE0pkVg5XGwDoixWPzVs/7Q7ofvPJGvfG5HVHntrQGeA797hLSLRjz R5oB/gT2/1PgiP2JjxGH0xKwMp6+CDSBSmEUNfZEe55WZrXwr7X1Ndou9sbNUYKEkO6x dRSkeZKeqwNil88QZQRs4ZFzXmS+djtmlQ97IyZjQ8TEgRNYlwecxXGji1T28wx5zQMn 8CBFL0ZzxW/q3OEB0AKUqiYMZ65OYZJDt6swIBGq/QvXrz3WsfLbeSHpQHniThFOgpGC e08+jRDRDY6OK8IuV+zNfsEjBCqeYLzHDpyPTlXwobyL3wY8KUbNEPIEg1+gdDl4w2bp sxSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CQyiOAp6zSE2OTRbXxeepqY8bKy5Uz4AiqvMqjbMfOM=; b=gSNH/Hf2GmuvDYI6ruftcMbIjadn6NmkCYnEhyjJ1BW++OHOYdRMv2d12eqALncQyR BV44mR8PxBquBGEc1zy4O00XFqGNjpZEs5uTzFOZUM6yXlaSvDYyI9vsnw6DBCmv5t4x H3JD+uv5K3HpGDELkNyHzLJNn5O8jCOq/1HX3EQHq5dncZn2Pic5EGRvOhoq30Kcs/vz Y3VYlWDiSHPei3iYSWt5+HbAIVdYDxLSrsz+lcdCnv78NIahnWm4fdpcHT2f/pSbLDHW nBtV5u8e5KhIje64STYpNjJBadxH6CEEhQNZpV75YD1oIRxTwkRciR7T2tOZE4wCHpRb MRCA== X-Gm-Message-State: AOAM531bq02a4UnAagPEUC7jYX155przzLBp3EyrcZ+Eqv8TpzTbLshD jjHiF2dUOnDuM9Cl2RHwxqg+l5dZr2U= X-Google-Smtp-Source: ABdhPJyO03RQLudeckfTeqc1WvA1AWq0kSaubRbtv/C/kTqGbgpOBlyUaLiiceVuOVbBfpCbvL7N+w== X-Received: by 2002:a65:640c:: with SMTP id a12mr25949125pgv.88.1595409597031; Wed, 22 Jul 2020 02:19:57 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction Date: Wed, 22 Jul 2020 17:15:55 +0800 Message-Id: <20200722091641.8834-33-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 7 ++++--- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 8cf5c4c065..e9e1c4e2f5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1048,7 +1048,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env,= i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) =20 -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32) =20 DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) =20 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7ad936e605..c9c9f30742 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -573,7 +573,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 = @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm +vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 89209a5d18..cca06dd1d3 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2933,8 +2933,8 @@ GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) =20 -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector mask population count vpopc */ +static bool trans_vpopc_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2954,13 +2954,14 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr= *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(a->rd, dst); =20 tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free(dst); tcg_temp_free_i32(desc); + return true; } return false; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 53867a6a2d..d3824304ec 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4655,9 +4655,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) =20 -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector mask population count vpopc */ +target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt =3D 0; uint32_t vm =3D vext_vm(desc); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 4 ++-- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e9e1c4e2f5..1dea171599 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1050,7 +1050,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env= , i32) =20 DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32) =20 -DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32) =20 DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c9c9f30742..b5b59fe6dd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -574,7 +574,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 = @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm -vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm +vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index cca06dd1d3..3ef106ddeb 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2968,7 +2968,7 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a) } =20 /* vmfirst find-first-set mask bit */ -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) +static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2988,7 +2988,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); + gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(a->rd, dst); =20 tcg_temp_free_ptr(mask); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d3824304ec..5bda274e70 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4674,9 +4674,9 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPU= RISCVState *env, return cnt; } =20 -/* vmfirst find-first-set mask bit*/ -target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* vfirst find-first-set mask bit*/ +target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 5 ++++- target/riscv/vector_helper.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b5b59fe6dd..37b2582981 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -575,9 +575,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 = @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 3ef106ddeb..3834aca9ab 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3006,7 +3006,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr = *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd !=3D a->rs2)) { \ uint32_t data =3D 0; \ gen_helper_gvec_3_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5bda274e70..aeaf3d1cfa 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4701,7 +4701,6 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; int i; @@ -4731,9 +4730,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPU= RISCVState *env, } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, i, 0); - } } =20 void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- target/riscv/vector_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 37b2582981..4560bc4379 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -578,7 +578,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 = @r2_vm vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aeaf3d1cfa..c1ed0ff6ad 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4774,7 +4774,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPUR= ISCVState *env, \ CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 -GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) +GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh) GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl) GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410711; cv=none; d=zohomail.com; s=zohoarc; b=nzswuUOyCo0J2uNSjKtVdDv2ytUeGwJfN9tQ9MEN1JKuSMPUrznQb9r7ZNYbWQIS6c7KG16qKuaW2oCAd5ESguJEyzU4kYCNYwNxar3xMnLkE4/qaElFi61L5PJhLompMsYhVjdoLfL5kjMrD+XxsLTGLKtFhfogCk4uRaESlk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410711; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=hnT4LfCpRz4l4mcm1WiBHzRG6KMccLv2xCUhcy2MNm4=; b=iclJ5b6sJeMt8TSEyO8aViErYrPionGFKABHh7gfYruAO+aYXUqNMbLvcbOp0SuEBXtT3D781oq3xHBnndBUqS9m29dHt4qscVQNd0n5CKAlJXRCOm/VcS0u/XsTZaM/b4aUwfdLW489+L/r57emw9SAYA8AAl0lMCrGXFReWRk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410711416279.1472340367677; Wed, 22 Jul 2020 02:38:31 -0700 (PDT) Received: from localhost ([::1]:48668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBCo-0006CD-4y for importer@patchew.org; Wed, 22 Jul 2020 05:38:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvA-0002gU-UU for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:17 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:52342) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAv8-0005hA-DB for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:16 -0400 Received: by mail-pj1-x1031.google.com with SMTP id gc9so867819pjb.2 for ; Wed, 22 Jul 2020 02:20:13 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4560bc4379..01316c908d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -579,7 +579,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 = @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm -vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm +vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410757; cv=none; d=zohomail.com; s=zohoarc; b=QJXORFhPgNMm3H96YBhBm2Px8VM4dbX5ymQv6COjJ5YgaWHZHoOaYwuLK3ZaZNVNrLRezYl9qPXuJN0UOHGMM4ksWrbDiyNjle6nE9TYr56qafqNlrcFHyWpo9iK1lyc529zwzqr/4guonxnaGSnthC6WEzYYP9zq2QR5BBMTt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410757; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=mA6WmTq0HAeTWVW9JADPKdrVVOFarnUnoSrrLmA/A+I=; b=jnFgu71/KzM08iJgspZ0klZF0NEMH32HJhZH/GUmiYtNyEVM8MVOv1UEiFHwZF9vyUFhZwPbl7k07oWrpv0UYUQ/ynRKZHinGTHdFmeHO76irWH9oyVSFh2awc2Wh8//LqWbShM9oRcB5NCGEqiJMxSrVGlqoLtZ0Eb4XkIFVnY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410757914347.5866339253595; Wed, 22 Jul 2020 02:39:17 -0700 (PDT) Received: from localhost ([::1]:53446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBDY-00086S-OO for importer@patchew.org; Wed, 22 Jul 2020 05:39:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvE-0002lz-2B for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:20 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:38982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvC-0005jH-75 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:19 -0400 Received: by mail-pj1-x1042.google.com with SMTP id b92so865665pjc.4 for ; Wed, 22 Jul 2020 02:20:17 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mA6WmTq0HAeTWVW9JADPKdrVVOFarnUnoSrrLmA/A+I=; b=Wti7+Qy45b3jYHs9Xy8mbgqEGdSM7BFOtliljG7BXGEWbbMK9RJiWprcnalthE2p6m O+q1HOouRAZSiJvCz1/9cYhInm+VKZ+myABMGLP2lugHqqV7iWSlrswkFtTENQ3XcgzC 6p7DEF42AdDLD4JIeEKNtqfAnGq1jt/26isQm04kNEgI0FYp4jFGUz0ikSY51yQ3CJOe vyVJ8E1P/iNx2KkumbGYh0CL1+l/mkNRSDEZEvqtjxYKnJzmSiwqQ2r+bt9zn2rALPZp B3XKS7U2Ro22lDkfSbe3YwftGsvBHpYbDGRufotqwzyjDRdhCl2oqXOG3KD9hyv0Hnlp ewTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mA6WmTq0HAeTWVW9JADPKdrVVOFarnUnoSrrLmA/A+I=; b=MQYlRwQ3cLGgf5rrLvitHwmRyCjszd0mDqToCUIIgrIiNUs2fyCw0eaHUlW7l7atFq Wx7sWRuiv7cbZnGTz1NQ5ihisKrykFYEb5QpQqkqZwiuzpMb+1TLzTiCwNN1gpIrs6lI pRE4sgE9olbawsROGafMYDtExUi74mIQv/j3UZsbMSzBQ/evgwHwtE97+ydJhREbFIrf e3YODixitPM0SfB0l0C7hiMHdMkDK3sCLMKWayzNPoXOCev/WMC8yOIBUs40kaQdQ6pd qcnggS/cgCMH2qmcuNFY5RhJ1lHBdvZYEXvsfNb/zuhJWpsI2C/S11X38qZcIS88nWmF xpSw== X-Gm-Message-State: AOAM532VlQPeb4nXgvHxaj2KL2I4pakvk1ei6Wjop8TmnWeht/pJWnLX dQB9Qqmh1RVDA6tr2BE3D1cKXqoMDbU= X-Google-Smtp-Source: ABdhPJxawJijz3GoSVgY68jv8xFhHGiVxhuOumLtsecuLmof5ZIi1Fr6ayu3ousgh+c38+o70/jIUg== X-Received: by 2002:a17:90a:cc:: with SMTP id v12mr8357277pjd.96.1595409616905; Wed, 22 Jul 2020 02:20:16 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended Date: Wed, 22 Jul 2020 17:16:00 +0800 Message-Id: <20200722091641.8834-38-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 26 ++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 3834aca9ab..6b4b7f6574 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3097,17 +3097,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v = *a) /* Integer Extract Instruction */ =20 static void load_element(TCGv_i64 dest, TCGv_ptr base, - int ofs, int sew) + int ofs, int sew, bool sign) { switch (sew) { case MO_8: - tcg_gen_ld8u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld8u_i64(dest, base, ofs); + } else { + tcg_gen_ld8s_i64(dest, base, ofs); + } break; case MO_16: - tcg_gen_ld16u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld16u_i64(dest, base, ofs); + } else { + tcg_gen_ld16s_i64(dest, base, ofs); + } break; case MO_32: - tcg_gen_ld32u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld32u_i64(dest, base, ofs); + } else { + tcg_gen_ld32s_i64(dest, base, ofs); + } break; case MO_64: tcg_gen_ld_i64(dest, base, ofs); @@ -3162,7 +3174,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, =20 /* Perform the load. */ load_element(dest, base, - vreg_ofs(s, vreg), s->sew); + vreg_ofs(s, vreg), s->sew, false); tcg_temp_free_ptr(base); tcg_temp_free_i32(ofs); =20 @@ -3180,9 +3192,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, } =20 static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, - int vreg, int idx) + int vreg, int idx, bool sign) { - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } =20 static bool trans_vext_x_v(DisasContext *s, arg_r *a) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410070; cv=none; d=zohomail.com; s=zohoarc; b=LhW19faVISq99lvTim+PtHSM/CgWhju7p0NaX0ljA4n8w1xQz3GStHH5StonuHTJxy4dP0LK4wdnDX3MMXGDqENfjFGuE43jv6OBmc0c60oStE25XUQvse1fmBpk8N55Xahw35LHUkpv+LX5Svt4+lw2zfl4LOgCuS0juBhnNSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410070; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=IWrCcJNFCIXNETTyltO0w8hd+iSggOqWcQXMvciqGQ4=; b=mXp0l+amkc1LY1zF1Eb2d3aXYHbJzatEaeAqErwwDNuh7fUdauQqrhobtCgPWa7znMu2nJz6gCZD2SuLq3Xfxnl2uwxVdJjerWO06MXduUwyHxw9qa5HO+qepzpeiuaO/zgLQJaFu+anfBQF4ECtaSAzomSYThEQExLRJ/D03FE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410070750544.238855505478; Wed, 22 Jul 2020 02:27:50 -0700 (PDT) Received: from localhost ([::1]:48730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB2T-0000L3-E6 for importer@patchew.org; Wed, 22 Jul 2020 05:27:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvI-0002rE-Mc for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:24 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:54155) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvG-0005mE-H5 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:24 -0400 Received: by mail-pj1-x102b.google.com with SMTP id a9so866646pjd.3 for ; Wed, 22 Jul 2020 02:20:22 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IWrCcJNFCIXNETTyltO0w8hd+iSggOqWcQXMvciqGQ4=; b=A6776ZCMWlg94EKNM/QTZrh43UcJTXyrRRa+Rooot6v5+tX4G1cePHr97hgQeignOd 1IlnqaSAdliLoMqDiuTDhjunOpsD2FlakJ+3qvEczST42FVuPelHj8d+WA9o/BfwPVnq lxxts7ezrQ8dkMlHylsgeGjs/0ttPj5PdG7xqowvZanP6M36dY4+gRZR6EcBb4BvBaXQ Cl9tix7FN77GrgQCC4JGtFvAQvKTBKNHBn9ENDKDotl/z9TJyq1VGwE7fFzEXzW77Bz9 X9D3ydpuRXAnJS5MnUJ4M2Wi2cDRfMoeNfx7EcI/6yRwrLMgaAgbZfTsjrmRVXFqc44c rzjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IWrCcJNFCIXNETTyltO0w8hd+iSggOqWcQXMvciqGQ4=; b=c3LD7895M8T+fDz1REHaSay4AdSmWe+i0uWv39h+9H5g4BcBw8o1uV3LYapxlc9amm O7hxfpyEaZeNqgjFrJVRfN1zWWitOHpM6ZO/4QLxtRQ3VVx7FhJ/j2iTsDNZ+G4QknK+ zJTM6h+Fhd+T9G2ehHnxQj+lKxuY0maYQ/cvqV36cBQbLo+wWax2Wr1CFgifAjkXIZrW zfSs1Os0Ud31HxUVIBd2KymR/NfDuhp98df9wgGxfByqdY7TTW9OrZ1Qm6QrkI6WU0yN 7VvWedmOUEI3zxqZIXcpX7CIhXB9O/ZDzIeUQOKFdmJzXX4GpfFgTBBlTnLz6UYeawl5 WLIQ== X-Gm-Message-State: AOAM533Irdj1fQxhOni/8SPBZspoESSZbFGB4XOnF8jAPkyxkZJx2kqZ 92fL96/WKuVNjwRMxNOeyGInoGDxib4= X-Google-Smtp-Source: ABdhPJwP7sySkmckyVKU5n1H+RqNNRpsnr4Q44eiPfTrC2PTV/ej6SCkZwAlvIHtfrVHYOnYd912Mw== X-Received: by 2002:a17:902:9683:: with SMTP id n3mr25264460plp.65.1595409621093; Wed, 22 Jul 2020 02:20:21 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions Date: Wed, 22 Jul 2020 17:16:01 +0800 Message-Id: <20200722091641.8834-39-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 6b4b7f6574..af19561e7d 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3384,11 +3384,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_= rmrr *a) } =20 if (a->vm && s->vl_eq_vlmax) { - int vlmax =3D s->vlen; + int vlmax =3D s->vlen * s->flmul / (1 << (s->sew + 3)); TCGv_i64 dest =3D tcg_temp_new_i64(); =20 if (a->rs1 =3D=3D 0) { - vec_element_loadi(s, dest, a->rs2, 0); + vec_element_loadi(s, dest, a->rs2, 0, false); } else { vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); } @@ -3415,7 +3415,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) } =20 if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >=3D s->vlen) { + int vlmax =3D s->vlen * s->flmul / (1 << (s->sew + 3)); + if (a->rs1 >=3D vlmax) { tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); } else { --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410154; cv=none; d=zohomail.com; s=zohoarc; b=CPm4WqM8Ylgt7aENqcV3EpI7FS1khWyMguxhZjijzaocwq0ahqnLzD4L2M01wWqWCnerm5d5hrnArC/JAAMkPCDK2NM73nDUsBrhmuMYNpYVfImGjOyY084kSJo2eBOW+Ksk79yKnSmK6nsuHtHVKKs3aAaLBuUhVhSnYZ5Bq5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410154; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=b009y4bHWo9FAz89fm3BgjB9nWZ1yvMrO2kzUNMCm3c=; b=DnJFvjlwmwB2vigMkFmcx0+B9uIQqSoqVAJ9MiTApB/86K7BAs6/zfKfrQhne4eEDMWZY+Q5SqzkYFnCxSm9dN+o8DMdtSmJXSsf/2zeJwaZS+E4jXZpaE9YortY6JrJ+dEE+qK1hwLGEjYaWsCKVbdXbbsS0INbS1jN/7iHsdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410154170822.9277970429157; Wed, 22 Jul 2020 02:29:14 -0700 (PDT) Received: from localhost ([::1]:57004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyB3o-0003gZ-Ud for importer@patchew.org; Wed, 22 Jul 2020 05:29:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvM-0002yc-EB for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:28 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:34895) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvK-0005mn-Il for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:28 -0400 Received: by mail-pj1-x1034.google.com with SMTP id f16so877639pjt.0 for ; Wed, 22 Jul 2020 02:20:26 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang * Remove "vmv.s.x: dothing if rs1 =3D=3D 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 46 ++++++++++++++++++++----- 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 01316c908d..ef53df7c73 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -580,8 +580,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 = @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm +vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd +vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index af19561e7d..780f8660bf 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3252,27 +3252,57 @@ static void vec_element_storei(DisasContext *s, int= vreg, store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); } =20 +/* vmv.x.s rd, vs2 # x[rd] =3D vs2[0] */ +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) +{ + if (require_rvv(s) && + vext_check_isa_ill(s)) { + TCGv_i64 t1; + TCGv dest; + + t1 =3D tcg_temp_new_i64(); + dest =3D tcg_temp_new(); + /* + * load vreg and sign-extend to 64 bits, + * then truncate to XLEN bits before storing to gpr. + */ + vec_element_loadi(s, t1, a->rs2, 0, true); + tcg_gen_trunc_i64_tl(dest, t1); + gen_set_gpr(a->rd, dest); + tcg_temp_free_i64(t1); + tcg_temp_free(dest); + mark_vs_dirty(s); + + return true; + } + return false; +} + /* vmv.s.x vd, rs1 # vd[0] =3D rs1 */ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { /* This instruction ignores LMUL and vector register groups */ - int maxsz =3D s->vlen >> 3; TCGv_i64 t1; + TCGv s1; TCGLabel *over =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); - if (a->rs1 =3D=3D 0) { - goto done; - } =20 t1 =3D tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + s1 =3D tcg_temp_new(); + + /* + * load gpr and sign-extend to 64 bits, + * then truncate to SEW bits when storing to vreg. + */ + gen_get_gpr(s1, a->rs1); + tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + tcg_temp_free(s1); mark_vs_dirty(s); - done: gen_set_label(over); return true; } --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410272; cv=none; d=zohomail.com; s=zohoarc; b=RkNOnU5XiqsZfVRKRAUYrz2RMdD4UGevF++fFxEUKuBhMekkGB+gq3I2Y7Ma8nN+706CmD/KZcmzA6GPN3sSO/DKK+6sVowzD+JyW2Sl6CeK1vsEadHl1cfxjuaRxPepWfX2Z567B7B7nW0/wxNwF+sfWDQKM4u/Yq/GhGAEpW0= ARC-Message-Signature: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 0.9's rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 780f8660bf..54c08ea1f8 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2722,6 +2722,7 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) { if (require_rvv(s) && + has_ext(s, RVF) && vext_check_isa_ill(s) && require_align(a->rd, s->flmul) && (s->sew !=3D 0)) { @@ -2744,7 +2745,20 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv= _v_f *a) dest =3D tcg_temp_new_ptr(); desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); + + if ((s->sew < MO_64 && has_ext(s, RVD)) || + (s->sew < MO_32)) { + /* SEW < FLEN */ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i32 sew =3D tcg_const_i32(1 << (s->sew + 3)); + gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1], + sew, cpu_env); + fns[s->sew - 1](dest, t1, cpu_env, desc); + tcg_temp_free_i64(t1); + tcg_temp_free_i32(sew); + } else { + fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); + } =20 tcg_temp_free_ptr(dest); tcg_temp_free_i32(desc); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410950; cv=none; d=zohomail.com; s=zohoarc; b=UCjIBRO4jkY4gt/JyPNKGZ9sK/2HAmuLQNVqnnZr4tX3UCciEXiFPFrVljBEWjI0B+yCn9pfk1wzVe61oih7JHEZfZc+HDaQ2D/tVgZY1Wn0Dfl/yYRXOpQ1RpC3e/w9RkQCUGOSBjlbHi2CFpGYf72KJ7VNMQ5l8ViYlrBQr4I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410950; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=BQ/w72oiGdyOS4wgaZxohpaXTkk17SEH1EVT1dtoFas=; b=Ru6lONa/f4dek2QrMhTm8t3j4hHT6Gva3Wco1R/c6ss2nypQByG0dnMfh4JPQcV4qjCUuZnoQMvI6ql3UK2cElyXU9lZkrmIzi+OZd8Z5sdFVcA+ZDrVX2twd5BZZAEuwYjKqc74qrsjz/3JvyK0N2FU22TEIZ67Ih3KkrKCzeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410950936492.09793832476817; Wed, 22 Jul 2020 02:42:30 -0700 (PDT) Received: from localhost ([::1]:41236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBGf-0006BT-PS for importer@patchew.org; Wed, 22 Jul 2020 05:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvV-0003Kf-90 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:37 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:55326) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvS-0005os-RS for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:36 -0400 Received: by mail-pj1-x102b.google.com with SMTP id k1so862608pjt.5 for ; Wed, 22 Jul 2020 02:20:34 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 0.9's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.inc.c | 45 ++++++++++++++++--------- 2 files changed, 31 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ef53df7c73..4be1b88e2d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -583,8 +583,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 = @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 54c08ea1f8..56cd7444f2 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3326,14 +3326,22 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_= s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs !=3D 0) && (s->sew !=3D 0)) { - unsigned int len =3D 8 << s->sew; - - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + if (require_rvv(s) && + vext_check_isa_ill(s) && + has_ext(s, RVF) && + (s->mstatus_fs !=3D 0) && + (s->sew !=3D 0)) { + unsigned int ofs =3D (8 << s->sew); + unsigned int len =3D 64 - ofs; + TCGv_i64 t_nan; + + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan =3D tcg_const_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); + tcg_temp_free_i64(t_nan); } =20 mark_fs_dirty(s); @@ -3345,22 +3353,27 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfm= v_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] =3D rs1 (vs2=3D0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew !=3D 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + vext_check_isa_ill(s) && + has_ext(s, RVF) && + (s->sew !=3D 0)) { /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax =3D s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over =3D gen_new_label(); =20 /* if vl =3D=3D 0, skip vector register write back */ - TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ t1 =3D tcg_temp_new_i64(); if (s->sew =3D=3D MO_64 && !has_ext(s, RVD)) { + /* SEW > FLEN, f[rs1] is NaN-boxed to SEW bits */ tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); + } else if ((s->sew < MO_64 && has_ext(s, RVD)) || + (s->sew < MO_32)) { + /* SEW < FLEN */ + TCGv_i32 sew =3D tcg_const_i32(1 << (s->sew + 3)); + gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1], sew, cpu_e= nv); + tcg_temp_free_i32(sew); } else { tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); } --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 ++++ target/riscv/insn_trans/trans_rvv.inc.c | 27 +++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4be1b88e2d..0e1d6b3ead 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -595,6 +595,10 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111= @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 56cd7444f2..85f22a1495 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3527,3 +3527,30 @@ static bool trans_vcompress_vm(DisasContext *s, arg_= r *a) } return false; } + +/* + * Whole Vector Register Move Instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 17.6) + */ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + ((a->rd & ((LEN) - 1)) =3D=3D 0) && \ + ((a->rs2 & ((LEN) - 1)) =3D=3D 0)) { \ + for (int i =3D 0; i < LEN; ++i) { \ + /* EEW =3D 8 */ \ + tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \ + vreg_ofs(s, a->rs2 + i), \ + s->vlen / 8, s->vlen / 8); \ + } \ + mark_vs_dirty(s); \ + return true; \ + } \ + return false; \ +} + +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410880; cv=none; d=zohomail.com; s=zohoarc; b=ad82xd7bz6euYoyujIapmboXKn8KMoYpIo7IUf6E8YiM99wRhINZuCNFbTtVoulZyu6K7RU1z07WhGnL/G3GNwxWheglT4nESzu60MdyIscs9qbj+lh7SqPP4HrZ0MoFw1EcjzqaE+pcsEhno0Oda78DkvQlNYUkybSzOLLMl2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410880; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=7I29w9Yyi3mvfOblF5aq3CVAkBnj/fLwd8DUfu+tXI4=; b=dMrtpku2j53SfHa+hNwp2CKswg/pNRgyDiXoTBaVlGtGUhGNlXe2W71j9eYv7N6spj3H0WIBODd8LX8XFsOoIW4PsnyBfWaqJxPHvJXs1xdmiCouCH/ShApBsbQxU2ZufWtYddCkDWjaQIyS7tyVvTBl2kOxFq6fnwUbzHYF79M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410880312659.5237208344184; Wed, 22 Jul 2020 02:41:20 -0700 (PDT) Received: from localhost ([::1]:34912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBFW-0003ei-Tr for importer@patchew.org; Wed, 22 Jul 2020 05:41:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvd-0003de-E3 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:45 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:43111) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvb-0005q2-Cs for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:45 -0400 Received: by mail-pg1-x535.google.com with SMTP id w2so864794pgg.10 for ; Wed, 22 Jul 2020 02:20:42 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7I29w9Yyi3mvfOblF5aq3CVAkBnj/fLwd8DUfu+tXI4=; b=PR470QOCJkLhxZqrs3Q4+wDcgfR4Pq6uU/WeGdXtKumTVdf0lEe1xZ4ftjAbmX5PM2 FbWAYZlkEzRUHZKp2E/MHZXkbJYylPfHAJHsavDrk5pQw/7pQeoQNW+xcrHC0pe34x8w K2/jh1uCFX63XFm4HaDqNSp4oUPlSUoOIiN3D7jV94Yd6zH1v50uUmJWyP3FRoYN91pk VXO9osz+1VdR2jvWy6/Cdip16eUICpwRNmB9tWJyjSAuZF3wAGz5zhgwFGF80TLi2nCr dTAvPN1cyzaXB4mcXBE23VJFxWXJasKjZbFRfBsjlBniSk0sWIRjEoVugTTg8jEfgoag 8gyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7I29w9Yyi3mvfOblF5aq3CVAkBnj/fLwd8DUfu+tXI4=; b=CRslTfvkDwbF09LYpOEFOajaXPvUkVedWemgmaotx5R/7gSlWaCcynFxym6qogeto6 vVUuTgHTkiEuOlq6C4FaeHlcXnUB84zexpyrwDq14SkiIGkNIK9vZWNL3hWJGXihGE0/ ZRRvBicC1LfeuoW0sDotfXO0IZV42mYjOUFoAsnbyU3xWyy3TJL+XsfNeNipVHAc3T+O l0f7sDjIq7FmJwkgaKl//zbOycFsR1jHFmt0xabf5XDxWvyV6Uwx4NlLOWavH7GonNog nsMOubc8/RREr5WDaQYEsdnJBYBBmdKCmf2R2Zv9gftFyJB/p9ouF25PGXvDfTUCXDyP yoHA== X-Gm-Message-State: AOAM5317+NmuDkNIcbSffuZil7mXXM8JpizAP/hyydg9LxOU97DPBC3I BD+yyowaAHR61nbljRDRZB/qfgWv+QQ= X-Google-Smtp-Source: ABdhPJzO1KXlGWIi/QMUnDAVdO1CYeDSCV2bvQv+EamJhNRcn1CKWVk8z1H9oEOVRnNvvcDRIeNh4Q== X-Received: by 2002:a63:8f51:: with SMTP id r17mr26024640pgn.124.1595409641521; Wed, 22 Jul 2020 02:20:41 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions Date: Wed, 22 Jul 2020 17:16:06 +0800 Message-Id: <20200722091641.8834-44-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x535.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 ++++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 87 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 34 ++++++++++ 4 files changed, 143 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1dea171599..7eca91e510 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1097,4 +1097,18 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, pt= r, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) =20 +DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_3(narrower_nanbox_fpr, i64, i64, i32, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0e1d6b3ead..5c31936a92 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -600,5 +600,13 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111= @r2rd vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd =20 +# Vector Integer Extension +vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm +vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm +vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm +vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm +vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm +vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm + vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 85f22a1495..e18ca432b7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3554,3 +3554,90 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) + +static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div) +{ + uint32_t from =3D (1 << (s->sew + 3)) / div; + bool ret =3D require_rvv(s); + ret &=3D (from >=3D 8 && from <=3D 64) && + (a->rd !=3D a->rs2) && + require_align(a->rd, s->flmul) && + require_align(a->rs2, s->flmul / div) && + require_vm(a->vm, a->rd); + if ((s->flmul / div) < 1) { + ret &=3D require_noover(a->rd, s->flmul, a->rs2, s->flmul / div); + } else { + ret &=3D require_noover_widen(a->rd, s->flmul, a->rs2, s->flmul / = div); + } + return ret; +} + +static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq) +{ + uint32_t data =3D 0; + gen_helper_gvec_3_ptr *fn; + TCGLabel *over =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + static gen_helper_gvec_3_ptr * const fns[6][4] =3D { + { + NULL, gen_helper_vzext_vf2_h, + gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d + }, + { + NULL, NULL, + gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vzext_vf8_d + }, + { + NULL, gen_helper_vsext_vf2_h, + gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d + }, + { + NULL, NULL, + gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vsext_vf8_d + } + }; + + fn =3D fns[seq][s->sew]; + if (fn =3D=3D NULL) { + return false; + } + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, 0, + s->vlen / 8, data, fn); + + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + +/* Vector Integer Extension */ +#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (int_ext_check(s, a, DIV)) { \ + return int_ext_op(s, a, SEQ); \ + } \ + return false; \ +} + +GEN_INT_EXT_TRANS(vzext_vf2, 2, 0) +GEN_INT_EXT_TRANS(vzext_vf4, 4, 1) +GEN_INT_EXT_TRANS(vzext_vf8, 8, 2) +GEN_INT_EXT_TRANS(vsext_vf2, 2, 3) +GEN_INT_EXT_TRANS(vsext_vf4, 4, 4) +GEN_INT_EXT_TRANS(vsext_vf8, 8, 5) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1ed0ff6ad..8516570e5f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5002,3 +5002,37 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, c= learb) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq) + +/* Vector Integer Extension */ +#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + HD(i)) =3D *((DTYPE *)vs2 + HS1(i)); \ + } \ + CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +} + +GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1, clearh) +GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2, clearl) +GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4, clearq) +GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1, clearl) +GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2, clearq) +GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1, clearq) + +GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1, clearh) +GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2, clearl) +GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4, clearq) +GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1, clearl) +GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2, clearq) +GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1, clearq) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++++++ target/riscv/insn32.decode | 13 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 5 +- target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 6 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 7eca91e510..11048efe7e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -676,18 +676,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, en= v, i32) DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5c31936a92..0521ca4ab4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -439,11 +439,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 101011= 1 @r_vm vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm -vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm -vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm -vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm +vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm +vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm +vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm +vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm +vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm +vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm +vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index e18ca432b7..d531c4edd1 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2278,10 +2278,13 @@ GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_c= heck) =20 /* Vector Single-Width Averaging Add and Subtract */ GEN_OPIVV_TRANS(vaadd_vv, opivv_check) +GEN_OPIVV_TRANS(vaaddu_vv, opivv_check) GEN_OPIVV_TRANS(vasub_vv, opivv_check) +GEN_OPIVV_TRANS(vasubu_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vaaddu_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) -GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vasubu_vx, opivx_check) =20 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ GEN_OPIVV_TRANS(vsmul_vv, opivv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8516570e5f..aa940080a7 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2652,6 +2652,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq) =20 +static inline uint32_t aaddu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + uint64_t res =3D (uint64_t)a + b; + uint8_t round =3D get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t aaddu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res =3D a + b; + uint8_t round =3D get_round(vxrm, res, 1); + uint64_t over =3D res < a ? ((uint64_t)1 << 63) : 0; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64) +GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64) +GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8, clearq) + static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) { int64_t res =3D (int64_t)a - b; @@ -2688,6 +2725,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq) =20 +static inline uint32_t asubu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + int64_t res =3D (int64_t)a - b; + uint8_t round =3D get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t asubu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res =3D (uint64_t)a - b; + uint8_t round =3D get_round(vxrm, res, 1); + uint64_t over =3D res > a ? ((uint64_t)1 << 63) : 0; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64) +GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1, clearb) +GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2, clearh) +GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64) +GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1, clearb) +GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2, clearh) +GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8, clearq) + /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t= b) { --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411134; cv=none; d=zohomail.com; s=zohoarc; b=OBuAVuHbRX9b3+70+jTzUPm/hXlF32Awxz8rJcu4f7gs75/l0HP0O5dxVFhpxph3hHDwxxduY6XrNzSbl1Y8PuaRwUf6uu4GWhhZgCEgtL3KYiIAnIpBUE08+Kin7yhw2cw3eZGriE5GLyfAcRKeJHpAF2H6RsREkxYwetk5q48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411134; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=WjHpOZhQo9fn4TvBmPBi/s1E299zigQx0QS5Nn+Jx2A=; b=APEvynINkxvBF6NDqtARMcDfJhuiD9XxVUvYkfi59K0pWL9cAhNKkeJUhLbMDIy38ayggTvEd8gQWP1Y5edP95GUKqJWUYFU1owgHejXHuSHfxKvzsLaBkphXbHCjoRXA15YIsYlbaiG23CoCQTBFjx19iXOjh343lDHZgI5DPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411134594539.4055479056373; Wed, 22 Jul 2020 02:45:34 -0700 (PDT) Received: from localhost ([::1]:58574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBJd-0004gX-Aa for importer@patchew.org; Wed, 22 Jul 2020 05:45:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvk-0003vJ-At for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:52 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:34092) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvi-0005rj-PJ for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:52 -0400 Received: by mail-pl1-x630.google.com with SMTP id o1so663768plk.1 for ; Wed, 22 Jul 2020 02:20:50 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:20:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WjHpOZhQo9fn4TvBmPBi/s1E299zigQx0QS5Nn+Jx2A=; b=hy4+5qHmG3bscVR9ymz9XSSLmdj3T8+hCXu0ILL+hfLWVIgUF+f9xdy0CPgaaj3OQT AkB1zyFu56xkSjMWlTOf4W1Cj7vmYnuKvZqYdQw8W1tKDmuoFJUHpM34rWCAOmIrV6Ps hnbjDKqyG5qSP6KJhWzpBr6569SPTIJ5j0MCjV+VeYQijiuWTUMMvI/53XInk3xw5eL+ huhfigAz2JmizvNNY+owM1uhgcGLPxBDexL0x9q0q6s3tF89pzduZ9DbGrbvtavWtDWl uu7A3DgHLBRNeV25cZum01legBzINTX3vewyhSYQpis+2onH8dumDxW7lVDjxu5xvZs6 HHPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WjHpOZhQo9fn4TvBmPBi/s1E299zigQx0QS5Nn+Jx2A=; b=nsoCBL7S/nGFf6v1jqOzgLBgbJp4MDPpJVJEcPFUcI0Kif4vaNOP5YOSOvd76PXXrg NjTDLhAq3KHQra/Pjjnp7f1ZeezfO45Pnbe1DnSUkgf7IiAYUCD2mtYse4gWzTMFVPp1 l9KgSjwxsKZ+oQDW5CyOEAw6DD8/4Bl9YJRkssW0USYZfq+yTD2ZOT7tSazflwHxV0J1 klgr6Thmf8tBC7O34X5AnqNTtpxTdfm+Dx+gi7GdEhw6r3MUEUCi2avMzEhUrpcwDrOO RoSUg1W5/COttosqw2hodTuzo668yFfndDhaSyl4bMwH0KFkKhGgzkPgo8Et0CFzjNzj KG1Q== X-Gm-Message-State: AOAM530NAUPvh8DigJk0UNx9UnjTm+yP0MorzdRezOo6epTIpUvGS7qu lDofTj382ACq/avfEQ8cBAAiNXOeGmE= X-Google-Smtp-Source: ABdhPJzYx14Qs0LXm56kMmpSffBhJiqk1Zz6h5sgIhnC3Mu3NNONuWcS0CKa0G7YNZtszq8iyj3YIA== X-Received: by 2002:a17:902:b682:: with SMTP id c2mr24830046pls.273.1595409649347; Wed, 22 Jul 2020 02:20:49 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions Date: Wed, 22 Jul 2020 17:16:08 +0800 Message-Id: <20200722091641.8834-46-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index d531c4edd1..3998011ef7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1947,9 +1947,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) =20 -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) =20 /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411278; cv=none; d=zohomail.com; s=zohoarc; b=iegmo5ElkU9ZyhLSFRvmWMqCbOA+vT7Zag+epmhk1k1v0TDeppWMOXnfeK9rROKUn42bgcpmA52gYZBQhZwyrXbjvtANS3qPMImPjdI1oJs6qZhIS0VCzxTLhBcSG4FNXG/tVrQmPPe6oORjrIgfsiDKAUFNqtJ0rWQEqYFWUBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411278; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=1G8zWKyeVAzloRYKwSZXE73uroL9SBK5gG0F+v5JF8U=; b=ERzqXzfYn/x9C0FOxGgRFyBzV47g0CEQGn/MjcbR/JRnAzE8yDjipBJIRKVwekAVYKgayKP8Bp+J0GKkCrC/L0VAgDOaf3UkhF6MjT0QikDyPm99gF5IsxzPYmegawbiBdD15j8Rv01DVQUOLocleS+Tfuad+Jn7C4jLizyoo60= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159541127813442.39069285163464; Wed, 22 Jul 2020 02:47:58 -0700 (PDT) Received: from localhost ([::1]:38858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBLu-0008BW-KS for importer@patchew.org; Wed, 22 Jul 2020 05:47:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvp-0004BQ-Qb for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:57 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvm-0005uS-SC for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:20:57 -0400 Received: by mail-pf1-x443.google.com with SMTP id z3so853352pfn.12 for ; Wed, 22 Jul 2020 02:20:54 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 +++++----- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- target/riscv/vector_helper.c | 50 ++++++++++++++----------- 3 files changed, 40 insertions(+), 32 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0521ca4ab4..481f909d47 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -324,16 +324,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 101011= 1 @r_vm vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm -vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 +vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm +vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm +vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm +vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm +vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 3998011ef7..45853812f7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1806,7 +1806,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ =20 /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.3) + * destination vector register is v0 and LMUL > 1. (Section 12.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aa940080a7..95248238df 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1316,24 +1316,28 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC= , clearq) (__typeof(N))(N + M) < N) #define DO_MSBC(N, M, C) (C ? N <=3D M : N < M) =20 -#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ - uint32_t i; \ - \ - for (i =3D 0; i < vl; i++) { \ - ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ - ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - uint8_t carry =3D vext_elem_mask(v0, i); \ - \ - vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ +#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vl =3D env->vl; \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false);\ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { \ + ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ + ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ + uint8_t carry =3D !vm ? vext_elem_mask(v0, i) : 0; \ + \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ + } \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ + } \ } =20 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) @@ -1352,17 +1356,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, \ { \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false);\ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - uint8_t carry =3D vext_elem_mask(v0, i); \ + uint8_t carry =3D !vm ? vext_elem_mask(v0, i) : 0; \ \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ } \ } =20 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411381; cv=none; d=zohomail.com; s=zohoarc; b=U7GvGCb/a8c8Ogqpm8EOy+WF1HMJhCv8uLdSdxUThoZbT8DCmrpj6xCINtEd6RObfjhXc6IsIQ7D3r2CZEzrx95WzNlb/KiRFq4bZZ85P4Y04upTnTBdls/6zxHGQT1XDyZKVtpw8LHm/wIZVeMHefS+cbOFR2e4SKDbVdmdK9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411381; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=eOba8Tk0Biv7SLGf/daURGXR2aaUs/Gp2nVqvWqB5qE=; b=gKb2CshbCMLXZKg9dJpbGir+mQD3eRP95Hv3xrDDKGCraIMUvxX/hhe0YD/W9tt34huJBgds74SsUNLOMTdMr+nBe6eY5iRPGnvXOX4odt6PUZKtW7oWtgOCLR/a8OBy2Aw2nc2drPCBHoIyK/OGlWu3djF3NLPgkBJKhAb/3QY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411381958937.5961063376533; Wed, 22 Jul 2020 02:49:41 -0700 (PDT) Received: from localhost ([::1]:47360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBNc-0003CK-K8 for importer@patchew.org; Wed, 22 Jul 2020 05:49:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAvu-0004Nw-AO for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:02 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvq-0005xY-U7 for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:01 -0400 Received: by mail-pg1-x52c.google.com with SMTP id d4so880088pgk.4 for ; Wed, 22 Jul 2020 02:20:58 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++++++++++---------- target/riscv/insn32.decode | 12 +++++----- target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++------------- target/riscv/vector_helper.c | 24 ++++++++++---------- 4 files changed, 45 insertions(+), 45 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 11048efe7e..02258b42d1 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -379,18 +379,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env,= i32) DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 -DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32) =20 DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 481f909d47..bc6c788edf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -352,12 +352,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 101011= 1 @r_vm vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm -vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm -vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm -vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm -vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm -vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm -vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm +vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm +vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm +vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm +vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm +vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm +vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 45853812f7..451931492d 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1952,7 +1952,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx,= shri) GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) =20 /* Vector Narrowing Integer Right Shift Instructions */ -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1960,10 +1960,10 @@ static bool opivv_narrow_check(DisasContext *s, arg= _rmrr *a) } =20 /* OPIVV with NARROW */ -#define GEN_OPIVV_NARROW_TRANS(NAME) \ +#define GEN_OPIWV_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivv_narrow_check(s, a)) { \ + if (opiwv_narrow_check(s, a)) { \ uint32_t data =3D 0; \ static gen_helper_gvec_4_ptr * const fns[3] =3D { \ gen_helper_##NAME##_b, \ @@ -1987,10 +1987,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ } \ return false; \ } -GEN_OPIVV_NARROW_TRANS(vnsra_vv) -GEN_OPIVV_NARROW_TRANS(vnsrl_vv) +GEN_OPIWV_NARROW_TRANS(vnsra_wv) +GEN_OPIWV_NARROW_TRANS(vnsrl_wv) =20 -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1998,10 +1998,10 @@ static bool opivx_narrow_check(DisasContext *s, arg= _rmrr *a) } =20 /* OPIVX with NARROW */ -#define GEN_OPIVX_NARROW_TRANS(NAME) \ +#define GEN_OPIWX_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] =3D { = \ gen_helper_##NAME##_b, \ gen_helper_##NAME##_h, \ @@ -2012,14 +2012,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ return false; \ } =20 -GEN_OPIVX_NARROW_TRANS(vnsra_vx) -GEN_OPIVX_NARROW_TRANS(vnsrl_vx) +GEN_OPIWX_NARROW_TRANS(vnsra_wx) +GEN_OPIWX_NARROW_TRANS(vnsrl_wx) =20 -/* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ +/* OPIWI with NARROW */ +#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] =3D { = \ gen_helper_##OPIVX##_b, \ gen_helper_##OPIVX##_h, \ @@ -2031,8 +2031,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ return false; \ } =20 -GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx) +GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx) +GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx) =20 /* Vector Integer Comparison Instructions */ /* diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 95248238df..7de858d65b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1515,18 +1515,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, = H4, DO_SRL, 0x1f, clearl) GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clear= q) =20 /* Vector Narrowing Integer Right Shift Instructions */ -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, cle= arb) -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, cl= earh) -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, cl= earl) -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clea= rb) -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, cle= arh) -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, cle= arl) -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clea= rb) -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, cl= earh) -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, cl= earl) -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clea= rh) -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clea= rl) +GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, cle= arb) +GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, cl= earh) +GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, cl= earl) +GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clea= rb) +GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, cle= arh) +GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, cle= arl) +GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clea= rb) +GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, cl= earh) +GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, cl= earl) +GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) +GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clea= rh) +GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clea= rl) =20 /* Vector Integer Comparison Instructions */ #define DO_MSEQ(N, M) (N =3D=3D M) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bc6c788edf..c6a7145aa5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -420,9 +420,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 = @r_vm vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm -vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm +vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411510; cv=none; d=zohomail.com; s=zohoarc; b=FC8JV6QXgvlFz9cAB06rseroJoIZGdF9x4t1D6SU7RSpOnMkX9QH4loWH/tmUUEHJlici/mFdrZ5vLidAU8WEEwYjbl6gDPFrZ7eBUfXx/dxqG5UpIFciGJTZdBKsMvjXLHNTtlPZPybjOz6NFSTbHLTtzfK/W3ykGeffxiA/P0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411510; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=wwBItfECgJTIuDe5vvyT8sv2Edy6E2QEMOkmqSFHsbw=; b=dRiAQFKwR5Kh9EvuTeZvnD5FC4RWqkkVQVTbxhr6SL5QGTPqicRbtP99fvNzHz9vsbJow3yLQ1Obd56EK7/C9XBtmXc8HG4ryCXK0ehvfOWAecF2BnOqSbPxPmcpOXN1ltnz9FKEbAcQ4OG3rNAOYHLyFm4fphqrC7iZo/Y4Z2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411510289832.9447088388166; Wed, 22 Jul 2020 02:51:50 -0700 (PDT) Received: from localhost ([::1]:56360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBPg-0006tt-Vz for importer@patchew.org; Wed, 22 Jul 2020 05:51:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAw2-0004j4-RK for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:10 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:55330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAvz-00060A-BI for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:10 -0400 Received: by mail-pj1-x102d.google.com with SMTP id k1so863426pjt.5 for ; Wed, 22 Jul 2020 02:21:06 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wwBItfECgJTIuDe5vvyT8sv2Edy6E2QEMOkmqSFHsbw=; b=Gjah03D70LqulALHsVfmthz9P2hDKg24AU+Oa0NpS7YnLccC2kEuycbO2OLVLhMm4t r08i7O+YRgvv4P9qUP6Y2M3l/fVEZ3WIRKxcf1ruKmBH6rEHVSVsf3KQpAxn1+iKsGvd AZEPiX9TnqcP5hjvfLL0hqfLro0jP5/DASxltiwPLtLjuLQL4lH9/MTMvPOVZGcqgHqh qHgugshIRLqiy0btF+cyerSLvsPvUEENLi1lWvzpksodpc7Rf6Hv9+FxwdgyKZoxeMPS txy/S2c0y+wtJsX65OG3u3f0NsRa9wO5jtjCbS4+VNPO9k3Fp5aN4iNvFpSzmFzgC8k3 CZeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wwBItfECgJTIuDe5vvyT8sv2Edy6E2QEMOkmqSFHsbw=; b=nFkin1BjPeVvOSojDNDMkT6n3YpZJp29Tn+/VayfwFSv9rx7aJxZCH1WPdmqlDWaFJ Bg0v4ABZU4v5UHJXpDmd9HEJyZwnrWBAzsFg2At3u8IHgR4uawvEac0ILRPDVXzeNqOA nSkxkNyAYeQbjosIAs5x3D1Uvdqd2LiQETBPiwIKbMPd/hpA0iBNsDB939Q1Fq3ajtQf /FPW0KgalgoSnyHKufHPyU8a9Cv34y1E1Cum5aFmsYfZsZMRwzTGoGmIE5UCimuMo6p2 +FeXPZ9/+4Sg7LKh3yEeHc9hb5F31HIj02scoKgR7NnnaQQ8Z93LFVKWbWig0UdtmURD pGCw== X-Gm-Message-State: AOAM530EQbX/9u05yxLPcrBR6RUHeLI/yZbOKQmDEtR351rOa0DWGQGg bV1ddgzjlsJ6MBPqUpmpXp3QX8/l8BQ= X-Google-Smtp-Source: ABdhPJxji5KB6KXHAv/dSYTUltJGvRTYh1U96MgHsNgW3LFtCv2C19i/J92sKxZSCxzuOguRc9GfeA== X-Received: by 2002:a17:902:7241:: with SMTP id c1mr26687236pll.79.1595409665334; Wed, 22 Jul 2020 02:21:05 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions Date: Wed, 22 Jul 2020 17:16:12 +0800 Message-Id: <20200722091641.8834-50-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vqmaccu.vv * vqmaccu.vx * vqmacc.vv * vqmacc.vx * vqmaccsu.vv * vqmaccsu.vx * vqmaccus.vx Signed-off-by: Frank Chang --- target/riscv/helper.h | 15 ++++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 101 ++++++++++++++++++++++++ target/riscv/vector_helper.c | 40 ++++++++++ 4 files changed, 163 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 02258b42d1..b8a436d3aa 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -622,6 +622,21 @@ DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, e= nv, i32) DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) =20 +DEF_HELPER_6(vqmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vqmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vqmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) + DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c6a7145aa5..acd65cb3a7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -423,6 +423,13 @@ vwmacc_vx 111101 . ..... ..... 110 ..... 1010111= @r_vm vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm +vqmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm +vqmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm +vqmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm +vqmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm +vqmaccsu_vv 111111 . ..... ..... 000 ..... 1010111 @r_vm +vqmaccsu_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm +vqmaccus_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 451931492d..956ee90745 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -453,6 +453,52 @@ static bool vext_check_dss(DisasContext *s, int vd, in= t vs1, int vs2, return ret; } =20 +/* + * Check function for vector instruction with format: + * quad-width result and single-width sources (4*SEW =3D SEW op SEW) + * + * is_vs1: indicates whether insn[19:15] is a vs1 field or not. + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * =3D> LMUL < 4. + * =3D> SEW < 32. + * 2. Destination vector register number is multiples of 4 * LMUL. + * (Section 3.3.2) + * 3. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.3.2) + * 4. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + * 5. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_check_qss(DisasContext *s, int vd, int vs1, int vs2, + int vm, bool is_vs1) +{ + bool ret =3D (s->flmul <=3D 2) && + (s->sew < 2) && + require_align(vd, s->flmul * 4) && + require_align(vs2, s->flmul) && + require_vm(vm, vd); + if (s->flmul < 1) { + ret &=3D require_noover(vd, s->flmul * 4, vs2, s->flmul); + } else { + ret &=3D require_noover_widen(vd, s->flmul * 4, vs2, s->flmul); + } + if (is_vs1) { + ret &=3D require_align(vs1, s->flmul); + if (s->flmul < 1) { + ret &=3D require_noover(vd, s->flmul * 4, vs1, s->flmul); + } else { + ret &=3D require_noover_widen(vd, s->flmul * 4, vs1, s->flmul); + } + } + return ret; +} + /* * Check function for vector instruction with format: * double-width result and double-width source1 and single-width @@ -2134,6 +2180,61 @@ GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) =20 +/* Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqma= c) */ +/* OPIVV with QUAD-WIDEN */ +static bool opivv_quad_widen_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_qss(s, a->rd, a->rs1, a->rs2, a->vm, true); +} + +#define GEN_OPIVV_QUAD_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_gvec_4_ptr * const fns[2] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h \ + }; \ + return do_opivv_widen(s, a, fns[s->sew], CHECK); \ +} + +GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccu_vv, opivv_quad_widen_check) +GEN_OPIVV_QUAD_WIDEN_TRANS(vqmacc_vv, opivv_quad_widen_check) +GEN_OPIVV_QUAD_WIDEN_TRANS(vqmaccsu_vv, opivv_quad_widen_check) + +/* OPIVX with QUAD-WIDEN */ +static bool opivx_quad_widen_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_qss(s, a->rd, a->rs1, a->rs2, a->vm, false); +} + +static bool do_opivx_quad_widen(DisasContext *s, arg_rmrr *a, + gen_helper_opivx *fn) +{ + if (opivx_quad_widen_check(s, a)) { + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + } + return false; +} + +#define GEN_OPIVX_QUAD_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[3] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h \ + }; \ + return do_opivx_quad_widen(s, a, fns[s->sew]); \ +} + +GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccu_vx) +GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx) +GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx) +GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx) + /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7de858d65b..420c5f675d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2121,6 +2121,46 @@ GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq) =20 +/* Vector Quad-Widening Integer Multiply-Add Instructions */ +#define QOP_UUU_B uint32_t, uint8_t, uint8_t, uint32_t, uint32_t +#define QOP_UUU_H uint64_t, uint16_t, uint16_t, uint64_t, uint64_t +#define QOP_SSS_B int32_t, int8_t, int8_t, int32_t, int32_t +#define QOP_SSS_H int64_t, int16_t, int16_t, int64_t, int64_t +#define QOP_SUS_B int32_t, uint8_t, int8_t, uint32_t, int32_t +#define QOP_SUS_H int64_t, uint16_t, int16_t, uint64_t, int64_t +#define QOP_SSU_B int32_t, int8_t, uint8_t, int32_t, uint32_t +#define QOP_SSU_H int64_t, int16_t, uint16_t, int64_t, uint64_t + +RVVCALL(OPIVV3, vqmaccu_vv_b, QOP_UUU_B, H4, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vqmaccu_vv_h, QOP_UUU_H, H8, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vqmacc_vv_b, QOP_SSS_B, H4, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vqmacc_vv_h, QOP_SSS_H, H8, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vqmaccsu_vv_b, QOP_SSU_B, H4, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vqmaccsu_vv_h, QOP_SSU_H, H8, H2, H2, DO_MACC) +GEN_VEXT_VV(vqmaccu_vv_b, 1, 4, clearl) +GEN_VEXT_VV(vqmaccu_vv_h, 2, 8, clearq) +GEN_VEXT_VV(vqmacc_vv_b, 1, 4, clearl) +GEN_VEXT_VV(vqmacc_vv_h, 2, 8, clearq) +GEN_VEXT_VV(vqmaccsu_vv_b, 1, 4, clearl) +GEN_VEXT_VV(vqmaccsu_vv_h, 2, 8, clearq) + +RVVCALL(OPIVX3, vqmaccu_vx_b, QOP_UUU_B, H4, H1, DO_MACC) +RVVCALL(OPIVX3, vqmaccu_vx_h, QOP_UUU_H, H8, H2, DO_MACC) +RVVCALL(OPIVX3, vqmacc_vx_b, QOP_SSS_B, H4, H1, DO_MACC) +RVVCALL(OPIVX3, vqmacc_vx_h, QOP_SSS_H, H8, H2, DO_MACC) +RVVCALL(OPIVX3, vqmaccsu_vx_b, QOP_SSU_B, H4, H1, DO_MACC) +RVVCALL(OPIVX3, vqmaccsu_vx_h, QOP_SSU_H, H8, H2, DO_MACC) +RVVCALL(OPIVX3, vqmaccus_vx_b, QOP_SUS_B, H4, H1, DO_MACC) +RVVCALL(OPIVX3, vqmaccus_vx_h, QOP_SUS_H, H8, H2, DO_MACC) +GEN_VEXT_VX(vqmaccu_vx_b, 1, 4, clearl) +GEN_VEXT_VX(vqmaccu_vx_h, 2, 8, clearq) +GEN_VEXT_VX(vqmacc_vx_b, 1, 4, clearl) +GEN_VEXT_VX(vqmacc_vx_h, 2, 8, clearq) +GEN_VEXT_VX(vqmaccsu_vx_b, 1, 4, clearl) +GEN_VEXT_VX(vqmaccsu_vx_h, 2, 8, clearq) +GEN_VEXT_VX(vqmaccus_vx_b, 1, 4, clearl) +GEN_VEXT_VX(vqmaccus_vx_h, 2, 8, clearq) + /* Vector Integer Merge and Move Instructions */ #define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=luapOFzm51xYRtzAj/W9SIi2lVG0a4XONIdVgpZBqII=; b=abQtfsOlpyA8C700Pth9hYwSb9dnPwgWP6K6Mzm6RLt2FH7ohMq6TXaRzksnPC2MnR IjRzFJY/TuDqyMnLXg/3fpwTiROsp8AdRhWkho5SnPTNwjk/+2c4ZO5rvKPDjarAn8HA ZCQ9xR9dw00gVLZGoqfq/hXSgDwr7lQR86QFqZlZbubnxat8K7XqnShPyuegnGyZZKBq q9pkrHFnGlSw99UsBBPHITg7N7AbOvVTgjFRGyKg2OvjbVBC2uCYHLWgnvUcFHyCmYcC F1HXzyfG1EieM1YSs6RLOdUwQ6JhFnu6ZEhkl1ZJY2G6PScXI1+uy3zXJwpLfEUkfijl QSVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=luapOFzm51xYRtzAj/W9SIi2lVG0a4XONIdVgpZBqII=; b=Vx98pTdeVBkyi3eFmZeHZEwK1M0Z2imbjzHxb8zNrWV348zzRFRj3pzDqjhLYTF1Xk QsAMgItZGyal76v4Cfv4/DtX6u5h+q4qazuxc8cZbgbRla6R+DTUexJ4xfVLg5UKGNd+ oGB47V+ZUBk1UfFUG1opFogb2wj29HPvzUPSfrQoX0z8g9CMYOcM7QnY2j7jMiB4fQs2 mDDH5Fn0OX7FhcsjzX7Z0wxP+Wj8CNS+yNqWTtlO8IGTWgnEOUCoIsRMKnshc8YnY0jF QF0OMJMqWMXJztI6L6FOv8ZSMVTnJO9n43LbEiKDqFi8iIT6REWdNBKiZwiltGCgMST8 jXkw== X-Gm-Message-State: AOAM532EDFDv6Rj2fGfPC+1D8a55E9cVOthPUGb0SzEy4FfdFKJQvjS2 KMuRJLZdB3W942bLv/9MQbrcqv4Vcbw= X-Google-Smtp-Source: ABdhPJxkxMPLAgYECMJKHdSBA6RtbOlCibPEKbKxQHoJ6zSSB5UsJYvthCZcx68j1zrxwzjMCKs55g== X-Received: by 2002:a17:90a:800b:: with SMTP id b11mr9119062pjn.105.1595409669044; Wed, 22 Jul 2020 02:21:09 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions Date: Wed, 22 Jul 2020 17:16:13 +0800 Message-Id: <20200722091641.8834-51-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x631.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 956ee90745..3018489536 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2374,7 +2374,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) GEN_OPIVX_TRANS(vsadd_vx, opivx_check) GEN_OPIVX_TRANS(vssubu_vx, opivx_check) GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check) GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) =20 /* Vector Single-Width Averaging Add and Subtract */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411603; cv=none; d=zohomail.com; s=zohoarc; b=NQYVP+bWG0cJZ3/PhXAWPjHW66Ea+bKJEVTH1xgkvLc5Q247lL11jc+5h35ztutKiFInLau0+T565lsZMvCUnWRbv7IuYif1QZY7u4B2dItOLwWQQ41nJwfKZSZuNBWAUIAHuD8OTpud02mc38SID91FmEUklSZ94XmhZHibpmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411603; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=uszXZkWPs2BCvFrrB1JthqoxvCbuVc0XI1W65Psr/2M=; b=XcvTGC4orcq/MLPHHPtsjneqlxtHbViIxqZSHBIn9Oui07zG8sBIX/RFaefPeYqrPJEBk5eE/6JyA6fNVwyaeHOQv/yPqsS7NczGs9DkEIoyNzzVV9L8SSUzgaePKywwdBhuQc37Tve4PoNOW+hn9abS84U+j15LwjT8Hqs3hxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411603040585.6279180128535; Wed, 22 Jul 2020 02:53:23 -0700 (PDT) Received: from localhost ([::1]:36560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBRB-0001rx-Kr for importer@patchew.org; Wed, 22 Jul 2020 05:53:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAw8-0004yU-NB for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:16 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:43113) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAw6-00061F-JZ for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:16 -0400 Received: by mail-pg1-x535.google.com with SMTP id w2so865498pgg.10 for ; Wed, 22 Jul 2020 02:21:14 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Sign-extend vmselu.vi and vmsgtu.vi immediate values. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 4 +- target/riscv/vector_helper.c | 86 +++++++++++++------------ 2 files changed, 48 insertions(+), 42 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 3018489536..378af8344d 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2118,9 +2118,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) =20 GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check) =20 /* Vector Integer Min/Max Instructions */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 420c5f675d..dc883e0352 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1535,26 +1535,29 @@ GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4,= H8, DO_SRL, 0x3f, clearl) #define DO_MSLE(N, M) (N <=3D M) #define DO_MSGT(N, M) (N > M) =20 -#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ - uint32_t i; \ - \ - for (i =3D 0; i < vl; i++) { \ - ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ - ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ +#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { \ + ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ + ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ + } \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ + } \ } =20 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) @@ -1587,26 +1590,29 @@ GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE) GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE) GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) =20 -#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ - uint32_t i; \ - \ - for (i =3D 0; i < vl; i++) { \ - ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - vext_set_elem_mask(vd, i, \ - DO_OP(s2, (ETYPE)(target_long)s1)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ +#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { \ + ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + vext_set_elem_mask(vd, i, \ + DO_OP(s2, (ETYPE)(target_long)s1)); \ + } \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ + } \ } =20 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410929; cv=none; d=zohomail.com; s=zohoarc; b=JFArl5Pu7AfZTZ9ibdJru/3sWuoglqci1DhKzb2Mzg4FDBCvpzoGg+/9Fi7Uh9vQqNSd1Ma76o4kMOGgU+0OdENx+mW+7SyTac+3AV2zfWAA84fCp+RoVzyGF3Z7OpqIH1Lll+oD4DU1fHIuC7uOHvbWseU7eQH6+h+6jDfNaIE= ARC-Message-Signature: i=1; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rgRsumD+WyP+g+9ywiEhwYNS2OqBdlvEKjanU4B1RZU=; b=LtE6qf826ci3D7L3stHnLZ4IxQdcpNzXYKRjHxlMvlmy0w/BWZKmndqxLcrbOn5HVq z6e0pZnvfB2ErKm2AYLU/1yv3EBGifBf8MOBWYK0lwrZ7afkb1hCui08Mp4nloXrPknf tsf31SZjQDjYVaJtez8q+OoLMBBHrlkE+I+eU+pH3YnSeRACpkmtakgpoD0QrkMjn1UN GNGGyrKUIFz9l3MTabNXCwd6P3nU8N9/sBTs/fqCOqFJwUsDOjJUm2ZPPUQEfu0JItCA A6ojSUd8cjYOhQTOVoDuE74vY4SJquFecQWrmzdM9LSBSbccBj6E/6lchEHNz3oANly0 l4Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rgRsumD+WyP+g+9ywiEhwYNS2OqBdlvEKjanU4B1RZU=; b=HdNsJifTtp3Rr7FEHQD1KsF/EQShYG4hkqSLmBSOleSpJTTbU7koYb7c2PGn2Tm/jU lzDRMS5VNdKxVnhBS0yaLAYOfVKFWWfylOG3zmHhBGxW9vLcpGIJjjDnWAb7sQIX0Yuc qw4rWP9zSFbNM3WBFzxS+CuulCXuk9wKI7e0jfWBBWgfvv0GJQlkeiwKIklzv3WhMePH rovqKU3vGCHFsATC1Z+pGjYRMvHivLvXtwRyI3Ix+bagOBkra/+MC8PhK+PjxMXQMhVp a209IogWDRPOK+JPWeNyCMb+Dp8pNT3bPy4nRUCyBFAtB2Bugr5mP+jPr4BImiSRTPHJ 1uSA== X-Gm-Message-State: AOAM532LP49Kv4VLoWuhVHFM3D/F11nyA/Zeen2qZv6ZANYLXweOSodS UPFadLzBMCAnj01m5jnDadUIwPFXQaM= X-Google-Smtp-Source: ABdhPJzJAg1FBZ5yz5oMup7bXnqJFltT2P+fmSTrDrZimyZiFP4rPJJmx+/D7S2I3Q6KZ1MpVr91eg== X-Received: by 2002:a62:1ad6:: with SMTP id a205mr27235306pfa.109.1595409676608; Wed, 22 Jul 2020 02:21:16 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 52/76] fpu: implement full set compare for fp16 Date: Wed, 22 Jul 2020 17:16:15 +0800 Message-Id: <20200722091641.8834-53-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Frank Chang , Chih-Min Chao , Kito Cheng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Acked-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 28 ++++++++++++++++++++++++++++ include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 79be4f5840..9c6640862e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s, return soft(ua.s, ub.s, s); } =20 +/*------------------------------------------------------------------------= ---- +| Returns the fraction bits of the half-precision floating-point value `a'. +*-------------------------------------------------------------------------= ---*/ + +static inline uint32_t extractFloat16Frac(float16 a) +{ + return float16_val(a) & 0x3ff; +} + +/*------------------------------------------------------------------------= ---- +| Returns the exponent bits of the half-precision floating-point value `a'. +*-------------------------------------------------------------------------= ---*/ + +static inline int extractFloat16Exp(float16 a) +{ + return (float16_val(a) >> 10) & 0x1f; +} + +/*------------------------------------------------------------------------= ---- +| Returns the sign bit of the half-precision floating-point value `a'. +*-------------------------------------------------------------------------= ---*/ + +static inline bool extractFloat16Sign(float16 a) +{ + return float16_val(a) >> 15; +} + + /*------------------------------------------------------------------------= ---- | Returns the fraction bits of the single-precision floating-point value `= a'. *-------------------------------------------------------------------------= ---*/ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index ff4e2605b1..267519cd65 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int = sign) return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); } =20 +static inline bool float16_eq(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) =3D=3D float_relation_equal; +} + +static inline bool float16_le(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) <=3D float_relation_equal; +} + +static inline bool float16_lt(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) =3D=3D float_relation_unordered; +} + +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) =3D=3D float_relation_equal; +} + +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) <=3D float_relation_equal; +} + +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered_quiet(float16 a, float16 b, + float_status *s) +{ + return float16_compare_quiet(a, b, s) =3D=3D float_relation_unordered; +} + #define float16_zero make_float16(0) #define float16_half make_float16(0x3800) #define float16_one make_float16(0x3c00) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index dc883e0352..95cce063d0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4197,12 +4197,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ } \ } =20 -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare =3D float16_compare_quiet(a, b, s); - return compare =3D=3D float_relation_equal; -} - GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) @@ -4258,12 +4252,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) =20 -static bool float16_lt(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare =3D float16_compare(a, b, s); - return compare =3D=3D float_relation_less; -} - GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) @@ -4271,13 +4259,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) =20 -static bool float16_le(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare =3D float16_compare(a, b, s); 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 52 ++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 95cce063d0..8dccec4e04 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4174,27 +4174,30 @@ GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl) GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) =20 /* Vector Floating-Point Compare Instructions */ -#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t vlmax =3D vext_maxsz(desc) / sizeof(ETYPE); \ - uint32_t i; \ - \ - for (i =3D 0; i < vl; i++) { \ - ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ - ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - vext_set_elem_mask(vd, i, \ - DO_OP(s2, s1, &env->fp_status)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ +#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { \ + ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ + ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + vext_set_elem_mask(vd, i, \ + DO_OP(s2, s1, &env->fp_status)); \ + } \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ + } \ } =20 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) @@ -4208,6 +4211,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D 0; i < vl; i++) { \ @@ -4218,8 +4222,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, v= oid *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ } \ } =20 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595410722; cv=none; d=zohomail.com; s=zohoarc; b=PLk0Pp4pi7KxQuWzdt+tsdrckMpep7U4lWV1ExGuHF+YvrCmExgKJ2RabDfWsSaDgKX8RAlZl6MXlMlpbee4lUcLlGznnZ+PO84t2uW3v0YBPb7nWChepI6H07Zqfm2/U0MAcfqK28muwFttTPxJrttho8pAAWrGnKfjYRJuPjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595410722; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Y2KhL2jx26SA0fTdqwK4kIep/hAoNdtUzmiGc3hCqv0=; b=DqOqF/dHRttHDO/4ZXMvQocFJVj5mVc8V62lginwYRugms+XausOkFyemW12Bj4a4XNjpXlxMDc8Pm1YW7SzzyUOc4hitvupS+Fb7jYzqxwD4PcJxJWoiybPF+9QRKbypRHx+McwYxlWvGEyUWQSCA88NrSE0ekVhGouXDJcLlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595410722603401.03819049794083; Wed, 22 Jul 2020 02:38:42 -0700 (PDT) Received: from localhost ([::1]:49842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBCz-0006fH-DF for importer@patchew.org; Wed, 22 Jul 2020 05:38:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAwO-0005ax-8V for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:32 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:35261) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAwM-00064S-Fl for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:31 -0400 Received: by mail-pf1-x442.google.com with SMTP id a14so878277pfi.2 for ; Wed, 22 Jul 2020 02:21:30 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Remove clear function from helper function as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 69 +++++++++++++++++------------------- 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8dccec4e04..39245b5ac8 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4565,15 +4565,13 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) *** Vector Reduction Operations */ /* Vector Single-Width Integer Reduction Instructions */ -#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ - uint32_t vta =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ - uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; \ TD s1 =3D *((TD *)vs1 + HD(0)); \ \ for (i =3D 0; i < vl; i++) { \ @@ -4584,56 +4582,55 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ s1 =3D OP(s1, (TD)s2); \ } \ *((TD *)vd + HD(0)) =3D s1; \ - CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \ } =20 /* vd[0] =3D sum(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb) -GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh) -GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl) -GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq) +GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD) +GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD) +GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD) +GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD) =20 /* vd[0] =3D maxu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX) =20 /* vd[0] =3D max(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX) =20 /* vd[0] =3D minu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN) =20 /* vd[0] =3D min(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN) =20 /* vd[0] =3D and(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb) -GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh) -GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl) -GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq) +GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND) +GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND) +GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND) +GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND) =20 /* vd[0] =3D or(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb) -GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh) -GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl) -GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq) +GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR) +GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR) +GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR) +GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR) =20 /* vd[0] =3D xor(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) -GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) -GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) -GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) +GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR) +GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR) +GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR) +GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR) =20 /* Vector Widening Integer Reduction Instructions */ /* signed sum reduction into double-width accumulator */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k/bbYZMF5KJp5b3HZ5BM8JAnwaOB46w118MIToz3Xrg=; b=ihOnf8IbSm+ohMq99dU54kGjjWHbl99ykFtKv7tYcl9hYSRFuNONOd2q4OaIrMNUoD lA4rhvAxKnGMWZNGrkA2eGX5hViuK/d/Z57nMh873jyPCrWR38mW8L4rAWj8shDCDQeL XjfeGoKwFH2qb0mcSLpG0EwXjSxri8y9F8NSS0QhgaO+47bF5HSgiSYWy4lB9LF0ir1a z9eS0Gb6omLZrdx1G/mMrheNamTeWjq2W99qENylQJQDzbkLwlsyx2DL92wHpbPFJcUz S7XU2fzJ7h/dBk4rcj+tIMHQzDuKrELyt9AdKsHDr8XmKuYnD/W/voHJQU9YQ7Q8Xro+ jIYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k/bbYZMF5KJp5b3HZ5BM8JAnwaOB46w118MIToz3Xrg=; b=sa7ywvF2xasrCL0E798cVp+7Q4LJPJYoXG+H+H1k0UjhBRLNxC4LkWxZyyPn7O01xt EY2D7Cr+mU2y9QBCaK7cuBiKTqMpVudAH5qj/arLbhR3fA9RCy/dKuQZoc+Zz/1rJnsR YkpgK+/ewjjVcmFb7j2yXmgXvjQ/Ffp8IUVFbkcS3KGa4b23YcpaMf/10oq5bok2t3Ir VRnFlXnLhO/DHn3WPLAgFEgV3vNjygyEV2e2ND4ZOou/9GdsTGPZvFZKCd2fpe4HX6UL eEGOaToJkkbhH6fx9Z8hX5tlaWFc6oHbJznzMhCf+QecjinZRZUwPblA1XnHe38ZsePU VBJg== X-Gm-Message-State: AOAM532SYpxZ9rZ19gG5R7HQD9e8+rBLxtA7ZBGelgxGdck7tpi4nahB RgSlZ5XvOT4ItUnv/yOK0CndKDpr3AM= X-Google-Smtp-Source: ABdhPJzCpObdv0jSauMJ3gK7jpJXU/3KwcNgW94h2LD6irmNXXawY9UdneaJV0D2Atmjt/KeLV8OLQ== X-Received: by 2002:a17:902:b102:: with SMTP id q2mr23695082plr.343.1595409692421; Wed, 22 Jul 2020 02:21:32 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions Date: Wed, 22 Jul 2020 17:16:19 +0800 Message-Id: <20200722091641.8834-57-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Remove clear function from helper function as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39245b5ac8..fa2459d941 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4634,14 +4634,14 @@ GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8= , DO_XOR) =20 /* Vector Widening Integer Reduction Instructions */ /* signed sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD) =20 /* Unsigned sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ #define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411079; cv=none; d=zohomail.com; s=zohoarc; b=YJzNYJCvi1xASceQKHNCVqFF1IqR4trbHVASYeM0fqWTiAqlPmTsfp3JyBQUu1Sx//ovUOP1V246iJBlKyrTPec8xlsJ+VpyszKM78f7FKBRpWgDud9PGkUvcaXxyeBvp4b8bSa08VUtB6MzF0+36TasC5S4chv6nhLqEMEEYpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411079; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=OUSvqk8N0OEsedcBlB/CQ0Og2x6aYFwr+QYiYEPQ0xY=; b=lbqpLn6CF5rwMhrWp/NBrNqRfWxchidsIycu9BiDRjRuHjFV9lk79SUHp7Y1MCR7L8/22HGjH63sPl87rRmFgh5ZcX0Qx/9t7lCv4WqtolCsE2OHUoaQoVbtkVcx1Fq7csCQbSSdk8ASH0xyA0DUXQ/+zorFv2FI2V6tCsR43ZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411079026497.49675517803905; Wed, 22 Jul 2020 02:44:39 -0700 (PDT) Received: from localhost ([::1]:53406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBIj-0002bi-OR for importer@patchew.org; Wed, 22 Jul 2020 05:44:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAwV-0005uG-Pz for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:39 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:33164) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAwT-00065C-Os for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:39 -0400 Received: by mail-pj1-x102f.google.com with SMTP id gc15so2631737pjb.0 for ; Wed, 22 Jul 2020 02:21:37 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 3 ++- target/riscv/vector_helper.c | 7 +++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 378af8344d..5004707b87 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3023,7 +3023,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) #define GEN_MM_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_r *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s)) { \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fa2459d941..bb426e224c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4738,6 +4738,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t desc) \ { \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; \ + uint32_t vta =3D vext_vta(desc); \ uint32_t vl =3D env->vl; \ uint32_t i; \ int a, b; \ @@ -4747,8 +4748,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ b =3D vext_elem_mask(vs2, i); \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ + if (vta =3D=3D 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ } \ } =20 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411200; cv=none; d=zohomail.com; s=zohoarc; b=JKZSo4wrMBA7oZf+K+z3IhlfUWSVl8+fq8k9DRYzM+7LvABOjxPV8UM+2QogxGrsPeDRH+ZLICh/lXnc4Jvx+6qKN9jJVfCcgn8lelj+8nxZQSwq6jN/HUpWjVpRikMj2/M+NovdMYJmkXT+WOwPd+8zSCg60bMNY8Zj+fo/gAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411200; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=gpep5/nDCBjR2xblMkuotvD31Bl23GAVCnm9qzFyGGI=; b=PiWwj5OvtdDgShe8xRJwmimX+gxELsHJzu4EO6MZho7ydtK7syVvmrIQANfz2dzpZf0wksf0yLTC6BxcRhxxHnBxfQZiOxrGalm7+IbjjduJVvHcUz3+Aur4HoGAEMtKrXEx3UAyOE1WA+5RBoneaecIltSeZEeLdJ7Pwjb1M3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159541120060632.78460517212682; Wed, 22 Jul 2020 02:46:40 -0700 (PDT) Received: from localhost ([::1]:33614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBKh-00065g-6I for importer@patchew.org; Wed, 22 Jul 2020 05:46:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAwa-00066r-GT for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:44 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:39294) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAwX-00065m-Bj for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:21:44 -0400 Received: by mail-pj1-x1031.google.com with SMTP id b92so867478pjc.4 for ; Wed, 22 Jul 2020 02:21:40 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gpep5/nDCBjR2xblMkuotvD31Bl23GAVCnm9qzFyGGI=; b=Rt0vzosm8vkfV3oPflNIgTAijlsLlsvLhfVmff/nMW/pxnHPtEWsJ72CVC13WwsiIe IdhggjQdAyGF+iXclJJVhGq/r1bbHhyWnpdhh76FQ+UOY+rM8yWzQPBUaU37are0yQXo WYQGJkT2GA8ikhAybdC9J18V8H5EZh0U655gOWVDZu6OcEPCivjRwQJ4a1It+Ab3xPeC WdTtTBaz4u9pDrwt4L+LbWd2Vjs1wYw5+QSjsGls+D7kugxejNZPkF5TQ3KUcIXIf+Ef GoxrQiKRZUCgUOc8dLU/O14AqIJ+frMYUt+FWZJd4TtzjyUs8oGBJLvG7Gy4MMSM/K9Q mQsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gpep5/nDCBjR2xblMkuotvD31Bl23GAVCnm9qzFyGGI=; b=Gzjk629d3KJrDU7CDq4eALKImL7LVMi4mPb1fyH2eSmf9dpv6ImhXLWF+sawlKwg5a 0noGiNb2y7pp1BwVJn88qvSgFe73X6HN6vsJX5BJDvkLEYx39AOsrZ3KDkUXaPAyCHIY A+aAzmHbgAEaUL5caMIDn8/2KFQxsz+Dh51gFVWFtUtNcTq4Iff6kXdaHp//D7Gf9Npp wZGyBU5yHJf1DbwrNIpT53vOogFWoaDstiPz/epShiHlFtdJh4bt1qtJjCwTliEsVaDb PF1bDaqN7zirSw3Q0sduXpoCc8Znb0SxCcjF6tsVC2oIfIlVY6bYsOIYDUwcUHbSPm4X psPg== X-Gm-Message-State: AOAM5312GkZltJJvptTLJnZBRt+3sQWyPSq9hlfEHmDG+cZfP/p85HDB w5xykk8X2k4uUQJKekpGNjhJnP4b750= X-Google-Smtp-Source: ABdhPJzgoRHUlMmWqvJocJLqB70jrpIXO54WxHhzp/7IR6/ZXCqtN13Ex305G+b++w96NFNk5ENJNw== X-Received: by 2002:a17:90a:cc03:: with SMTP id b3mr8297944pju.80.1595409699796; Wed, 22 Jul 2020 02:21:39 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions Date: Wed, 22 Jul 2020 17:16:21 +0800 Message-Id: <20200722091641.8834-59-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang * Fix offset overflow issue. * Remove clear function from helper functions as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 83 ++++++++++++++++-------------------- 1 file changed, 37 insertions(+), 46 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bb426e224c..b47ca6c406 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4923,64 +4923,59 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) */ =20 /* Vector Slide Instructions */ -#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); = \ - uint32_t vm =3D vext_vm(desc); = \ - uint32_t vta =3D vext_vta(desc); = \ - uint32_t vl =3D env->vl; = \ - target_ulong offset =3D s1, i; = \ - \ - for (i =3D offset; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ - } \ - CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + target_ulong offset =3D s1, i; \ + \ + for (i =3D offset; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); \ + } \ } =20 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] =3D vs2[i] */ -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8) =20 -#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ + uint32_t vlmax =3D vext_max_elems(desc, sizeof(ETYPE), false); = \ uint32_t vm =3D vext_vm(desc); = \ - uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ target_ulong offset =3D s1, i; = \ \ for (i =3D 0; i < vl; ++i) { = \ + /* offset may be a large value, which j may overflow */ \ target_ulong j =3D i + offset; = \ + bool is_valid =3D (offset >=3D vlmax || j >=3D vlmax) ? false : tr= ue; \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - *((ETYPE *)vd + H(i)) =3D j >=3D vlmax ? 0 : *((ETYPE *)vs2 + H(j)= ); \ + *((ETYPE *)vd + H(i)) =3D is_valid ? *((ETYPE *)vs2 + H(j)) : 0; \ } \ - CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+rs1] */ -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) =20 -#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ - uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -4994,22 +4989,19 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ } \ } \ - CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=3Dx[rs1], vd[i+1] =3D vs2[i] */ -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8) =20 -#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax =3D env_archcpu(env)->cfg.vlen; = \ uint32_t vm =3D vext_vm(desc); = \ - uint32_t vta =3D vext_vta(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -5023,14 +5015,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ } \ } \ - CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } =20 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+1], vd[vl-1]=3Dx[rs1]= */ -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) =20 /* Vector Register Gather Instruction */ #define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wwWnFYhgiAsGU9GssgKhfj0XKT6lILK/t0ZSavv8d7E=; b=VcVKOF9VrFYiUuCfn5V48pm30uaOH6aIISKUoYJ2IsLVu9ON1W235TsULUOHOwjgRB aRMhSWgY4Rd72XZczgWH5VmIdjdKtCOPViuXP5eMC+F1J6SzOx1D0GNo1LqaZk6Pqb2f 8csfpEc7Nt5vBdjjqfVAIHZCIz2sJyIvqtKRVZLcku6Pqr8KzsFsdi7FAclm4tbMbusU aOkKLQUeylwDcDB7p12GlZJ/8WJxASx03I0VL3MjbkiNKYTD7Ncb4hdjq0VVsVgbD82m 1lfiAfy6OTTkuBFaAs35gOYr1AcxxjQpBNMK1D8glwjnjWdaCL5ebHrr9LaHbvCY82XS MrRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wwWnFYhgiAsGU9GssgKhfj0XKT6lILK/t0ZSavv8d7E=; b=ufjLkV4Q8EEVWQPb30X+6J6NVBpLGDndNmEYE9SA0ixXNvFHYe6zUn5s4MJdA+h5PP q0L/CLWj3uPPNml+Lg5hsVLOdswoTQF3p61T5/pmSEHYv0lNBX7MhrgKTb19nbS5gSsw hilZBDPjQaWlOaK5MPuFtMWLXszQjlgrZNQf8/ibaj2vMcn4HvNzIqhN1QmPyJWOCquX pqxXsiqb/zE135MoJ8ejqln91YIqq+s6FYxMMvKLVJeGGK7D05e9Wkno4VnEZhUTAMFE hoCSS/NChUQgiRnndIeaCDDDKwXjKcDNc09p7XqMoFwKPINiRXQhgQ1P8EjKY9CVjNUC RF8A== X-Gm-Message-State: AOAM533gMmzqcRlBgzpoe7vjGD7yhhbOcCVqMwrh9vWEzQ530eOBw71i iXJXjGcCzbYrTMTH1DO7SINTO+gp2KI= X-Google-Smtp-Source: ABdhPJxFKAtQ7XWKMSU1UWbUMpue98RxS3lwhaubYmhsFtv8IahKoQpwxmQpXp/Y08sdjfUjemXG8A== X-Received: by 2002:a65:5201:: with SMTP id o1mr11334281pgp.404.1595409704098; Wed, 22 Jul 2020 02:21:44 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions Date: Wed, 22 Jul 2020 17:16:22 +0800 Message-Id: <20200722091641.8834-60-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x532.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 ++++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 ++ target/riscv/vector_helper.c | 51 +++++++++++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b8a436d3aa..c6738336e8 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1114,6 +1114,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, p= tr, env, i32) DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 +DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32) + DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index acd65cb3a7..ed34ccd0e3 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -530,6 +530,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 = @r_vm vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 5004707b87..d16db7f61a 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3514,6 +3514,10 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) =20 +/* Vector Floating-Point Slide Instructions */ +GEN_OPFVF_TRANS(vfslide1up_vf, slideup_check) +GEN_OPFVF_TRANS(vfslide1down_vf, slidedown_check) + /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b47ca6c406..4036be4425 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5023,6 +5023,57 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, = H2) GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) =20 +/* Vector Floating-Point Slide Instructions */ +#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ETYPE, H) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); = \ + uint32_t vl =3D env->vl; = \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { = \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i =3D=3D 0) { = \ + *((ETYPE *)vd + H(i)) =3D s1; = \ + } else { \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ + } \ + } \ +} + +/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=3Df[rs1], vd[i+1] =3D vs2[i] */ +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, uint16_t, H1) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, uint32_t, H1) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, uint64_t, H1) + +#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ETYPE, H) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); = \ + uint32_t vl =3D env->vl; = \ + uint32_t i; \ + \ + for (i =3D 0; i < vl; i++) { = \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i =3D=3D vl - 1) { = \ + *((ETYPE *)vd + H(i)) =3D s1; = \ + } else { \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ + } \ + } \ +} + +/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] =3D vs2[i+1], vd[vl-1]=3Df[rs1= ] */ +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, uint16_t, H1) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, uint32_t, H1) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, uint64_t, H1) + /* Vector Register Gather Instruction */ #define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411842; cv=none; d=zohomail.com; s=zohoarc; b=jDPIhf5zxxKGCuX4xVMiqvt/J24RWrIAdnMdyIO08ZZyZjQUMSiKAKVRToavGGZ5lSNbz94W/BAvq2lHgi0gye9AbVIcBU7KKa4tHkrooCnM9TY3DXptJQzChvGBV2bQzvocfavGWVTOQtowkwc/8AERooQfyTDnwTkuOOO73uo= ARC-Message-Signature: i=1; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XSIREXmkO515MpaCTeTjx8Si06NdiF6mDrEjZd4Q8S8=; b=haLChm8uGDaNMpkNPHsmthJNYPZcxLjbtWryQXHxPDz5BfoySBrwUVoCrO+OsMgh7a a8SbJjW8x9nBsJxeQ7ysM4LdJ/CyxzhusJOAREKGYPKL84ixZLLgERGI8Zmhtl1Lxj5n 5+kLFLsNa7fM8nGumg/IMJjIk6WYB63YGB9XN1C2FJ+uY55qSKYFnkugG1/gHMRnse05 6N9Vyu4sGH+AIcG0QYxOSAtvzWwYL/qBoUmgKpr46jqdpt/kIrY3hakRxc4xESuMc3hV Vkh9DUj2ta31gku1mLpwEEV99LPg84qfv3kAqCdnnFtBy5IdswFB6PRtoQ7SBeLVlq7k iENQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XSIREXmkO515MpaCTeTjx8Si06NdiF6mDrEjZd4Q8S8=; b=CFRdO8a10r83t3hV/i5TK4olByZ/aw+cARV2cJdTf7TwHkFoT4DBnEfxXs8GIX749P kpv74YKf0S5+4IwXo45SnkIm2HHIl+nhowYTOWuPcLOU2xilFB0wQugFKSChPEOjw4i8 5eIHJFaOhcvz6Rsc20CN+RfuQaHL71hnfdP/+8AZ2xVd/J6kAo61NumkyI/Bt8PRUpqr P6kmXYCHLM2EgbWE13A9ORrzH0VtfMTT9E4iHvmsGf6q49PxrSJ+ElYdxZtcltJS7Qmf SoWvVbCvFja5vLu/N/OuTjLPrpadSUxHbWFc6BLDBmJs8sQa4YSbhmLECfxh/NB6pxU2 UFTw== X-Gm-Message-State: AOAM531vjIVKcMyfPYPt0cj36T8xKaH3j7mOcD7SfKLItNmzPO5EQSqB l78lvHeWo7JxzFDyrdx4Wq9OojjpEBw= X-Google-Smtp-Source: ABdhPJxmrZa91GndUjcDNP0apZQVd0TBFifV1ivuMXFLsbf83qhLNZE5DQahPA/8dH9643ZXw3Mijg== X-Received: by 2002:a63:3ece:: with SMTP id l197mr26475107pga.313.1595409708316; Wed, 22 Jul 2020 02:21:48 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions Date: Wed, 22 Jul 2020 17:16:23 +0800 Message-Id: <20200722091641.8834-61-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x534.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++++++------ target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 12 +++--- target/riscv/vector_helper.c | 52 ++++++++++++------------- 4 files changed, 50 insertions(+), 50 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c6738336e8..9dfe1c2b10 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -768,18 +768,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 -DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32) =20 DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ed34ccd0e3..dc3965c050 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -469,12 +469,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 101011= 1 @r_vm vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm -vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm -vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm -vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm -vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm -vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm -vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm +vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm +vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm +vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm +vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm +vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm +vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index d16db7f61a..9ea58bf14b 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2409,12 +2409,12 @@ GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_c= heck) GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) =20 /* Vector Narrowing Fixed-Point Clip Instructions */ -GEN_OPIVV_NARROW_TRANS(vnclipu_vv) -GEN_OPIVV_NARROW_TRANS(vnclip_vv) -GEN_OPIVX_NARROW_TRANS(vnclipu_vx) -GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) +GEN_OPIWV_NARROW_TRANS(vnclipu_wv) +GEN_OPIWV_NARROW_TRANS(vnclip_wv) +GEN_OPIWX_NARROW_TRANS(vnclipu_wx) +GEN_OPIWX_NARROW_TRANS(vnclip_wx) +GEN_OPIWI_NARROW_TRANS(vnclipu_wi, IMM_ZX, vnclipu_wx) +GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx) =20 /* *** Vector Float Point Arithmetic Instructions diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4036be4425..c8d3168cee 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3304,19 +3304,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, i= nt32_t b) } } =20 -RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8) -RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16) -RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32) -GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl) - -RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8) -RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16) -RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32) -GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl) +RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8) +RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16) +RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32) +GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1, clearb) +GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2, clearh) +GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4, clearl) + +RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8) +RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16) +RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32) +GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1, clearb) +GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2, clearh) +GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4, clearl) =20 static inline uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) @@ -3354,7 +3354,7 @@ static inline uint32_t vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) { uint8_t round, shift =3D b & 0x3f; - int64_t res; + uint64_t res; =20 round =3D get_round(vxrm, a, shift); res =3D (a >> shift) + round; @@ -3366,19 +3366,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a,= uint32_t b) } } =20 -RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) -RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) -RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) -GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl) +RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) +RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) +RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) +GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1, clearb) +GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2, clearh) +GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4, clearl) =20 -RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8) -RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16) -RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) -GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl) +RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8) +RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16) +RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32) +GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1, clearb) +GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2, clearh) +GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4, clearl) =20 /* *** Vector Float Point Arithmetic Instructions --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xX3TKxwO5nmbDDyxQK/BmEY05aUhOyzJvahr+HIJ9h4=; b=D7cz6OtPrbkQvc6NbIiVcoACkN8DH1Df5IniPbq2Mk9UaSRssiuXjt83yS+LpFHBfD dy1h0PMo2O0fS03gS/Fpe0+SFLYVXYDBOvHJuaoMQPus1AQt/rfVPL3KBOUok/kn6/kh BwjpySWhMtOWoe75bT8ZDwg9eQA+oVmyapVMztEsSyVHmKpc2JktQN54yNXBRcTWZ0rt imj/Hwr9McWhCOEfnCmIu6mXfWVsMMS16M9BGTxtgOBlzBEmIG8QViedptJVZezBquJy gb6NK5yy7x9MxL7Z2nqNyNBMLkdqhC2ryLxrPF7zTqPsVHqTKU6MZjPZmd/R0JWZOLsr X4hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xX3TKxwO5nmbDDyxQK/BmEY05aUhOyzJvahr+HIJ9h4=; b=au1QACEY46gc1Gn2DQ/xh3+EJA0kQqLthpc4cw8YJYGi8SCNzdQKWZwQ+EXrgpMjJU hyNO53FV0NhxOZUsUXU7/zj7ChSE0JVDMsiDAGzdcpYbG3vKoYADPV4V7C7XquYLQiHB UdB7MYm/a0CrXzUVA4RK4eNkdBuxjDTOS94oZSovLb3D74qi5zDNQDRVaTPkWMQGx4Zv srWgh51FZOsqtERtOkKSzDGZ0yeueuIh0vS53elEfcHN+dc/r370CBAKRM9HlqoBxdVP yG3loaUlYBT+pKV6eTBTxi+BLY+G1/PgR8ej9rtDVC0Mv5fJT3aUwfmLjcJLWm7el1ir BpKw== X-Gm-Message-State: AOAM531gWVTPGQzPzTj+3akL9LVnz09tXlwq/QyRPEGBxj325oOChErZ r7sbAknDtJ3nvfPkVgwUPpdAQWDoHH0= X-Google-Smtp-Source: ABdhPJxWpeT75Uyjza6HMWETjZ/g1srxU+s64l+4h8wiRdQRYUyh/ru6OSYskxfsGVfa387MBNtf2g== X-Received: by 2002:a63:7c56:: with SMTP id l22mr25299688pgn.127.1595409712687; Wed, 22 Jul 2020 02:21:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions Date: Wed, 22 Jul 2020 17:16:24 +0800 Message-Id: <20200722091641.8834-62-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x433.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 ++++ target/riscv/insn32.decode | 11 ++++--- target/riscv/insn_trans/trans_rvv.inc.c | 2 ++ target/riscv/vector_helper.c | 38 +++++++++++++++++++++++++ 4 files changed, 53 insertions(+), 4 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9dfe1c2b10..318fe643f4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -994,6 +994,12 @@ DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env,= i32) DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_xu_f_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_rtz_x_f_v_d, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index dc3965c050..e4b36af89e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -547,10 +547,13 @@ vmford_vf 011010 . ..... ..... 101 ..... 101011= 1 @r_vm vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 -vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm -vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm -vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm -vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm + +vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm +vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm +vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm +vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm +vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm +vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 9ea58bf14b..c1fc168043 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2879,6 +2879,8 @@ GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_rtz_xu_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_rtz_x_f_v, opfv_check) =20 /* Widening Floating-Point/Integer Type-Convert Instructions */ =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c8d3168cee..bbd3be527c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4480,6 +4480,44 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh) GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl) GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq) =20 +#define FCVT_RTZ_F_V(STYPE, DTYPE) \ +static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, float_status *s) \ +{ \ + signed char frm =3D s->float_rounding_mode; \ + s->float_rounding_mode =3D float_round_to_zero; \ + DTYPE##_t result =3D STYPE##_to_##DTYPE(a, s); \ + s->float_rounding_mode =3D frm; \ + return result; \ +} + +/* + * vfcvt.rtz.xu.f.v vd, vs2, vm + * Convert float to unsigned integer, truncating. + */ +FCVT_RTZ_F_V(float16, uint16) +FCVT_RTZ_F_V(float32, uint32) +FCVT_RTZ_F_V(float64, uint64) +RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16_rtz) +RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32_rtz) +RVVCALL(OPFVV1, vfcvt_rtz_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64_rtz) +GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_rtz_xu_f_v_d, 8, 8, clearq) + +/* + * vfcvt.rtz.x.f.v vd, vs2, vm + * Convert float to signed integer, truncating. + */ +FCVT_RTZ_F_V(float16, int16) +FCVT_RTZ_F_V(float32, int32) +FCVT_RTZ_F_V(float64, int64) +RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16_rtz) +RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32_rtz) +RVVCALL(OPFVV1, vfcvt_rtz_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64_rtz) +GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq) + /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ #define WOP_UU_H uint32_t, uint16_t, uint16_t --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kgevnvu183fosxsa31Scb7niGRVtkpmcq30ar5EP818=; b=bUe06ltLaIMDmQ9hzJJmGBvHWxL9E6Ga4WqmJoDrv1iugDhw0XF0VXtWetQEYwjqFH f+1zlv73SdAKQJZy6hAUjLPk7egBmX24bm7diaAgwOiN5pqws/HQsNZCazTp/dlbr7rf Ug5qbE/K9+2u0XNzwmmGI1MAZpQkI6WiVqsQJKcC1rHW5/iiLYWANgYCAb2mCQSR8KJx ykkBM+kNGJBYUmxfkGeXJ6apeXq06ri4b94zPrw/YqGhcclgZojr+vD4R+c+txlnafbm yr8GpTsD92Fi3UZCfCugsNW2H2ntPVzEjFMWVn7lXRCNSK3uKT0kPwimiRv4R6VqjM76 MIGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kgevnvu183fosxsa31Scb7niGRVtkpmcq30ar5EP818=; b=PnggFuwzECLqyZfN2MxaACpftMkm0DF4SPffHUU2PimFG/iwOzrxXIrLXRRO4cBwoO NroXCO9RJG914pc4l+wQ7AYPgBoKpeDp1vSYBAqeEEcA3on0QgmLUInLgORCZGwmyVhc dyPPMILzJXFMAZu11NgsdIVmMUqS5O8L6nxDO6e6TrcgDwXaHbiGFMxMgIe94tVgUrsM eid/UkzTrBIzXNVcgc3QuEhyhvTdaYIg1crViDgCgHxJDoYAHHSV0yKu+wFl5ePtvEdt 4ICZtLMF3xrZaVAsWzNUEvh8Sb3a5go6o4CX/oYKl11jyWEFAu2YtKHxhSOdBFERC0Vp RAQA== X-Gm-Message-State: AOAM533SMI6sKqxC7PW1K4symNg5kEBLas8a69FMKvxAoSig2vFv4/nA 6801ffZ7l5dxLQugJFamIKA3cbroE4Q= X-Google-Smtp-Source: ABdhPJyb9rD3sNaA/k2li3wr315NqPjhAPtSfzHkn1hoMOA75t+D29Qt8pG/+BLOgMmHk1ojzAig7A== X-Received: by 2002:a65:5c08:: with SMTP id u8mr27180403pgr.184.1595409716806; Wed, 22 Jul 2020 02:21:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction Date: Wed, 22 Jul 2020 17:16:25 +0800 Message-Id: <20200722091641.8834-63-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Separate the implementation of vfredsum.vs and vfredosum.vs. Introduce propagate NaN feature for vfredsum.vs as implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag. Signed-off-by: Frank Chang --- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 1 + target/riscv/vector_helper.c | 144 +++++++++++++++++++----- 4 files changed, 120 insertions(+), 31 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 318fe643f4..6957a98237 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1066,6 +1066,9 @@ DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr,= env, i32) DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e4b36af89e..0fe46c10c2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -575,7 +575,8 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 = @r_vm vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm # Vector ordered and unordered reduction sum -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm +vfredsum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm # Vector widening ordered and unordered float reduction sum diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index c1fc168043..37eee6cf97 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3011,6 +3011,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_c= heck) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) +GEN_OPFVV_TRANS(vfredosum_vs, reduction_check) GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bbd3be527c..8465aec94e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4682,43 +4682,127 @@ GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H= 4, H2, DO_ADD) GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ -#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t i; \ - uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; \ - TD s1 =3D *((TD *)vs1 + HD(0)); \ - \ - for (i =3D 0; i < vl; i++) { \ - TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - s1 =3D OP(s1, (TD)s2, &env->fp_status); \ - } \ - *((TD *)vd + HD(0)) =3D s1; \ - CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \ + +/* + * If f is NaN, return SEW-bit canonical NaN. + * Set the invalid exception flag if f is a sNaN. + */ +static uint64_t propagate_nan(uint64_t f, uint32_t sew, float_status *s) +{ + target_ulong ret; + + switch (sew) { + case 16: + ret =3D fclass_h(f); + /* check if f is NaN */ + if (ret & 0x300) { + /* check if f is a sNaN */ + if (ret & 0x100) { + s->float_exception_flags |=3D float_flag_invalid; + } + /* return canonical NaN */ + return float16_default_nan(s); + } else { + return f; + } + break; + case 32: + ret =3D fclass_s(f); + /* check if f is NaN */ + if (ret & 0x300) { + /* check if f is a sNaN */ + if (ret & 0x100) { + s->float_exception_flags |=3D float_flag_invalid; + } + /* return canonical NaN */ + return float32_default_nan(s); + } else { + return f; + } + break; + case 64: + ret =3D fclass_d(f); + /* check if f is NaN */ + if (ret & 0x300) { + /* check if f is a sNaN */ + if (ret & 0x100) { + s->float_exception_flags |=3D float_flag_invalid; + } + /* return canonical NaN */ + return float64_default_nan(s); + } else { + return f; + } + break; + default: + g_assert_not_reached(); + } } =20 +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, PROPAGATE_NAN, OP, CLEAR_FN)= \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ + void *vs2, CPURISCVState *env, = \ + uint32_t desc) = \ +{ = \ + uint32_t vm =3D vext_vm(desc); = \ + uint32_t vta =3D vext_vta(desc); = \ + uint32_t vl =3D env->vl; = \ + uint32_t i; = \ + uint32_t tot =3D env_archcpu(env)->cfg.vlen >> 3; = \ + bool active =3D false; = \ + TD s1 =3D *((TD *)vs1 + HD(0)); = \ + = \ + for (i =3D 0; i < vl; i++) { = \ + TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); = \ + if (!vm && !vext_elem_mask(v0, i)) { = \ + continue; = \ + } = \ + active =3D true; = \ + s1 =3D OP(s1, (TD)s2, &env->fp_status); = \ + } = \ + = \ + if (vl > 0) { = \ + if (PROPAGATE_NAN && !active) { = \ + *((TD *)vd + HD(0)) =3D propagate_nan(s1, sizeof(TD) * 8, = \ + &env->fp_status); = \ + } else { = \ + *((TD *)vd + HD(0)) =3D s1; = \ + } = \ + } = \ + CLEAR_FN(vd, vta, 1, sizeof(TD), tot); = \ +} + +/* Ordered sum */ +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, false, + float16_add, clearh) +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, false, + float32_add, clearl) +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, false, + float64_add, clearq) + /* Unordered sum */ -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clea= rh) -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clea= rl) -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clea= rq) +GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, true, + float16_add, clearh) +GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, true, + float32_add, clearl) +GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, true, + float64_add, clearq) =20 /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, c= learh) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, c= learl) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, c= learq) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, false, + float16_maxnum_noprop, clearh) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, false, + float32_maxnum_noprop, clearl) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, false, + float64_maxnum_noprop, clearq) =20 /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, c= learh) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, c= learl) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, c= learq) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, false, + float16_minnum_noprop, clearh) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, false, + float32_minnum_noprop, clearl) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false, + float64_minnum_noprop, clearq) =20 /* Vector Widening Floating-Point Reduction Instructions */ /* Unordered reduce 2*SEW =3D 2*SEW + sum(promote(SEW)) */ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Separate the implementation of vfwredsum.vs and vfwredosum.vs. Introduce propagate NaN feature for vfwredsum.vs as implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 3 +- target/riscv/vector_helper.c | 71 +++++++++++++++++++++++-- 4 files changed, 73 insertions(+), 6 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6957a98237..cfe9baa253 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1078,6 +1078,8 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr,= env, i32) =20 DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0fe46c10c2..e32946b1f5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -580,7 +580,8 @@ vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 = @r_vm vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm # Vector widening ordered and unordered float reduction sum -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm +vfwredsum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 37eee6cf97..10d8b8b00d 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3016,7 +3016,8 @@ GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) =20 /* Vector Widening Floating-Point Reduction Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, reduction_widen_check) =20 /* *** Vector Mask Operations diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8465aec94e..2b2b1f521f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4805,6 +4805,51 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8,= H8, false, float64_minnum_noprop, clearq) =20 /* Vector Widening Floating-Point Reduction Instructions */ +/* Ordered reduce 2*SEW =3D 2*SEW + sum(promote(SEW)) */ +void HELPER(vfwredosum_vs_h)(void *vd, void *v0, void *vs1, + void *vs2, CPURISCVState *env, uint32_t desc) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); + uint32_t vl =3D env->vl; + uint32_t i; + uint32_t tot =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t s1 =3D *((uint32_t *)vs1 + H4(0)); + + for (i =3D 0; i < vl; i++) { + uint16_t s2 =3D *((uint16_t *)vs2 + H2(i)); + if (!vm && !vext_elem_mask(v0, i)) { + continue; + } + s1 =3D float32_add(s1, float16_to_float32(s2, true, &env->fp_statu= s), + &env->fp_status); + } + *((uint32_t *)vd + H4(0)) =3D s1; + clearl(vd, vta, 1, sizeof(uint32_t), tot); +} + +void HELPER(vfwredosum_vs_w)(void *vd, void *v0, void *vs1, + void *vs2, CPURISCVState *env, uint32_t desc) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vta =3D vext_vta(desc); + uint32_t vl =3D env->vl; + uint32_t i; + uint32_t tot =3D env_archcpu(env)->cfg.vlen >> 3; + uint64_t s1 =3D *((uint64_t *)vs1); + + for (i =3D 0; i < vl; i++) { + uint32_t s2 =3D *((uint32_t *)vs2 + H4(i)); + if (!vm && !vext_elem_mask(v0, i)) { + continue; + } + s1 =3D float64_add(s1, float32_to_float64(s2, &env->fp_status), + &env->fp_status); + } + *((uint64_t *)vd) =3D s1; + clearq(vd, vta, 1, sizeof(uint64_t), tot); +} + /* Unordered reduce 2*SEW =3D 2*SEW + sum(promote(SEW)) */ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) @@ -4813,18 +4858,27 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, voi= d *vs1, uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; - uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; + uint32_t tot =3D env_archcpu(env)->cfg.vlen >> 3; uint32_t s1 =3D *((uint32_t *)vs1 + H4(0)); + bool active =3D false; =20 for (i =3D 0; i < vl; i++) { uint16_t s2 =3D *((uint16_t *)vs2 + H2(i)); if (!vm && !vext_elem_mask(v0, i)) { continue; } + active =3D true; s1 =3D float32_add(s1, float16_to_float32(s2, true, &env->fp_statu= s), &env->fp_status); } - *((uint32_t *)vd + H4(0)) =3D s1; + + if (vl > 0) { + if (!active) { + *((uint32_t *)vd + H4(0)) =3D propagate_nan(s1, 32, &env->fp_s= tatus); + } else { + *((uint32_t *)vd + H4(0)) =3D s1; + } + } clearl(vd, vta, 1, sizeof(uint32_t), tot); } =20 @@ -4835,18 +4889,27 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, voi= d *vs1, uint32_t vta =3D vext_vta(desc); uint32_t vl =3D env->vl; uint32_t i; - uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; + uint32_t tot =3D env_archcpu(env)->cfg.vlen >> 3; uint64_t s1 =3D *((uint64_t *)vs1); + bool active =3D false; = \ =20 for (i =3D 0; i < vl; i++) { uint32_t s2 =3D *((uint32_t *)vs2 + H4(i)); if (!vm && !vext_elem_mask(v0, i)) { continue; } + active =3D true; s1 =3D float64_add(s1, float32_to_float64(s2, &env->fp_status), &env->fp_status); } - *((uint64_t *)vd) =3D s1; + + if (vl > 0) { + if (!active) { + *((uint64_t *)vd) =3D propagate_nan(s1, 64, &env->fp_status); + } else { + *((uint64_t *)vd) =3D s1; + } + } clearq(vd, vta, 1, sizeof(uint64_t), tot); } =20 --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Zero-extend vssra.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 10d8b8b00d..fb8478a456 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2406,7 +2406,7 @@ GEN_OPIVV_TRANS(vssra_vv, opivv_check) GEN_OPIVX_TRANS(vssrl_vx, opivx_check) GEN_OPIVX_TRANS(vssra_vx, opivx_check) GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, IMM_ZX, vssra_vx, opivx_check) =20 /* Vector Narrowing Fixed-Point Clip Instructions */ GEN_OPIWV_NARROW_TRANS(vnclipu_wv) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411545; cv=none; d=zohomail.com; s=zohoarc; b=FQioAx0yHgz/dLGBsDLQmPA6Er26r4VtWi/xp9XC+NkAmqUdGtFcvsdB8rtkAyimWUElrYQ/CLPUDIpqEL+IEjR4fOoL0gCk6pQ5jME/DpOClICL/UpZvtZquUlMK9wR943y1NgC2Zns9Ftx07Lon4eQGzb1MaO7TmzZW61Plnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411545; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=hZBXTV5hlrVFu7qHkv9AB/jEY5LbpBvJ+tF1Sv4FGBo=; b=WUUjGqXsXS+kpEfrEJEHI/zSE9cl/OJv/MKOzg3h0jE4P3vQKYZbJlw2v5CsSPYTvcHt7CGy9LKtnQogQB3TSstAlMXSLpc4lIGSmWVJtocXlm7rJnB2I3Hew6WfK58ZdLdlkW9luwmEPRsXJzIybPNLUcs/k/yj7542K92039A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411545583221.32247131380586; Wed, 22 Jul 2020 02:52:25 -0700 (PDT) Received: from localhost ([::1]:59946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBQG-0008Lo-4m for importer@patchew.org; Wed, 22 Jul 2020 05:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAx3-0006sW-IY for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:13 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:41178) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAx1-0006AL-Il for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:13 -0400 Received: by mail-pf1-x436.google.com with SMTP id w126so702269pfw.8 for ; Wed, 22 Jul 2020 02:22:11 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hZBXTV5hlrVFu7qHkv9AB/jEY5LbpBvJ+tF1Sv4FGBo=; b=N5C50KSwZQwjaukyqcXv4vSPiixk2pEzscSfgnNDSpmyVfUqBA4IL+e+A8YIebVX50 /cLZFBpN6Dfzjezl13Iamthkh2sJr6Pr17BSQ6Dqhj21z8NJwERkv89LDOC2EKECsJrp rDNoFWo3kt1bM6x1LqRMNk5hklFoSSyzshK4KBxQEZAk04y1hSqTcrd6EUtxZ3wK4CMW 2FODbLHGKeUbpQlTbPdwIBbMds3yNsj7v30BSqfz3+Wbu4wVdwwHoerMs6bFJFig4R+1 L3T2Y2g0+0a7/sNSBX3+fkwtSBKHioEzFfkkBQ1l5BXdPl6Vx+pyioA/opWpIzh5vzZh Gg8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hZBXTV5hlrVFu7qHkv9AB/jEY5LbpBvJ+tF1Sv4FGBo=; b=sLab7DZRDn8x2O5Cu24e49c46kZDnlR+IdozvXrkQdJLb86ww5tOaXDic/E8R0QjWB KuMOm78ium54mhrWk7Z4hfgXbQNoPA5aeJqFzyDAfL7C1DIg7Ei2dzG5k5obdc0Zox4+ aHgyqnIvxOXPbv0EPr9aY33c8Dfdu7rcN4ZY+0qq4Ps/jvvB0jKtXEw8aBq/lPDv0rAa VBxVeXJnjRRnGeUiaKrui9Vs7fe1cuj8H8luSGh/uZBaeaYV+/xXBGokGCD1BPpM2jDz 1lN+X/Ke3AaRh01NSc2CqTHvJFj+9N2wEyaLvfkZW3tGY7PAF1i1G6q9ECZlkjtSefHn tQTQ== X-Gm-Message-State: AOAM532IWP0VFMNw0Lja3BznqR2Xxi5S+rXfZvRhTpOi8CfSl6a+ovve zI3/DOkmVfcEmZrCHrm4U1D33neBMcY= X-Google-Smtp-Source: ABdhPJy4FuhrNjWZkG2WOrW2QMbmj/AEmxQv4Y+rRwm1y41vDxY8CErrh/biEYBqtc+/QIPXY2An1A== X-Received: by 2002:a63:8f51:: with SMTP id r17mr26028335pgn.124.1595409729922; Wed, 22 Jul 2020 02:22:09 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add Date: Wed, 22 Jul 2020 17:16:28 +0800 Message-Id: <20200722091641.8834-66-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.inc.c | 9 -- target/riscv/vector_helper.c | 205 ------------------------ 4 files changed, 243 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index cfe9baa253..d7f3714ba6 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -729,28 +729,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env,= i32) DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 -DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) - DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e32946b1f5..2be673c2c7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -456,13 +456,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111= @r_vm vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm -vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm -vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index fb8478a456..9480c64971 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2391,15 +2391,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check) GEN_OPIVV_TRANS(vsmul_vv, opivv_check) GEN_OPIVX_TRANS(vsmul_vx, opivx_check) =20 -/* Vector Widening Saturating Scaled Multiply-Add */ -GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) - /* Vector Single-Width Scaling Shift Instructions */ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2b2b1f521f..c5fc61bf76 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2923,211 +2923,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq) =20 -/* Vector Widening Saturating Scaled Multiply-Add */ -static inline uint16_t -vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b, - uint16_t c) -{ - uint8_t round; - uint16_t res =3D (uint16_t)a * b; - - round =3D get_round(vxrm, res, 4); - res =3D (res >> 4) + round; - return saddu16(env, vxrm, c, res); -} - -static inline uint32_t -vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b, - uint32_t c) -{ - uint8_t round; - uint32_t res =3D (uint32_t)a * b; - - round =3D get_round(vxrm, res, 8); - res =3D (res >> 8) + round; - return saddu32(env, vxrm, c, res); -} - -static inline uint64_t -vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b, - uint64_t c) -{ - uint8_t round; - uint64_t res =3D (uint64_t)a * b; - - round =3D get_round(vxrm, res, 16); - res =3D (res >> 16) + round; - return saddu64(env, vxrm, c, res); -} - -#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - TD d =3D *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) =3D OP(env, vxrm, s2, s1, d); \ -} - -RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) -GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq) - -#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, target_long s1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - TD d =3D *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) =3D OP(env, vxrm, s2, (TX1)(T1)s1, d); \ -} - -RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) -GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res =3D (int16_t)a * b; - - round =3D get_round(vxrm, res, 4); - res =3D (res >> 4) + round; - return sadd16(env, vxrm, c, res); -} - -static inline int32_t -vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c) -{ - uint8_t round; - int32_t res =3D (int32_t)a * b; - - round =3D get_round(vxrm, res, 8); - res =3D (res >> 8) + round; - return sadd32(env, vxrm, c, res); - -} - -static inline int64_t -vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res =3D (int64_t)a * b; - - round =3D get_round(vxrm, res, 16); - res =3D (res >> 16) + round; - return sadd64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) -RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) -RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) -GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq) -RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) -RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) -RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) -GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res =3D a * (int16_t)b; - - round =3D get_round(vxrm, res, 4); - res =3D (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t = c) -{ - uint8_t round; - int32_t res =3D a * (int32_t)b; - - round =3D get_round(vxrm, res, 8); - res =3D (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res =3D a * (int64_t)b; - - round =3D get_round(vxrm, res, 16); - res =3D (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) -GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) -GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c) -{ - uint8_t round; - int16_t res =3D (int16_t)a * b; - - round =3D get_round(vxrm, res, 4); - res =3D (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c) -{ - uint8_t round; - int32_t res =3D (int32_t)a * b; - - round =3D get_round(vxrm, res, 8); - res =3D (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c) -{ - uint8_t round; - int64_t res =3D (int64_t)a * b; - - round =3D get_round(vxrm, res, 16); - res =3D (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) -GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq) - /* Vector Single-Width Scaling Shift Instructions */ static inline uint8_t vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411904; cv=none; d=zohomail.com; s=zohoarc; b=mpNPzsM3XW2218IxZqk5/sg+d4OO7DOu2Dh0w5XDsEK1DX9WiIgporlx79f7fg3cNg6Dg3XvSWJJAezG4YRkXwBg4hngyFxxl3PfsM6l8M3Zh04PVDSCz9PeJEG08WigGp765/G7vBJPtBIKy7YdaxZX9G6cpAWOxaUTQpiwdDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411904; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=442LCk3HrChupyhPWwxJa1XCObc+Y0ctzDc4sW/DerE=; b=hW44BvDrG9lp6WGuqcO8uACGdC2oG54Dg/aF6T8giv0RJDi+xqfUHioHok7H5KzRMp49flOIjYcgeRCLfRyuKQVcNSocHMHBHWgUlVAvcJwf6YunW1KcFW8wdKsIqQEiCH8qpklVMn4GSNXQybXonVNCHp7p+SedlQoNnAlScvU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411904503603.2080541922882; Wed, 22 Jul 2020 02:58:24 -0700 (PDT) Received: from localhost ([::1]:53612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBW3-0000Wi-Bi for importer@patchew.org; Wed, 22 Jul 2020 05:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAx7-00071o-5l for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:17 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:41167) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAx5-0006An-In for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:16 -0400 Received: by mail-pf1-x42a.google.com with SMTP id w126so702349pfw.8 for ; Wed, 22 Jul 2020 02:22:15 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 ------ target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.inc.c | 2 -- target/riscv/vector_helper.c | 13 ------------- 4 files changed, 23 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d7f3714ba6..d74dbffc21 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -945,12 +945,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env= , i32) DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2be673c2c7..47337abe52 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -535,8 +535,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 = @r_vm vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm -vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm -vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 9480c64971..ea55428293 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2790,7 +2790,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) =20 static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) { @@ -2806,7 +2805,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) =20 /* Vector Floating-Point Classify Instruction */ GEN_OPFV_TRANS(vfclass_v, opfv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c5fc61bf76..49e6a91859 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4114,19 +4114,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *= s) -{ - FloatRelation compare =3D float16_compare_quiet(a, b, s); - return compare =3D=3D float_relation_unordered; -} - -GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) - /* Vector Floating-Point Classify Instruction */ #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i) \ --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411631; cv=none; d=zohomail.com; s=zohoarc; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.inc.c | 23 ----------------------- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 47337abe52..bc0e44b8ab 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -590,7 +590,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 = @r2_vm vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 -vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index ea55428293..6249f9af5b 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3206,8 +3206,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) *** Vector Permutation Instructions */ =20 -/* Integer Extract Instruction */ - static void load_element(TCGv_i64 dest, TCGv_ptr base, int ofs, int sew, bool sign) { @@ -3309,27 +3307,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_= i64 dest, load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } =20 -static bool trans_vext_x_v(DisasContext *s, arg_r *a) -{ - TCGv_i64 tmp =3D tcg_temp_new_i64(); - TCGv dest =3D tcg_temp_new(); - - if (a->rs1 =3D=3D 0) { - /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0); - } else { - /* This instruction ignores LMUL and vector register groups */ - int vlmax =3D s->vlen >> (3 + s->sew); - vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); - } - tcg_gen_trunc_i64_tl(dest, tmp); - gen_set_gpr(a->rd, dest); - - tcg_temp_free(dest); - tcg_temp_free_i64(tmp); - return true; -} - /* Integer Scalar Move Instruction */ =20 static void store_element(TCGv_i64 val, TCGv_ptr base, --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411054; cv=none; d=zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Chih-Min Chao , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chih-Min Chao For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic return NaN and set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNan The alternative path set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNaN return NaN if ft1 =3D=3D sNaN && ft2 =3D=3D sNaN The ieee754 spec allows both implementation and some architecture such as riscv choose differenct defintion in two spec versions. (riscv-spec-v2.2 use original one, riscv-spec-20191213 changes to alternative one) Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- fpu/softfloat.c | 75 ++++++++++++++++++++++++++--------------- include/fpu/softfloat.h | 6 ++++ 2 files changed, 54 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9c6640862e..e1661f22a5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -898,11 +898,16 @@ static FloatParts return_nan(FloatParts a, float_stat= us *s) return a; } =20 -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static void set_snan_flag(FloatParts a, FloatParts b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { s->float_exception_flags |=3D float_flag_invalid; } +} + +static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +{ + set_snan_flag(a, b, s); =20 if (s->default_nan_mode) { return parts_default_nan(s); @@ -2771,23 +2776,32 @@ float64 uint16_to_float64(uint16_t a, float_status = *status) * and minNumMag() from the IEEE-754 2008. */ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, - bool ieee, bool ismag, float_status *s) + bool ieee, bool ismag, bool issnan_prop, + float_status *s) { if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { if (ieee) { /* Takes two floating-point values `a' and `b', one of * which is a NaN, and returns the appropriate NaN * result. If either `a' or `b' is a signaling NaN, - * the invalid exception is raised. + * the invalid exception is raised but the NaN + * propagation is 'shall'. */ if (is_snan(a.cls) || is_snan(b.cls)) { - return pick_nan(a, b, s); - } else if (is_nan(a.cls) && !is_nan(b.cls)) { + if (issnan_prop) { + return pick_nan(a, b, s); + } else { + set_snan_flag(a, b, s); + } + } + + if (is_nan(a.cls) && !is_nan(b.cls)) { return b; } else if (is_nan(b.cls) && !is_nan(a.cls)) { return a; } } + return pick_nan(a, b, s); } else { int a_exp, b_exp; @@ -2841,37 +2855,44 @@ static FloatParts minmax_floats(FloatParts a, Float= Parts b, bool ismin, } } =20 -#define MINMAX(sz, name, ismin, isiee, ismag) \ +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \ float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ - FloatParts pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, \ + issnan_prop, s); \ \ return float ## sz ## _round_pack_canonical(pr, s); \ } =20 -MINMAX(16, min, true, false, false) -MINMAX(16, minnum, true, true, false) -MINMAX(16, minnummag, true, true, true) -MINMAX(16, max, false, false, false) -MINMAX(16, maxnum, false, true, false) -MINMAX(16, maxnummag, false, true, true) - -MINMAX(32, min, true, false, false) -MINMAX(32, minnum, true, true, false) -MINMAX(32, minnummag, true, true, true) -MINMAX(32, max, false, false, false) -MINMAX(32, maxnum, false, true, false) -MINMAX(32, maxnummag, false, true, true) - -MINMAX(64, min, true, false, false) -MINMAX(64, minnum, true, true, false) -MINMAX(64, minnummag, true, true, true) -MINMAX(64, max, false, false, false) -MINMAX(64, maxnum, false, true, false) -MINMAX(64, maxnummag, false, true, true) +MINMAX(16, min, true, false, false, true) +MINMAX(16, minnum, true, true, false, true) +MINMAX(16, minnum_noprop, true, true, false, false) +MINMAX(16, minnummag, true, true, true, true) +MINMAX(16, max, false, false, false, true) +MINMAX(16, maxnum, false, true, false, true) +MINMAX(16, maxnum_noprop, false, true, false, false) +MINMAX(16, maxnummag, false, true, true, true) + +MINMAX(32, min, true, false, false, true) +MINMAX(32, minnum, true, true, false, true) +MINMAX(32, minnum_noprop, true, true, false, false) +MINMAX(32, minnummag, true, true, true, true) +MINMAX(32, max, false, false, false, true) +MINMAX(32, maxnum, false, true, false, true) +MINMAX(32, maxnum_noprop, false, true, false, false) +MINMAX(32, maxnummag, false, true, true, true) + +MINMAX(64, min, true, false, false, true) +MINMAX(64, minnum, true, true, false, true) +MINMAX(64, minnum_noprop, true, true, false, false) +MINMAX(64, minnummag, true, true, true, true) +MINMAX(64, max, false, false, false, true) +MINMAX(64, maxnum, false, true, false, true) +MINMAX(64, maxnum_noprop, false, true, false, false) +MINMAX(64, maxnummag, false, true, true, true) =20 #undef MINMAX =20 diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 267519cd65..078cad8ad9 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -231,6 +231,8 @@ float16 float16_minnum(float16, float16, float_status *= status); float16 float16_maxnum(float16, float16, float_status *status); float16 float16_minnummag(float16, float16, float_status *status); float16 float16_maxnummag(float16, float16, float_status *status); +float16 float16_minnum_noprop(float16, float16, float_status *status); +float16 float16_maxnum_noprop(float16, float16, float_status *status); float16 float16_sqrt(float16, float_status *status); FloatRelation float16_compare(float16, float16, float_status *status); FloatRelation float16_compare_quiet(float16, float16, float_status *status= ); @@ -392,6 +394,8 @@ float32 float32_minnum(float32, float32, float_status *= status); float32 float32_maxnum(float32, float32, float_status *status); float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); +float32 float32_minnum_noprop(float32, float32, float_status *status); +float32 float32_maxnum_noprop(float32, float32, float_status *status); bool float32_is_quiet_nan(float32, float_status *status); bool float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); @@ -581,6 +585,8 @@ float64 float64_minnum(float64, float64, float_status *= status); float64 float64_maxnum(float64, float64, float_status *status); float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); +float64 float64_minnum_noprop(float64, float64, float_status *status); +float64 float64_maxnum_noprop(float64, float64, float_status *status); bool float64_is_quiet_nan(float64 a, float_status *status); bool float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 49e6a91859..4c6755db97 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3857,28 +3857,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) =20 /* Vector Floating-Point MIN/MAX Instructions */ -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop) +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop) +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum_noprop) GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop) +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop) +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop) GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) =20 -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop) +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop) +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop) GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop) +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop) +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop) GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O3tJNy/mx1SX7dN5+KyOXPJCc/LvDChTHRqMQLei8AM=; b=WRoQ2ibAqobzDm8yOt/UqdokkPfCrAEZ9qULnkjMSpLZGq3/8oyYX3xqvdqP8SmSJp S+ZP0A5r+VTpbEpeb6ktHBAH95GITgqlGaOHsJ/lS84/TM1LhiloXLbNPQ8uPh/zz/Fp w8DjqqFaeAQyMKoIGPxnA5sC7Dw0Um2unCXrt59GdvXJLoR2CE+p8vzfgGTZ8KFtqirI mYCJfl31UhNgR+TVscohR6RsbbnefJmS5eWaXLs6zD1IBHJB4p2QBE/PqTUDvAGUESvk znvlD0zFJoW1PIEFveqdOFYnlw3Tq9suArHCpvSc5Ywfh4ER3WN+RKLzm0GfzyjGM63+ YCtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O3tJNy/mx1SX7dN5+KyOXPJCc/LvDChTHRqMQLei8AM=; b=mNSoSVCX1BlY9+MElGiHfB4LU8n00FFR727p8OrC8ntrMUpcatD6m8600vZDOQn+PF L/Utl714IJyh9H9b7Y52VG+1JPMRjaOKu6B64jRQpoJQDocy5D9duMz2D2LtX1Wty2kY We1rQrP/9j34aI61XV1azJTAbgtuja7kByEj5bPUBYZiw2AC7nDPj8pBGVbKE5oOavUr ZGbPf1IY7tNOVXOcq5wSZBq1RCAdITWN+caiMwh2Cx3LFjG/xx0hlqtQ7t/6TYSTcOhw YpvLvCfHForsJG9aVQzjUTTH7sXdR/QlXxvj4/8rK7Bu81jwAaMYihYJxFWxhz/6q3h0 kJvA== X-Gm-Message-State: AOAM5339Q8aEgLjd5KLknxYXtMW9NH+V9bwl1If8w7Zuc29NyE4jNzmf 3XNLXPK6H1w2Dgd0/skzZB6ruWW2Gmo= X-Google-Smtp-Source: ABdhPJyjNAis+n0uSfZEcOr9YsbAZYC9Kh0vD5Q9aAohh0dOZb4EEx/3IlLA7UpCaEd0UBLHjmOGGw== X-Received: by 2002:a17:90a:d583:: with SMTP id v3mr8549065pju.33.1595409749906; Wed, 22 Jul 2020 02:22:29 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions Date: Wed, 22 Jul 2020 17:16:33 +0800 Message-Id: <20200722091641.8834-71-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x632.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 34 ++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 ++++++++ 2 files changed, 42 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e1661f22a5..89634267db 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2142,6 +2142,13 @@ static int64_t round_to_int_and_pack(FloatParts in, = FloatRoundMode rmode, } } =20 +int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_int_and_pack(float16_unpack_canonical(a, s), + rmode, scale, INT8_MIN, INT8_MAX, s); +} + int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { @@ -2205,6 +2212,11 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoun= dMode rmode, int scale, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 +int8_t float16_to_int8(float16 a, float_status *s) +{ + return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16(float16 a, float_status *s) { return float16_to_int16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2355,6 +2367,13 @@ static uint64_t round_to_uint_and_pack(FloatParts in= , FloatRoundMode rmode, } } =20 +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_uint_and_pack(float16_unpack_canonical(a, s), + rmode, scale, UINT8_MAX, s); +} + uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int sca= le, float_status *s) { @@ -2418,6 +2437,11 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRo= undMode rmode, int scale, rmode, scale, UINT64_MAX, s); } =20 +uint8_t float16_to_uint8(float16 a, float_status *s) +{ + return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s); +} + uint16_t float16_to_uint16(float16 a, float_status *s) { return float16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2572,6 +2596,11 @@ float16 int16_to_float16(int16_t a, float_status *st= atus) return int64_to_float16_scalbn(a, 0, status); } =20 +float16 int8_to_float16(int8_t a, float_status *status) +{ + return int64_to_float16_scalbn(a, 0, status); +} + float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { FloatParts pa =3D int_to_float(a, scale, status); @@ -2697,6 +2726,11 @@ float16 uint16_to_float16(uint16_t a, float_status *= status) return uint64_to_float16_scalbn(a, 0, status); } =20 +float16 uint8_to_float16(uint8_t a, float_status *status) +{ + return uint64_to_float16_scalbn(a, 0, status); +} + float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *stat= us) { FloatParts pa =3D uint_to_float(a, scale, status); diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 078cad8ad9..5700d2024b 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -136,9 +136,11 @@ float16 uint16_to_float16_scalbn(uint16_t a, int, floa= t_status *status); float16 uint32_to_float16_scalbn(uint32_t a, int, float_status *status); float16 uint64_to_float16_scalbn(uint64_t a, int, float_status *status); =20 +float16 int8_to_float16(int8_t a, float_status *status); float16 int16_to_float16(int16_t a, float_status *status); float16 int32_to_float16(int32_t a, float_status *status); float16 int64_to_float16(int64_t a, float_status *status); +float16 uint8_to_float16(uint8_t a, float_status *status); float16 uint16_to_float16(uint16_t a, float_status *status); float16 uint32_to_float16(uint32_t a, float_status *status); float16 uint64_to_float16(uint64_t a, float_status *status); @@ -187,10 +189,13 @@ float32 float16_to_float32(float16, bool ieee, float_= status *status); float16 float64_to_float16(float64 a, bool ieee, float_status *status); float64 float16_to_float64(float16 a, bool ieee, float_status *status); =20 +int8_t float16_to_int8_scalbn(float16, FloatRoundMode, int, + float_status *status); int16_t float16_to_int16_scalbn(float16, FloatRoundMode, int, float_status= *); int32_t float16_to_int32_scalbn(float16, FloatRoundMode, int, float_status= *); int64_t float16_to_int64_scalbn(float16, FloatRoundMode, int, float_status= *); =20 +int8_t float16_to_int8(float16, float_status *status); int16_t float16_to_int16(float16, float_status *status); int32_t float16_to_int32(float16, float_status *status); int64_t float16_to_int64(float16, float_status *status); @@ -199,6 +204,8 @@ int16_t float16_to_int16_round_to_zero(float16, float_s= tatus *status); int32_t float16_to_int32_round_to_zero(float16, float_status *status); int64_t float16_to_int64_round_to_zero(float16, float_status *status); =20 +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode, + int, float_status *status); uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode, int, float_status *status); uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode, @@ -206,6 +213,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRound= Mode, uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode, int, float_status *status); =20 +uint8_t float16_to_uint8(float16 a, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); uint32_t float16_to_uint32(float16 a, float_status *status); uint64_t float16_to_uint64(float16 a, float_status *status); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411714; cv=none; d=zohomail.com; s=zohoarc; b=hU916TpFaiRVxHNeVaz7gyEvO5Sp6YeDgpo9Dzviw6TSohGFnpdxBatzR5AHl3JT2rNJwM7geWa3F2F9MxBjFTh+IEtMMGyWrhk+R8ZWsdNFxsNTkNZONB0kFYwLtbo219vvCfCefFPLxFl0bj91FwZ9k7BF5i4r9flTokPuWRs= ARC-Message-Signature: i=1; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+D0zPyB+6VBV8sI4ksQukTNEFjnxE7hOXag5S/fiqkI=; b=RzC2zJG7GcbxY9lcWv11+Cm7fflMzyBsi83tdplTpoJkc5wT29ivnpf3UUeBm6+rRv LQbSYuHBQgQ3echT84pa4BBbvhxMuElo8ijZAGWxpXyH7A3lT4H/nR7fJrkW9ztXE26+ V6rt1eHKtpRdiCNPk60lvPtenBlulc01o/y5bHpawNEj0vV42Igc0u7IOv7KFcQaITva q3DDZ9Mgxkkt4fZz5wxiemljt53D85P2cvPOcEFV2w2H91j7nJdxnMbWiqLBjMQKDQE8 I4IuduL9KCHlWx0dRMArii9zZuzYm3d5xcHagWCDrK9HxW4LSflIvKuhBLuzdoLeGRI7 dJww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+D0zPyB+6VBV8sI4ksQukTNEFjnxE7hOXag5S/fiqkI=; b=gjn7kNWyEip/tfKJX1jT7Mp0ER2Rat8oS2djNfenzUfjHIe6up3o+98G3He0wRCMCN R5meHcvuXYJW5R2sCwtWQZ3+HOP2PSVUuDIpylg82bvK56vETfEVIIMo0s1hjcrcMzYn nHWWSgNSFvI/ma3C2cRSdbq8YC8InOyiRB/AQBGNR+fPAPAYVH/9WW1AazI1Vglo8N7s +VWS8EbzWLrYLLFHQpm0suAHh7u71Le0T/xdnnEyDvs3E0uvdBdO6UZZT3/jz5YayBB+ aiGFZ7Ka2sOGMCPVC/rHwXJHz+qpMFdIyEOXhTnxw182KM8dqn0D74cJXoMrxUMZ7QKo RF1Q== X-Gm-Message-State: AOAM533mswc1etINg5mLqzVNxAuKyFUt0Wt2jVO2jF1wI6hhhocexzJS YqoBzRM5wvPUgZJadT1dmDPZg8t+pJs= X-Google-Smtp-Source: ABdhPJyyIwtGndCTM2eFkh/+oof+hkkTO4HgvkF8X/8sN78meEB2SD/epJBebI8XIvbo7jVqHog8qQ== X-Received: by 2002:a17:90a:ac14:: with SMTP id o20mr9158568pjq.185.1595409754238; Wed, 22 Jul 2020 02:22:34 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert Date: Wed, 22 Jul 2020 17:16:34 +0800 Message-Id: <20200722091641.8834-72-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 ++++ target/riscv/insn32.decode | 13 +++++--- target/riscv/insn_trans/trans_rvv.inc.c | 43 +++++++++++++++++++++++-- target/riscv/vector_helper.c | 29 ++++++++++++++++- 4 files changed, 83 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d74dbffc21..03330fa332 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -977,12 +977,18 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, en= v, i32) DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bc0e44b8ab..55d7a6f338 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -545,11 +545,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 101= 0111 @r2_vm vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm -vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm -vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm -vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm -vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm -vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm + +vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm +vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm +vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm +vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm +vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm +vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm +vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 6249f9af5b..775811c9f0 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2915,9 +2915,48 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a= ) \ =20 GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v) + +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV widening instructions ignore vs1 check */ + vext_check_dss(s, a->rd, 0, a->rs2, a->vm, false); +} + +#define GEN_OPFXV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfxv_widen_check(s, a)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over =3D gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v) +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4c6755db97..3d12638c4b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4302,6 +4302,7 @@ GEN_VEXT_V_ENV(vfcvt_rtz_x_f_v_d, 8, 8, clearq) =20 /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger.*/ @@ -4317,19 +4318,45 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl) GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq) =20 /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat */ +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2, clearh) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq) =20 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2, clearh) GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq) =20 /* - * vfwcvt.f.f.v vd, vs2, vm # + * vfwcvt.rtz.xu.f.v vd, vs2, vm + * Convert float to double-width unsigned integer, truncating + */ +FCVT_RTZ_F_V(float16, uint32) +FCVT_RTZ_F_V(float32, uint64) +RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32_r= tz) +RVVCALL(OPFVV1, vfwcvt_rtz_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64_r= tz) +GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_h, 2, 4, clearl) +GEN_VEXT_V_ENV(vfwcvt_rtz_xu_f_v_w, 4, 8, clearq) + +/* + * vfwcvt.rtz.x.f.v vd, vs2, vm + * Convert float to double-width signed integer, truncating. + */ +FCVT_RTZ_F_V(float16, int32) +FCVT_RTZ_F_V(float32, int64) +RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32_rtz) +RVVCALL(OPFVV1, vfwcvt_rtz_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64_rtz) +GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_h, 2, 4, clearl) +GEN_VEXT_V_ENV(vfwcvt_rtz_x_f_v_w, 4, 8, clearq) + +/* + * vfwcvt.f.f.v vd, vs2, vm * Convert single-width float to double-width float. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9XOTESI9eXA/uC1WDkucmt0i6gkmJBujKi7+z0KtGwA=; b=nAMRy9DEgjrqVfEGOsO6MGznuW9V8pSK4iqexcjg+yC5cmN8WdXqEjq9n+5DuKMp7g TzKXu0P2UScfVnj0s2YctNlancSx8IYq17NylGarogQrtpCu73VWDpEbbhkLctMduMTm pxcJvYv33sxhRtzDjIMy454WWuFLN15DG7YyxjYFS94tLD47iovvAiPJD/Gn/Yuhdozq G3k9HoIADnpxgAdkMSnpJTRGFdpjENvpt56q0sh3gtx8auub5XtgSYGFMVC3D7z6T7kX 7WICg/qaT3coL3jXqyIPr9dLoRelrVbr9K8IANABKyYMOsPc8QqHDC73FCsqKjFgz5qY kxlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9XOTESI9eXA/uC1WDkucmt0i6gkmJBujKi7+z0KtGwA=; b=ljBTKbstnsTxhclMRNAZ020Pks48r7ntiTGtl9SyzlSu0lfwFXak96w2Fv+BBssTjU DPHQUPheLcH6kbXu/cU+QAKGlQJbiN/BaOC+0lH/I0u2tC4uCJNmDd19iZ0trDhyCkPT QAjQax1lqZitUkIIKWRVILM8w21P2q1+JyLybA/xOlHXEjyvdk1atWcCpX2qQS9/VK0I E91R7ZEZIl+JFZXsEOC7yBzqpRjmdn7M+LNoF9nwTb4fHUXXM5Ns00iHH4BWRTy6SlgR vfr5zetJJ1HXyJ4AtB/RIz0xTp6CBDgPhfiQEnKV+JZtQetoYV33R/TYaAYa260VMheV E9gw== X-Gm-Message-State: AOAM532d8LuX45sRZk0cAckSpol/J09ZhLFEtQoPPIOCLi0zdF8+x6O8 mpyRskdWYWrSEEBcfsckWpvT8QfnsBQ= X-Google-Smtp-Source: ABdhPJwFditogk5CvmFL5pAeKr51uez7CR4lVqImYSOTfltMyEe+M+JxLKHgPjuFwxiHOWx4Ssu0Og== X-Received: by 2002:aa7:9d81:: with SMTP id f1mr27221800pfq.225.1595409758329; Wed, 22 Jul 2020 02:22:38 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert Date: Wed, 22 Jul 2020 17:16:35 +0800 Message-Id: <20200722091641.8834-73-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 30 +++++--- target/riscv/insn32.decode | 15 ++-- target/riscv/insn_trans/trans_rvv.inc.c | 50 +++++++++++-- target/riscv/vector_helper.c | 99 ++++++++++++++++++++----- 4 files changed, 154 insertions(+), 40 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 03330fa332..a8260072e6 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -990,16 +990,26 @@ DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr= , env, i32) DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32) =20 -DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rod_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rod_f_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_w, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 55d7a6f338..17350227c6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -553,11 +553,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 101= 0111 @r2_vm vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm -vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm -vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm -vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm -vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm -vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm + +vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm +vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm +vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm +vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm +vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm +vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm +vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm +vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm + vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 775811c9f0..7c4f78a065 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -3000,11 +3000,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ return false; \ } =20 -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w) +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w) + +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sds(s, a->rd, 0, a->rs2, a->vm, false); +} + +#define GEN_OPXFV_NARROW_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opxfv_narrow_check(s, a)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over =3D gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w) +GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w) =20 /* *** Vector Reduction Operations diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3d12638c4b..d4563e9091 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4272,6 +4272,16 @@ static DTYPE##_t STYPE##_to_##DTYPE##_rtz(STYPE a, f= loat_status *s) \ return result; \ } =20 +#define FCVT_ROD_F_F(STYPE, DTYPE) \ +static DTYPE STYPE##_to_##DTYPE##_rod(STYPE a, float_status *s) \ +{ \ + signed char frm =3D s->float_rounding_mode; \ + s->float_rounding_mode =3D float_round_to_odd; \ + DTYPE result =3D STYPE##_to_##DTYPE(a, s); \ + s->float_rounding_mode =3D frm; \ + return result; \ +} + /* * vfcvt.rtz.xu.f.v vd, vs2, vm * Convert float to unsigned integer, truncating. @@ -4371,31 +4381,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define NOP_UU_B uint8_t, uint16_t, uint32_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ -RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) -RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1, clearb) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4, clearl) =20 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer= . */ -RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) -RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1, clearb) +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4, clearl) =20 /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to fl= oat */ -RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4, clearl) =20 /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ -RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4, clearl) =20 /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. = */ static uint16_t vfncvtffv16(uint32_t a, float_status *s) @@ -4403,10 +4418,54 @@ static uint16_t vfncvtffv16(uint32_t a, float_statu= s *s) return float32_to_float16(a, true, s); } =20 -RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) -RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4, clearl) + +/* + * vfncvt.rod.f.f.w vd, vs2, vm + * Convert double-width float to single-width float, rounding towards odd. + */ +static uint16_t vfncvtffv16_rod(uint32_t a, float_status *s) +{ + s->float_rounding_mode =3D float_round_to_odd; + return float32_to_float16(a, true, s); +} + +FCVT_ROD_F_F(float64, float32) +RVVCALL(OPFVV1, vfncvt_rod_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16_rod) +RVVCALL(OPFVV1, vfncvt_rod_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32_r= od) +GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_w, 4, 4, clearl) + +/* + * vfncvt.rtz.xu.f.w vd, vs2, vm + * Convert double-width float to unsigned integer, truncating. + */ +FCVT_RTZ_F_V(float16, uint8) +FCVT_RTZ_F_V(float32, uint16) +FCVT_RTZ_F_V(float64, uint32) +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8_rt= z) +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16_r= tz) +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32_r= tz) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_b, 1, 1, clearb) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_w, 4, 4, clearl) + +/* + * vfncvt.rtz.x.f.w vd, vs2, vm + * Convert double-width float to signed integer, truncating. + */ +FCVT_RTZ_F_V(float16, int8) +FCVT_RTZ_F_V(float32, int16) +FCVT_RTZ_F_V(float64, int32) +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8_rtz) +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16_rtz) +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32_rtz) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_b, 1, 1, clearb) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_w, 4, 4, clearl) =20 /* *** Vector Reduction Operations --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QSJ1bGauDFTOgyu9hOGxlnkT/w4hfR8pkrBU4Rw5V5g=; b=HjhZ2F4gv7Uu7C3rXpDpLHw4wz8hiqlxT6qS8+x4o2TE//yGi7O48zjIgE6fUSLhDM 5cVuY7s5ATOoA9RB3lA7Kh3fRFHoS873Hwo7lZqiIIfLwZ6XPFV4M21VEZ+M/6E2/imX Lb6VNcH2xE4vmAOGZBvDtQKjSv4AezK2naRlC2tOruCvxShsP3VFMFZ272VYahy7F7o9 0uMDo3EEY6YsMTDF29AwUWvsdJy9YybZI6mfrB29tCIGpgm1kuP8PLGvkZEcPDW2Ry8u zFArc7Xt8AO53HbMA1Lwj1dDhryAdchSkrjDiGzlkeo5L0dfsgm5TTJ+INXrmk9/spDk Malg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QSJ1bGauDFTOgyu9hOGxlnkT/w4hfR8pkrBU4Rw5V5g=; b=QlURzR24eGI4jnq5+Tf5i5uqcxsw1C4kqCrjm7LIzwQIIrbx90jugBXdfSCd+SkLLq Ogz5nQQbsnB5O90ObBD1MRjl5Yzt3stzFuy69jEIJGZloOhY4QcAWWW56JtQdhDwLQWd t156lGk/EzVhETjvBSoq2944rf7MSyIujy+OxCSwQCLMmYAk+77sUPs68zBK4oMb1nOg wJStcuAxp98Cfo2gPt1jhz/C0/zWDUGMUQs4+GPdJKCM8Nnk9X/EzAbOlldNcYml9GeP NJPY7ouNFT3CT0vlPtTjAdTvYKF5aywD9I2S25IYSm7psutKMNt8Eiry4iMv39aKkgyK ntWw== X-Gm-Message-State: AOAM5338th1nDABCrtQ1fuSgateJpiekTCUPHEtgv2yOxvf3h7t2pFvU 77YNbmBniOuhV5lAVcHy298GK2Gu9q0= X-Google-Smtp-Source: ABdhPJzuOYtwL+PSMas3So5P3JXz99kBSBRC++2v4n11BJfk73CrHvsRD8suY2dOP+SsFPXLzSn+mg== X-Received: by 2002:a17:90b:400f:: with SMTP id ie15mr8864355pjb.94.1595409761871; Wed, 22 Jul 2020 02:22:41 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 73/76] fpu: fix float16 nan check Date: Wed, 22 Jul 2020 17:16:36 +0800 Message-Id: <20200722091641.8834-74-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Chih-Min Chao , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chih-Min Chao 16 15 10 0 |sign | exp | mantissa | qNaN x 11111 1x_xxxx_xxxx The mask should check exp + msb of mantissa Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- fpu/softfloat-specialize.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index 44f5b661f8..fe7a5e79e4 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat-specialize.inc.c @@ -254,7 +254,7 @@ bool float16_is_quiet_nan(float16 a_, float_status *sta= tus) if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } else { - return ((a & ~0x8000) >=3D 0x7C80); + return ((a & ~0x8000) >=3D 0x7E00); } #endif } @@ -271,7 +271,7 @@ bool float16_is_signaling_nan(float16 a_, float_status = *status) #else uint16_t a =3D float16_val(a_); if (snan_bit_is_one(status)) { - return ((a & ~0x8000) >=3D 0x7C80); + return ((a & ~0x8000) >=3D 0x7E00); } else { return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); } --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411809; cv=none; d=zohomail.com; s=zohoarc; b=Z+vThYqjjpfaNnGKtrouOHRAoMgBiUcItfkwi5sZvPfdVTVRjcajiNfnMkRar4h/00gbU2dByv5zG3CkMXQABzJLJ5lMdl9VeiDH2mWyfZT4lbsSVXjZ86Lh0tornMLd4pBUQZCA1MG9IuEfVWED3Mdad9IDNXRkul59FXFSPY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411809; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Pi0ETlpWV5x2QnbEIJYiwXrfA/Q9GYlQx2rBVg7/nsg=; b=c+geFbyVSfkf84lSoIHL6m/lMTu9y/OKQbMu9rayMLrzCDkAKWDlFa0SbNCbLzwhnTMFKr/h3rcrfnL7FpTkil8KeyEP/+Idg9oKFUY/STYO9XVWmIqq4VaWQu6Y1P8evNP6zhN9dvCXBFWXMaDphrqkk1Z9YqUHyAO8lqrErBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595411809703961.1848178860137; Wed, 22 Jul 2020 02:56:49 -0700 (PDT) Received: from localhost ([::1]:48312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBUW-0006lY-GK for importer@patchew.org; Wed, 22 Jul 2020 05:56:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAxd-0008CA-VW for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:49 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:54168) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAxb-0006GQ-Gu for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:49 -0400 Received: by mail-pj1-x1031.google.com with SMTP id a9so870393pjd.3 for ; Wed, 22 Jul 2020 02:22:47 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pi0ETlpWV5x2QnbEIJYiwXrfA/Q9GYlQx2rBVg7/nsg=; b=m8AEGkIrfRpHFKMOp9MrXTcjNLBgys9u87LvgWsYfFzfF/IMcJIIorfYhVUpi5l6vW ERgX/OXiIEXl7oYZODR488XucGP+frLA6JYeBQDxcJ0ARSwKlFls6lZa+As/PeECjKY0 QCsTVJi1yLNJNUIXCxoZynHuFNSU8AQDPHgmi3S7JVjBlv6LolfiXzom9KLv45CY9B2P cJx4lkCc6acxgvIRJN4s1QaAMNlNUx1Xdb6jVmjY/iKKOacfhq6LsMmIR58ZcVza0siy CU53jYtCcBssos6V/cDZlNi3aSYGKQ57kPPjqh1AFgenVTCxCDlMr+ENPOTncCaYRuMa gmCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pi0ETlpWV5x2QnbEIJYiwXrfA/Q9GYlQx2rBVg7/nsg=; b=CvDhykVTUTXNvYZ+8bGnIQIfIeL4Hy0GYaICAN5e0hRozY99AYfjtjnWfQH43afpQL fPhAsrDljBuiVBYPFemO3N7PW8flt1pXmRkGj/RQXCvPmkP0+8Y1n7zBM1QEz/gtoYE0 nb+I4Xl6M4MI9DTZvVwOlPgwVsyyKJ/RksgekDZw0PQTC9jQp2Yh6qIKTrfIChIQcKFL 72Oa+4FeJhZEgzU+Z8X0f2Jvu2Dnt81Ty05kVTw9v5shkCNvP2A0onC3Z9cSBhaPuwPj K3dcTZfpc9xY6secJpFezYrlssNoh7rrtBTd134PzgcIN8qtx2PskhHOvuKQRoBuLVsZ 4/sw== X-Gm-Message-State: AOAM5338wyQP+DsjUifNN/TlFDmMvTLIEZgxQ5QG6BBCQb91yAL8llvb J7VTCZroPRRao6/Q4DrjmErHrn1ERso= X-Google-Smtp-Source: ABdhPJyBn3z5vNb3z6ChytI7djpTQusLCibyVpMk7Oe4KX0u99ydq29Ee2igZYNRL4LZaeJm4AENKQ== X-Received: by 2002:a17:90a:a10b:: with SMTP id s11mr9394459pjp.216.1595409766075; Wed, 22 Jul 2020 02:22:46 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map Date: Wed, 22 Jul 2020 17:16:37 +0800 Message-Id: <20200722091641.8834-75-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Hsiangkai Wang , Palmer Dabbelt , Bastian Koppelmann , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- gdb-xml/riscv-32bit-csr.xml | 11 ++++++----- gdb-xml/riscv-64bit-csr.xml | 11 ++++++----- target/riscv/gdbstub.c | 4 ++-- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml index da1bf19e2f..3d2031da7d 100644 --- a/gdb-xml/riscv-32bit-csr.xml +++ b/gdb-xml/riscv-32bit-csr.xml @@ -110,6 +110,8 @@ + + @@ -232,12 +234,11 @@ - - - - - + + + + diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml index 6aa4bed9f5..9039456293 100644 --- a/gdb-xml/riscv-64bit-csr.xml +++ b/gdb-xml/riscv-64bit-csr.xml @@ -110,6 +110,8 @@ + + @@ -232,12 +234,11 @@ - - - - - + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index eba12a86f2..f7c5212e27 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -418,13 +418,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 240, "riscv-32bit-csr.xml", 0); + 241, "riscv-32bit-csr.xml", 0); =20 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 240, "riscv-64bit-csr.xml", 0); + 241, "riscv-64bit-csr.xml", 0); =20 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-64bit-virtual.xml", 0); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595412072; cv=none; d=zohomail.com; s=zohoarc; b=E5pKeLxZtPQ/cuKSNdcBG9dvPMol12xxvb3ctAOWkEd3JaL8NDHcCT3pzmBTFFLLuyxVQDV/vQQJOy83pEjXgRXzIElIkbuxtJAyc1j7ac3zm3N7sEG4DV3AynoR0ECBnkjP9D+m7g56fwmknRmARFjD3X4kv4lKiYeNVZxGJRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595412072; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=MqJ1W7Xx6Rp4RwGFL/cojw2iykbesH1Xy4iT4eyuvxQ=; b=hyUoydrjjZEY4QHv3qpCBKEK8ikrTWdzh/2APA+hH49oJR6jWD6rHnK5wE80KrJPW7GBhJcJidQ6QWw6THqbVhBx7xKwoG5sWD+mhGtTAL0Dw3SPn7t0UJiJc52imM3jNXC8rwVHqcXAgEi5CClPeq06Dmfp9c0Vbn/lvobUPIg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1595412072355694.1143676900626; Wed, 22 Jul 2020 03:01:12 -0700 (PDT) Received: from localhost ([::1]:58460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jyBYk-0002dn-Q9 for importer@patchew.org; Wed, 22 Jul 2020 06:01:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jyAxi-0008Oj-IY for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:54 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:33099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jyAxg-0006H3-AY for qemu-devel@nongnu.org; Wed, 22 Jul 2020 05:22:54 -0400 Received: by mail-pg1-x531.google.com with SMTP id o13so895047pgf.0 for ; Wed, 22 Jul 2020 02:22:51 -0700 (PDT) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MqJ1W7Xx6Rp4RwGFL/cojw2iykbesH1Xy4iT4eyuvxQ=; b=TFK6oXAmpE4GwPcmKizc2c4ZIln0NzP4fFxg/NfqCom1NHwcWklZRlqClYmC0X8qJ9 F2n3h++8MAYoaWB5vU8Q6qwzuKmNo7EezJ5rNe6O842UiTxQLBHbTCcBTZIKr76VO+Ma zR23MRQjkR3spt4vj5QpFVlltkHZJ0oCTje12/av8xzTktHxEpksjMr5v8vV9UljJyeu KH6nnhZpweRyyy0/R0iE7fj27icmQxjFPT/IRd8A+j3fz20AW1IDgmJxxpUCQxo8qMqF FpvjrgtcuI9UEXvOJHkhzFimtaQyGHuZyuTwUpsmnDsnEvATkR9jnlRh3M/y8W/Qf7fw urGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MqJ1W7Xx6Rp4RwGFL/cojw2iykbesH1Xy4iT4eyuvxQ=; b=swTzphvvYL2bKJwjfat0GhFRNFkPv3mwOZO/QKfGRfWG/Pur2SeNU68APd2bzYZkSE 1lS/w3WxeUyFiTIRxogjQoKJC5V/1lYl1KDehcnavF1Ybr3uY+uV0INq415J1C6iHLjg gt3NlrYF6wSxccnpRPIxe9WamDzwNOmhB4mV7tnkdy81FoE7RpA8+U2wWXvXjkPn5ah2 Ng9f6T/3DfhbXx9VVj5IhNl68MIgarUzsVXKI5sI2XWpbq+2i1yzmwIPbRjJ4ROzVdAe wVUHXjos22wpVWRT/7UvqBynVaCykmWiEjlKsVAVb0SOkEly7GZRL0EAE31o3H7uiVzg OZEw== X-Gm-Message-State: AOAM531pzUpENnpkVzEHYbwRK6BVUnkestyhOAASegVLj9iV87Y80b6u cGUOeHur4HWMIFSeZtf8PfdKxsRwmfE= X-Google-Smtp-Source: ABdhPJwhk2+ZYsuIY7BNcbGN4g1i7wHjjy6Jdk7GL+Kf3tsx4uJzLz3KxIM4Ja0dBlRWDru1sTdAig== X-Received: by 2002:a05:6a00:2b0:: with SMTP id q16mr29635976pfs.79.1595409770535; Wed, 22 Jul 2020 02:22:50 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 Date: Wed, 22 Jul 2020 17:16:38 +0800 Message-Id: <20200722091641.8834-76-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x531.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Hsiangkai Wang , Richard Henderson , Laurent Vivier , Paolo Bonzini , Palmer Dabbelt , Bastian Koppelmann , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- configure | 2 +- gdb-xml/riscv-64bit-csr.xml | 7 ++++ gdb-xml/riscv-64bit-vector-128b.xml | 59 +++++++++++++++++++++++++++ gdb-xml/riscv-64bit-vector-256b.xml | 59 +++++++++++++++++++++++++++ gdb-xml/riscv-64bit-vector-512b.xml | 59 +++++++++++++++++++++++++++ target/riscv/gdbstub.c | 62 ++++++++++++++++++++++++++++- 6 files changed, 245 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/riscv-64bit-vector-128b.xml create mode 100644 gdb-xml/riscv-64bit-vector-256b.xml create mode 100644 gdb-xml/riscv-64bit-vector-512b.xml diff --git a/configure b/configure index ee6c3c6792..8d69013a97 100755 --- a/configure +++ b/configure @@ -8228,7 +8228,7 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" + gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml riscv-64bit-= vector-512b.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; rx) TARGET_ARCH=3Drx diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml index 9039456293..28a7c9a9f3 100644 --- a/gdb-xml/riscv-64bit-csr.xml +++ b/gdb-xml/riscv-64bit-csr.xml @@ -248,4 +248,11 @@ + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-128b.xml b/gdb-xml/riscv-64bit-vect= or-128b.xml new file mode 100644 index 0000000000..f6150968b3 --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-128b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-256b.xml b/gdb-xml/riscv-64bit-vect= or-256b.xml new file mode 100644 index 0000000000..6183846a35 --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-256b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-512b.xml b/gdb-xml/riscv-64bit-vect= or-512b.xml new file mode 100644 index 0000000000..78bb147cdf --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-512b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f7c5212e27..1681f883e4 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -268,6 +268,13 @@ static int csr_register_map[] =3D { CSR_MUCOUNTEREN, CSR_MSCOUNTEREN, CSR_MHCOUNTEREN, + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VCSR, + CSR_VL, + CSR_VTYPE, + CSR_VLENB, }; =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) @@ -351,6 +358,34 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8= _t *mem_buf, int n) return 0; } =20 +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt =3D 0; + for (i =3D 0; i < vlenb; i +=3D 8) { + cnt +=3D gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) +{ + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i =3D 0; i < vlenb; i +=3D 8) { + env->vreg[(n * vlenb + i) / 8] =3D ldq_p(mem_buf + i); + } + return vlenb; + } + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < ARRAY_SIZE(csr_register_map)) { @@ -416,15 +451,38 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa & RVV) { + /* TODO: support vlen other than 128, 256, 512 bits. */ + const char *vector_xml_name =3D NULL; + switch (cpu->cfg.vlen) { + case 128: + vector_xml_name =3D "riscv-64bit-vector-128b.xml"; + break; + case 256: + vector_xml_name =3D "riscv-64bit-vector-256b.xml"; + break; + case 512: + vector_xml_name =3D "riscv-64bit-vector-512b.xml"; + break; + default: + vector_xml_name =3D NULL; + break; + } + if (vector_xml_name) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, + riscv_gdb_set_vector, + 32, vector_xml_name, 0); + } + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 241, "riscv-32bit-csr.xml", 0); + 248, "riscv-32bit-csr.xml", 0); =20 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 241, "riscv-64bit-csr.xml", 0); + 248, "riscv-64bit-csr.xml", 0); =20 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-64bit-virtual.xml", 0); --=20 2.17.1 From nobody Fri May 17 21:20:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1595411304; cv=none; d=zohomail.com; s=zohoarc; b=VKOGArocBFYwf7nYmIMa2cRvYfnCoiFh8Y7bs3HHrmKQOWP6zV2M0Ri5BFZEhWsxZ+faEhUxViMVRW8EtSHCOphXiJP9SNESnKcBcNb07EtIC7PtWDW/95usjdMwvzvzeVg0J4B4Ct5o0/KDiWrbG2yaetElr7BfnycyXyt1s2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595411304; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=GIJ/UPBp2WO1BlyJ6/1RakPZrL4gW2QpybA3d/fh+SA=; b=KXGDmhqQLa3AFCH+dAtBxjdaUpFMGBC1v2kgUpZKeh6X6GaZO7iuACt7CnRKtnUivjPtEsVXEd/HudpxDK3ERONAYUDJInts1O6bOAe2YrsNLiHpL0pC+Pv4zlzORgpBIXWHldEbN9SMmCucP0DM4myr3LxIlalWQ1mdoaUofSo= ARC-Authentication-Results: i=1; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Laurent Vivier , Paolo Bonzini , Greentime Hu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greentime Hu This patch adds vector support for rv32 gdb. It allows gdb client to access vector registers correctly. Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 8d69013a97..dbe3c4e4c5 100755 --- a/configure +++ b/configure @@ -8222,7 +8222,7 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes - gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" + gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml riscv-64bit-= vector-512b.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=3Driscv --=20 2.17.1