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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Control this cpu feature via a machine property, much as we do with secure=3Don, since both require specialized support in the machine setup to be functional. Default MTE to off, since this feature implies extra overhead. Signed-off-by: Richard Henderson Message-id: 20200713213341.590275-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++----- target/arm/cpu.c | 19 +++++++++++-------- target/arm/cpu64.c | 5 +++-- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 54bcf17afd3..dff67e1bef0 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -140,6 +140,7 @@ typedef struct { bool its; bool virt; bool ras; + bool mte; OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9005dae356b..5866c4ce202 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1837,12 +1837,19 @@ static void machvirt_init(MachineState *machine) OBJECT(secure_sysmem), &error_abort); } =20 - /* - * The cpu adds the property if and only if MemTag is supported. - * If it is, we must allocate the ram to back that up. - */ - if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (vms->mte) { + /* Create the memory region only once, but link to all cpus. */ if (!tag_sysmem) { + /* + * The property exists only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (!object_property_find(cpuobj, "tag-memory", NULL)) { + error_report("MTE requested, but not supported " + "by the guest CPU"); + exit(1); + } + tag_sysmem =3D g_new(MemoryRegion, 1); memory_region_init(tag_sysmem, OBJECT(machine), "tag-memory", UINT64_MAX / 32); @@ -2061,6 +2068,20 @@ static void virt_set_ras(Object *obj, bool value, Er= ror **errp) vms->ras =3D value; } =20 +static bool virt_get_mte(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->mte; +} + +static void virt_set_mte(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + vms->mte =3D value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -2481,6 +2502,14 @@ static void virt_instance_init(Object *obj) "Set on/off to enable/disable reportin= g host memory errors " "to a KVM guest using ACPI and guest e= xternal abort exceptions"); =20 + /* MTE is disabled by default. */ + vms->mte =3D false; + object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte); + object_property_set_description(obj, "mte", + "Set on/off to enable/disable emulatin= g a " + "guest CPU which implements the ARM " + "Memory Tagging Extension"); + vms->irqmap =3D a15irqmap; =20 virt_flash_create(vms); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5050e1843a8..111579554fb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1698,6 +1698,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->id_pfr1 &=3D ~0xf000; } =20 +#ifndef CONFIG_USER_ONLY + if (cpu->tag_memory =3D=3D NULL && cpu_isar_feature(aa64_mte, cpu)) { + /* + * Disable the MTE feature bits if we do not have tag-memory + * provided by the machine. + */ + cpu->isar.id_aa64pfr1 =3D + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + } +#endif + /* MPU can be configured out of a PMSA CPU either by setting has-mpu * to false or by setting pmsav7-dregion to 0. */ @@ -1787,14 +1798,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", cpu->secure_tag_memory); } - } else if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Since there is no tag memory, we can't meaningfully support MTE - * to its fullest. To avoid problems later, when we would come to - * use the tag memory, downgrade support to insns only. - */ - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); } =20 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 15494002d20..dd696183dfb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -646,8 +646,9 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr1; t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* - * Begin with full support for MTE; will be downgraded to MTE=3D1 - * during realize if the board provides no tag memory. + * Begin with full support for MTE. This will be downgraded to MTE= =3D0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 =3D t; --=20 2.20.1