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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 10 Jul 2020 08:57:17 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , LIU Zhiwei , Alistair Francis , Greentime Hu , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++++++ 4 files changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..871c2ddfa1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause =3D 0; env->pc =3D env->resetvec; + env->vlenb =3D cpu->cfg.vlen >> 3; #endif cs->exception_index =3D EXCP_NONE; env->load_res =3D -1; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c02690ed0d..81c85bf4c2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,6 +111,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + target_ulong vlenb; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 79ae0accbc..62789e3720 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -63,6 +63,7 @@ #define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 =20 /* VCSR fields */ #define VCSR_VXSAT_SHIFT 0 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 77d371f385..6b05c631f4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -197,6 +197,12 @@ static int read_vtype(CPURISCVState *env, int csrno, t= arget_ulong *val) return 0; } =20 +static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vlenb; + return 0; +} + static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->vl; @@ -1301,6 +1307,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_VCSR] =3D { vs, read_vcsr, write_vcsr = }, [CSR_VL] =3D { vs, read_vl = }, [CSR_VTYPE] =3D { vs, read_vtype = }, + [CSR_VLENB] =3D { vs, read_vlenb = }, /* User Timers and Counters */ [CSR_CYCLE] =3D { ctr, read_instret = }, [CSR_INSTRET] =3D { ctr, read_instret = }, --=20 2.17.1