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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id 65sm2253337wma.48.2020.07.07.11.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2020 11:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zsTv03VARaihe+oGT92uCGB4KZTAlGdB70IybG3Qeu4=; b=edDvCar2cn9eMjXOdlh2Y7NDKzzd593p4RCZTIwlYx/SuoBwEFWjKEtqfR2kdKsFy7 Mj44IjIKC3P0dEgF49Q4v12NNPAy7/7RALlpf4LbwiBmklqjsupAVm6xSvwavRfCaIiS 3qo3C5P8KVemVSffLchjtt80ORMl8o9L1mdmvRBmTB1QoJUHlScSpNkybv74PIoAmC3v Vvq3BGahvW90KIZgNT8FSNOwoF2KZV/oH766WcRZ8zhHsiVSs3zl+xrybO7hQWdeqnHa WjouK4kpqeBDhO8+y0hqzNvJ4JyNQgou3aL7UI5olmhet5EdiyQum2Xk0/1gmUME+ot6 fhxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zsTv03VARaihe+oGT92uCGB4KZTAlGdB70IybG3Qeu4=; b=cmZYcnHOJaLk3jnC+vMxQJ7mCttfeyoZNgmvem85wGdI/i5Sb5raRzlZSWCgxq+o9K 9g/5r4r6dtrUPwJUS+bqtq55jDYcQuFno4uO5LQL+vWYj6nEstlwVB3F1gHQQDKJW8+L wBTgtMlCJbTD2w/gc3ZEfnQab1/rFqmS5g7uHT5l7xv23JMZEnfaxglgxHgGT9d+MLQ4 7CDM4t+3wbLDxzUodxO0DK7cyh8wOpZh3S2RLfBOOYdpEOmnFkhHt4isCpvVOLDPW4ld /IN+MdERe1VE+HYl1jcrGzWr0+utHDQmaMePxuJ+OId3eP0nx53EHhmOGQJ3Z22kGpwW yrsQ== X-Gm-Message-State: AOAM530/8QnR7s5+K2VhfR8iRyytP7WXbO8GdOlO9vo/rVekDVY6G+Ek O/2lPBgxm41tQytXAAXo1G7djpyH X-Google-Smtp-Source: ABdhPJzlmqyfprzO9P3m8lD9u//smozCTVLQkk/fTb/HItQPf8oOoZHBIyUKGG1WjPUulDbE6GK6xA== X-Received: by 2002:a1c:2392:: with SMTP id j140mr5338922wmj.6.1594145870108; Tue, 07 Jul 2020 11:17:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 23/32] hw/misc: avr: Add limited support for power reduction device Date: Tue, 7 Jul 2020 20:17:01 +0200 Message-Id: <20200707181710.30950-24-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200707181710.30950-1-f4bug@amsat.org> References: <20200707181710.30950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Sarah Harris , Eduardo Habkost , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cleber Rosa , Richard Henderson , Markus Armbruster , Wainer dos Santos Moschetta , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Michael Rolnik , Paolo Bonzini , Pavel Dovgalyuk , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Michael Rolnik This is a simple device of just one register, and whenever this register is written to it calls qemu_set_irq function for each of 8 bits/IRQs. It is used to implement AVR Power Reduction. [AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by: Aleksandar Markovic Signed-off-by: Michael Rolnik Signed-off-by: Philippe Mathieu-Daud=C3=A9 [rth: Squash include fix and file rename from f4bug] Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Thomas Huth Message-Id: <20200705140315.260514-22-huth@tuxfamily.org> --- include/hw/misc/avr_power.h | 46 +++++++++++++++ hw/misc/avr_power.c | 113 ++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 2 + hw/misc/trace-events | 4 ++ 6 files changed, 170 insertions(+) create mode 100644 include/hw/misc/avr_power.h create mode 100644 hw/misc/avr_power.c diff --git a/include/hw/misc/avr_power.h b/include/hw/misc/avr_power.h new file mode 100644 index 0000000000..e08e44f629 --- /dev/null +++ b/include/hw/misc/avr_power.h @@ -0,0 +1,46 @@ +/* + * AVR Power Reduction Management + * + * Copyright (c) 2019-2020 Michael Rolnik + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MISC_AVR_POWER_H +#define HW_MISC_AVR_POWER_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + + +#define TYPE_AVR_MASK "avr-power" +#define AVR_MASK(obj) OBJECT_CHECK(AVRMaskState, (obj), TYPE_AVR_MASK) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion iomem; + + uint8_t val; + qemu_irq irq[8]; +} AVRMaskState; + +#endif /* HW_MISC_AVR_POWER_H */ diff --git a/hw/misc/avr_power.c b/hw/misc/avr_power.c new file mode 100644 index 0000000000..a5412f2cfe --- /dev/null +++ b/hw/misc/avr_power.c @@ -0,0 +1,113 @@ +/* + * AVR Power Reduction Management + * + * Copyright (c) 2019-2020 Michael Rolnik + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/misc/avr_power.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/irq.h" +#include "trace.h" + +static void avr_mask_reset(DeviceState *dev) +{ + AVRMaskState *s =3D AVR_MASK(dev); + + s->val =3D 0x00; + + for (int i =3D 0; i < 8; i++) { + qemu_set_irq(s->irq[i], 0); + } +} + +static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size) +{ + assert(size =3D=3D 1); + assert(offset =3D=3D 0); + AVRMaskState *s =3D opaque; + + trace_avr_power_read(s->val); + + return (uint64_t)s->val; +} + +static void avr_mask_write(void *opaque, hwaddr offset, + uint64_t val64, unsigned size) +{ + assert(size =3D=3D 1); + assert(offset =3D=3D 0); + AVRMaskState *s =3D opaque; + uint8_t val8 =3D val64; + + trace_avr_power_write(val8); + s->val =3D val8; + for (int i =3D 0; i < 8; i++) { + qemu_set_irq(s->irq[i], (val8 & (1 << i)) !=3D 0); + } +} + +static const MemoryRegionOps avr_mask_ops =3D { + .read =3D avr_mask_read, + .write =3D avr_mask_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .max_access_size =3D 1, + }, +}; + +static void avr_mask_init(Object *dev) +{ + AVRMaskState *s =3D AVR_MASK(dev); + SysBusDevice *busdev =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK, + 0x01); + sysbus_init_mmio(busdev, &s->iomem); + + for (int i =3D 0; i < 8; i++) { + sysbus_init_irq(busdev, &s->irq[i]); + } + s->val =3D 0x00; +} + +static void avr_mask_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D avr_mask_reset; +} + +static const TypeInfo avr_mask_info =3D { + .name =3D TYPE_AVR_MASK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AVRMaskState), + .class_init =3D avr_mask_class_init, + .instance_init =3D avr_mask_init, +}; + +static void avr_mask_register_types(void) +{ + type_register_static(&avr_mask_info); +} + +type_init(avr_mask_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 61a6017342..443b377a72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -987,6 +987,8 @@ F: include/hw/char/avr_usart.h F: hw/char/avr_usart.c F: include/hw/timer/avr_timer16.h F: hw/timer/avr_timer16.c +F: include/hw/misc/avr_power.h +F: hw/misc/avr_power.c =20 CRIS Machines ------------- diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index bdd77d8020..92c397ca07 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -131,4 +131,7 @@ config MAC_VIA select MOS6522 select ADB =20 +config AVR_POWER + bool + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 5aaca8a039..6be3d255ab 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -91,3 +91,5 @@ common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o obj-$(CONFIG_MAC_VIA) +=3D mac_via.o =20 common-obj-$(CONFIG_GRLIB) +=3D grlib_ahb_apb_pnp.o + +obj-$(CONFIG_AVR_POWER) +=3D avr_power.o diff --git a/hw/misc/trace-events b/hw/misc/trace-events index ebea53735c..066752aa90 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -19,6 +19,10 @@ allwinner_h3_dramphy_write(uint64_t offset, uint64_t dat= a, unsigned size) "write allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset = 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset= 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 =20 +# avr_power.c +avr_power_read(uint8_t value) "power_reduc read value:%u" +avr_power_write(uint8_t value) "power_reduc write value:%u" + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" --=20 2.21.3