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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id 65sm2253337wma.48.2020.07.07.11.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2020 11:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K8Od5RoTrgZHXT0STiHKBSYH0Kuox0fs2mOyzEFa/Yg=; b=nyV2KIsllIk9bJ2/1vkkafWPHrdM0pumAZ3pvSPF5sUWrB6G+3qXZwJ9IwVOMI8kIi 9q3oy4XEu0j6CXqq0ZbcLl/5EIcdecSSkd7LSUjWLKopihGrJhXaXDTBbzsChTPmsBw0 oi6evbzeYGMzB9zX8CksDHVPkMVIBU9p/xYMFqD4ltxHUtilUdOb8yy2Knd4G/Eo40kh anBq1GCLFAdYwK0LuSxSY+Te47FqJEy4RJGnoZmY+Fd6xeVGibQWASCqKhrufkHHVI6+ onsYeYiwMc/Rsr77Iw6LnHawK88I9P7uVdGJOlZ0LZ4w9Y6npm7HU2clUhaozIxIB4LB sYaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=K8Od5RoTrgZHXT0STiHKBSYH0Kuox0fs2mOyzEFa/Yg=; b=EU8U+IZPv4l4IIZTEF9VMbGbP1wQ7HV7tKardJQCzO6bGZclGFHbNO40m1f6thritt gPFEdJgM++vVALXcqNWtFOQSLEafz2LvkxWvDjukCI48vXHMCtUNcSe3X4Zw2Zrs3A29 R+YwWA49XFoNBBZY5ka3UnB6VjaePXAibxK8Psv5fvZlOEXC/R+uyPTh9BmODq9/1kj3 3GN30/+GOmdUB652XFzJ7Z6e9xDygpZspp4RTZ1HnPBvd3Pcn82DzC1v19FtUNl/HzdS /Kg5VT8lRqcZRNTgtVtIRgWu6KQPlsWIk0yKvL48gcCjXB5QYrq+Fcw1EeC05IgVrrOS wS2Q== X-Gm-Message-State: AOAM530iyTGXqpUeSyGKrffAXSHeas4v+kEhyCuymQjFfCzVioqBsHFB rcXHuL1A1ukr/8lS+9NF0WUZSaP3 X-Google-Smtp-Source: ABdhPJyFhPzdbxlpwFdFdNFnmlb4BXAe03iYfjiUozqfHROQon3iGjz8x+6grY/hBhz2XsEPL/rXKg== X-Received: by 2002:a05:600c:21ca:: with SMTP id x10mr5377021wmj.63.1594145857464; Tue, 07 Jul 2020 11:17:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 15/32] target/avr: Add instruction translation - MCU Control Instructions Date: Tue, 7 Jul 2020 20:16:53 +0200 Message-Id: <20200707181710.30950-16-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200707181710.30950-1-f4bug@amsat.org> References: <20200707181710.30950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Sarah Harris , Eduardo Habkost , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cleber Rosa , Richard Henderson , Markus Armbruster , Wainer dos Santos Moschetta , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Michael Rolnik , Paolo Bonzini , Pavel Dovgalyuk , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Michael Rolnik This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Signed-off-by: Thomas Huth Message-Id: <20200705140315.260514-16-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/insn.decode | 8 ++++++ target/avr/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 7bb6ce7495..482c23ad0c 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -177,3 +177,11 @@ BST 1111 101 rd:5 0 bit:3 BLD 1111 100 rd:5 0 bit:3 BSET 1001 0100 0 bit:3 1000 BCLR 1001 0100 1 bit:3 1000 + +# +# MCU Control Instructions +# +BREAK 1001 0101 1001 1000 +NOP 0000 0000 0000 0000 +SLEEP 1001 0101 1000 1000 +WDR 1001 0101 1010 1000 diff --git a/target/avr/translate.c b/target/avr/translate.c index 884fbb6081..ee7811995a 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2740,3 +2740,68 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *= a) =20 return true; } + +/* + * MCU Control Instructions + */ + +/* + * The BREAK instruction is used by the On-chip Debug system, and is + * normally not used in the application software. When the BREAK instruct= ion is + * executed, the AVR CPU is set in the Stopped Mode. This gives the On-ch= ip + * Debugger access to internal resources. If any Lock bits are set, or e= ither + * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BRE= AK + * instruction as a NOP and will not enter the Stopped mode. This instru= ction + * is not available in all devices. Refer to the device specific instruct= ion + * set summary. + */ +static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a) +{ + if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) { + return true; + } + +#ifdef BREAKPOINT_ON_BREAK + tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); + gen_helper_debug(cpu_env); + ctx->bstate =3D DISAS_EXIT; +#else + /* NOP */ +#endif + + return true; +} + +/* + * This instruction performs a single cycle No Operation. + */ +static bool trans_NOP(DisasContext *ctx, arg_NOP *a) +{ + + /* NOP */ + + return true; +} + +/* + * This instruction sets the circuit in sleep mode defined by the MCU + * Control Register. + */ +static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) +{ + gen_helper_sleep(cpu_env); + ctx->bstate =3D DISAS_NORETURN; + return true; +} + +/* + * This instruction resets the Watchdog Timer. This instruction must be + * executed within a limited time given by the WD prescaler. See the Watc= hdog + * Timer hardware specification. + */ +static bool trans_WDR(DisasContext *ctx, arg_WDR *a) +{ + gen_helper_wdr(cpu_env); + + return true; +} --=20 2.21.3