From nobody Tue Feb 10 19:53:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1593957987; cv=none; d=zohomail.com; s=zohoarc; b=Laf08zHzOOQeP7b6JfsCwla+E51FdnXi9H/kYOz8aWNZG8nOlyWY0wW+UJHpbsqBBxGUYURufaiYghW1WJAksXANZQZJuA33tv14isHe61gHuYEKzAsLbVAHXBO/2AKCBxTjPagDVPQj7UD3Hp/1PMupP/fkc+oBXimCNYJtqhg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593957987; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nU3NyJ2X7Xjxmum7XHMBSlsCJUfYlHu47F6ZvOe+oHc=; b=LaSNM+uId8l/82rG2r/1Pax/0OiU6t4TkONuzMfyzNJzAffCzn1x61m+HDhx06UwWPfr740P2DtVVsd6CbH7vbuWSoAl7SoZ87XrulLd/I6ea3u9o/XR6tVjhlf/7gI3VskpgtPOP4x1t0uoUT2qrAWIV7Z22oYUqHC9CyOyxiY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593957987384685.8380080740495; Sun, 5 Jul 2020 07:06:27 -0700 (PDT) Received: from localhost ([::1]:51600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1js5Hm-0004T8-5P for importer@patchew.org; Sun, 05 Jul 2020 10:06:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1js5F9-0007TG-M3 for qemu-devel@nongnu.org; Sun, 05 Jul 2020 10:03:43 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:43881) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1js5F8-0008K0-37 for qemu-devel@nongnu.org; Sun, 05 Jul 2020 10:03:43 -0400 Received: by mail-ed1-f66.google.com with SMTP id d15so32287079edm.10 for ; Sun, 05 Jul 2020 07:03:41 -0700 (PDT) Received: from thl530.multi.box (pd9e83654.dip0.t-ipconnect.de. [217.232.54.84]) by smtp.gmail.com with ESMTPSA id bq8sm10941776ejb.103.2020.07.05.07.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jul 2020 07:03:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nU3NyJ2X7Xjxmum7XHMBSlsCJUfYlHu47F6ZvOe+oHc=; b=GwhTkmwGEa4Vm+mqnoEhVcl6eQiI2kapuHjIhU6gJCarspDwP7rXhqgYRlK81rg5lU cYemh2Syx8Ri34g0cwgR/KR+STrNhEcdKnXEhuI0bE1YS+cfr4vpgvTLTDNJ3zk8eMCE hedJv8q4xOnGUISLWtXsdYTeKd+j1atYGA6PkR0eqjd+MB/1cfZYckGPFYqqCpwb+Imm uyZXhvBabJvjXdRZ+B19a4oKsPbvWFuUp9TCeCARX5opMbVniaBnGe/9zmwy5thp3oUE jw8C+nSi/EixI1UohQcxgCPtt2gHwomt09SrAcEnPzigfvicQYIzpqo+8X7AbyffJpZQ tn1w== X-Gm-Message-State: AOAM532ssY3mYoUs9DBNYGsswhVJ+bZQnPOaZQ+f1PX88q/mv+qZCzHk hGLWpwXbpKX8VUQBG5yZFO9rwkD/ X-Google-Smtp-Source: ABdhPJxWHeFwrO5zLaHELOD5KyZWEjJ9OST3UzH2kJfjL3yLxZJQ4dqNl1w3xptyn3Hkfi8BtNGnpg== X-Received: by 2002:a05:6402:787:: with SMTP id d7mr49325784edy.46.1593957820629; Sun, 05 Jul 2020 07:03:40 -0700 (PDT) From: Thomas Huth To: qemu-devel@nongnu.org, Michael Rolnik , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH rc6 17/30] target/avr: Initialize TCG register variables Date: Sun, 5 Jul 2020 16:03:02 +0200 Message-Id: <20200705140315.260514-18-huth@tuxfamily.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200705140315.260514-1-huth@tuxfamily.org> References: <20200705140315.260514-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.208.66; envelope-from=th.huth@gmail.com; helo=mail-ed1-f66.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/05 10:03:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Rolnik Initialize TCG register variables. Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic Signed-off-by: Thomas Huth --- target/avr/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index a6e67488df..becf096c12 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -129,6 +129,36 @@ struct DisasContext { }; =20 =20 +void avr_cpu_tcg_init(void) +{ + int i; + +#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) + cpu_pc =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); + cpu_Cf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); + cpu_Zf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); + cpu_Nf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); + cpu_Vf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); + cpu_Sf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); + cpu_Hf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); + cpu_Tf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); + cpu_If =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); + cpu_rampD =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "ra= mpD"); + cpu_rampX =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "ra= mpX"); + cpu_rampY =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "ra= mpY"); + cpu_rampZ =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "ra= mpZ"); + cpu_eind =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind= "); + cpu_sp =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); + cpu_skip =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip= "); + + for (i =3D 0; i < NUMBER_OF_CPU_REGISTERS; i++) { + cpu_r[i] =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), + reg_names[i]); + } +#undef AVR_REG_OFFS +} + + static int to_regs_16_31_by_one(DisasContext *ctx, int indx) { return 16 + (indx % 16); --=20 2.26.2