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bh=LDpaYhPZ/FHMcFEBo2iduOx48Ch9dqf1Z0IyUm32XR4=; b=KAbszJhx8UjpAOBcmHSpCBoZ5w871Z3g63ht1wIW/Q5WDEcnwiyIc06cYJzBxt9+2UGsuP atC+AC31XTQXWs3O5PW1Rc0lBDLVsjOqq6CoL7GE4AyvzpxIML1j4Zn30EcdkQxNM9GFFs oaYQUV8LWWBWUPxGLV+1Yz0zBgaRaqY= X-MC-Unique: oLbRihpdMoCt7vFd8brXeA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Date: Thu, 2 Jul 2020 17:26:51 +0200 Message-Id: <20200702152659.8522-2-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Page and block PTE decoding can share some code. Let's first handle table PTE and factorize some code shared by page and block PTEs. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - restore goto error in case get_pte() fails --- hw/arm/smmu-common.c | 48 ++++++++++++++++---------------------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e13a5f4a7c..a3f9e47398 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -186,7 +186,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); - uint64_t pte; + uint64_t pte, gpa; dma_addr_t pte_addr =3D baseaddr + offset * sizeof(pte); uint8_t ap; =20 @@ -199,56 +199,42 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { trace_smmu_ptw_invalid_pte(stage, level, baseaddr, pte_addr, offset, pte); - info->type =3D SMMU_PTW_ERR_TRANSLATION; - goto error; + break; } =20 - if (is_page_pte(pte, level)) { - uint64_t gpa =3D get_page_pte_address(pte, granule_sz); + if (is_table_pte(pte, level)) { + ap =3D PTE_APTABLE(pte); =20 - ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + baseaddr =3D get_table_pte_address(pte, granule_sz); + level++; + continue; + } else if (is_page_pte(pte, level)) { + gpa =3D get_page_pte_address(pte, granule_sz); trace_smmu_ptw_page_pte(stage, level, iova, baseaddr, pte_addr, pte, gpa); - return 0; - } - if (is_block_pte(pte, level)) { + } else { uint64_t block_size; - hwaddr gpa =3D get_block_pte_address(pte, level, granule_sz, - &block_size); - - ap =3D PTE_AP(pte); - if (is_permission_fault(ap, perm)) { - info->type =3D SMMU_PTW_ERR_PERMISSION; - goto error; - } =20 + gpa =3D get_block_pte_address(pte, level, granule_sz, + &block_size); trace_smmu_ptw_block_pte(stage, level, baseaddr, pte_addr, pte, iova, gpa, block_size >> 20); - - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); - return 0; } - - /* table pte */ - ap =3D PTE_APTABLE(pte); - + ap =3D PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type =3D SMMU_PTW_ERR_PERMISSION; goto error; } - baseaddr =3D get_table_pte_address(pte, granule_sz); - level++; - } =20 + tlbe->translated_addr =3D gpa + (iova & mask); + tlbe->perm =3D PTE_AP_TO_PERM(ap); + return 0; + } info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1593704210; cv=none; d=zohomail.com; s=zohoarc; b=Vsf/1aVuCwtrNpZPKWkUMwV/REx7Dt45By90LqA5HrovfaspfRiYD8xzhkca8gPZymlUwuDh70QvV1VOunzSacRYzMPH8RiqnW46+QHVrSsAxpNGMtDihkRoxNUzYmmSZUEpXyFGOeiMWv2sVw+j/XXeNVYz+WeFPCTDiq8gNyk= ARC-Message-Signature: i=1; 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Thu, 2 Jul 2020 15:27:24 +0000 (UTC) Received: from laptop.redhat.com (ovpn-112-70.ams2.redhat.com [10.36.112.70]) by smtp.corp.redhat.com (Postfix) with ESMTP id 033DF5DD61; Thu, 2 Jul 2020 15:27:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593703647; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WuZ2FwmRJiypa21uDwerc5RiK2LDWiVltIu8BgP89UA=; b=aaE6f4k2XOiZ6RAbfROIC01OKtnNTkM9WNLAU08snwxIZqB5fS1MDoFqhos39oK8bzADil r0xBRw46THlXNxnNgzx9dYKXMskAKl0MmsYufgJ+EIvY59OBI54ygqUPYujMxSiBfrO8if xyyjZaGhiooUSzb2i8/mkorZpJK20tw= X-MC-Unique: 2o8-obZuPcC1KD3AaHv8qQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 2/9] hw/arm/smmu-common: Add IOTLB helpers Date: Thu, 2 Jul 2020 17:26:52 +0200 Message-Id: <20200702152659.8522-3-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Add two helpers: one to lookup for a given IOTLB entry and one to insert a new entry. We also move the tracing there. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- include/hw/arm/smmu-common.h | 2 ++ hw/arm/smmu-common.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 26 ++------------------------ hw/arm/trace-events | 5 +++-- 4 files changed, 43 insertions(+), 26 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index ca4a4b1ad1..1dceec5cb1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index a3f9e47398..f3aa581f80 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,6 +32,42 @@ =20 /* IOTLB Management */ =20 +IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) +{ + SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + + if (entry) { + cfg->iotlb_hits++; + trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)); + } else { + cfg->iotlb_misses++; + trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + cfg->iotlb_hits, cfg->iotlb_misses, + 100 * cfg->iotlb_hits / + (cfg->iotlb_hits + cfg->iotlb_misses)= ); + } + return entry; +} + +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +{ + SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + + if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { + smmu_iotlb_inv_all(bs); + } + + key->asid =3D cfg->asid; + key->iova =3D entry->iova; + trace_smmu_iotlb_insert(cfg->asid, entry->iova); + g_hash_table_insert(bs->iotlb, key, entry); +} + inline void smmu_iotlb_inv_all(SMMUState *s) { trace_smmu_iotlb_inv_all(); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 57a79df55b..cd2a2e7e14 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -636,7 +636,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; - SMMUIOTLBKey key, *new_key; =20 qemu_mutex_lock(&s->mutex); =20 @@ -675,16 +674,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - key.asid =3D cfg->asid; - key.iova =3D aligned_addr; - - cached_entry =3D g_hash_table_lookup(bs->iotlb, &key); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - cfg->iotlb_hits++; - trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { @@ -698,16 +689,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, goto epilogue; } =20 - cfg->iotlb_misses++; - trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask, - cfg->iotlb_hits, cfg->iotlb_misses, - 100 * cfg->iotlb_hits / - (cfg->iotlb_hits + cfg->iotlb_misses)); - - if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { - smmu_iotlb_inv_all(bs); - } - cached_entry =3D g_new0(IOMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { @@ -753,10 +734,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, } status =3D SMMU_TRANS_ERROR; } else { - new_key =3D g_new0(SMMUIOTLBKey, 1); - new_key->asid =3D cfg->asid; - new_key->iova =3D aligned_addr; - g_hash_table_insert(bs->iotlb, new_key, cached_entry); + smmu_iotlb_insert(bs, cfg, cached_entry); status =3D SMMU_TRANS_SUCCESS; } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..b808a1bfc1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" +smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" @@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr,= bool leaf) "vmid =3D%d a smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" -smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t = miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d mi= ss=3D%d hit rate=3D%d" -smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d = miss=3D%d hit rate=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=S3NFNYSrX7syMo104tWcXIgZ34cLFK5JYwxiQJRSUHU=; b=b+lRJs8A7L0QFNZLab0v7olaqFPPNv0UWuEg6DfEU1GEKAfHQd7/E1xg2KdK+dg31j3mcz hep0ZmHMNKfQ+xBj0ApW5a8L/gUhRjIIESgk4UP/oePVuzXnN9ECvaMUjz1fLGI5RTqkKi +stRuw/hattmbtwKaj0ETC/YrJYi//I= X-MC-Unique: XpmiJm--NoWvDCE3vSfOoA-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 3/9] hw/arm/smmu: Introduce smmu_get_iotlb_key() Date: Thu, 2 Jul 2020 17:26:53 +0200 Message-Id: <20200702152659.8522-4-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce the smmu_get_iotlb_key() helper and the SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and smmu_iotlb_key_hash in the IOTLB related code section. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - creation --- hw/arm/smmu-internal.h | 1 + include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 66 ++++++++++++++++++++---------------- 3 files changed, 38 insertions(+), 30 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 7794d6d394..3104f768cd 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -96,4 +96,5 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 +#define SMMU_IOTLB_ASID(key) ((key).asid) #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 1dceec5cb1..5f9f3535d2 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -155,6 +155,7 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index f3aa581f80..7dc8541e8b 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -32,10 +32,42 @@ =20 /* IOTLB Management */ =20 +static guint smmu_iotlb_key_hash(gconstpointer v) +{ + SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; + uint32_t a, b, c; + + /* Jenkins hash */ + a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); + a +=3D key->asid; + b +=3D extract64(key->iova, 0, 32); + c +=3D extract64(key->iova, 32, 32); + + __jhash_mix(a, b, c); + __jhash_final(a, b, c); + + return c; +} + +static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) +{ + const SMMUIOTLBKey *k1 =3D v1; + const SMMUIOTLBKey *k2 =3D v2; + + return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); +} + +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +{ + SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + + return key; +} + IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova) { - SMMUIOTLBKey key =3D {.asid =3D cfg->asid, .iova =3D iova}; + SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { @@ -62,8 +94,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, = IOMMUTLBEntry *entry) smmu_iotlb_inv_all(bs); } =20 - key->asid =3D cfg->asid; - key->iova =3D entry->iova; + *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); trace_smmu_iotlb_insert(cfg->asid, entry->iova); g_hash_table_insert(bs->iotlb, key, entry); } @@ -80,12 +111,12 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, uint16_t asid =3D *(uint16_t *)user_data; SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; =20 - return iotlb_key->asid =3D=3D asid; + return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova); =20 trace_smmu_iotlb_inv_iova(asid, iova); g_hash_table_remove(s->iotlb, &key); @@ -383,31 +414,6 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_= t sid) return NULL; } =20 -static guint smmu_iotlb_key_hash(gconstpointer v) -{ - SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; - uint32_t a, b, c; - - /* Jenkins hash */ - a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid; - b +=3D extract64(key->iova, 0, 32); - c +=3D extract64(key->iova, 32, 32); - - __jhash_mix(a, b, c); - __jhash_final(a, b, c); - - return c; -} - -static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) -{ - const SMMUIOTLBKey *k1 =3D v1; - const SMMUIOTLBKey *k2 =3D v2; - - return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); -} - /* Unmap the whole notifier's range */ static void smmu_unmap_notifier_range(IOMMUNotifier *n) { --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=C4qLqUFnjHc7wzCPN/LQ1XBPh1dVzrlm59KIf9UKpNI=; b=SDrJineXFohaQ+QDJKOmPCqatbLBhI1sOIjZR0s6geUTq8Pnkp8s83Wg1Ld+o34+yBiY+M CLBz1cMj1C3Qj42KV0BScTJTFokS/PXlot+PVHV6D4UoC5/O7guK/GJPfsXbB3TsgulBJ2 3q907M7XPZS/5BX4pFXDJBg1+NmWljw= X-MC-Unique: SOYhJYvxPsO4tZsivXU2sw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 4/9] hw/arm/smmu: Simplify the IOTLB key format Date: Thu, 2 Jul 2020 17:26:54 +0200 Message-Id: <20200702152659.8522-5-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Instead of using a Jenkins hash function to generate the key let's just use a 64 bit unsigned integer that contains the asid and the 40 upper bits of the iova. A maximum of 52-bit IOVA is supported. This change in the key format also prepares for the addition of new fields in subsequent patches (granule and level). Signed-off-by: Eric Auger --- v1 -> v2: - split the inital patch into 2 patches and keep SMMUIOTLBKey type --- hw/arm/smmu-internal.h | 5 ++++- include/hw/arm/smmu-common.h | 5 +---- hw/arm/smmu-common.c | 23 +++-------------------- 3 files changed, 8 insertions(+), 25 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 3104f768cd..2ecb6f1dc6 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -96,5 +96,8 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 -#define SMMU_IOTLB_ASID(key) ((key).asid) +#define SMMU_IOTLB_ASID_SHIFT 40 + +#define SMMU_IOTLB_ASID(key) (((key) >> SMMU_IOTLB_ASID_SHIFT) & 0xFFFF) +#define SMMU_IOTLB_IOVA(key) (((key) & MAKE_64BIT_MASK(0, 40)) << 12) #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 5f9f3535d2..455d7855b2 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -88,10 +88,7 @@ typedef struct SMMUPciBus { SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc= */ } SMMUPciBus; =20 -typedef struct SMMUIOTLBKey { - uint64_t iova; - uint16_t asid; -} SMMUIOTLBKey; + typedef uint64_t SMMUIOTLBKey; =20 typedef struct SMMUState { /* */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 7dc8541e8b..5e85e30bdf 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -34,34 +34,17 @@ =20 static guint smmu_iotlb_key_hash(gconstpointer v) { - SMMUIOTLBKey *key =3D (SMMUIOTLBKey *)v; - uint32_t a, b, c; - - /* Jenkins hash */ - a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid; - b +=3D extract64(key->iova, 0, 32); - c +=3D extract64(key->iova, 32, 32); - - __jhash_mix(a, b, c); - __jhash_final(a, b, c); - - return c; + return (guint)*(const uint64_t *)v; } =20 static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) { - const SMMUIOTLBKey *k1 =3D v1; - const SMMUIOTLBKey *k2 =3D v2; - - return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova); + return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); } =20 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova}; - - return key; + return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; } =20 IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1593704026; cv=none; d=zohomail.com; s=zohoarc; b=bTj/EPBKX0JPHRtse+enjhRIT0KxEA4Z1Eb57JMH0KQu7+Tbjb8iWnGBaZQfHxGayqnlXQK0jAVZP2HmDPwSPMKWsZCifP7Iq8PQrCLcwolOwf1YCCFqlx5nsZf1JV3J9AylE1DHosytj8Qtjp6Z9og7DVqygQ2rA8XbSWUwxYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593704026; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593703666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WElSrA+VgEgLTbsGU0boHiHVCWxJc+bqwwm1EkQuJN0=; b=dNrVkg2yZQfM3iK1nnsgbc0xn9fYkcoklQdsW1xNa7XtasIm5TzuFnRkqIwHR0ICoSCkcg tKVqffwGmd+0TBv8kn//AeSTbq3Qd9DRDSy9z04Rcfp7aY8NEquqslsjiwb2aUE3UzXdLK XDUeLOcX/ey4UmXdQIflYfYSdIcuWs8= X-MC-Unique: m9krQ7SrO4-zk2sh9HUW9Q-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 5/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Date: Thu, 2 Jul 2020 17:26:55 +0200 Message-Id: <20200702152659.8522-6-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - fix 2 indents and typdef - added Peter's R-b --- include/hw/arm/smmu-common.h | 12 +++++++++--- hw/arm/smmu-common.c | 32 +++++++++++++++++--------------- hw/arm/smmuv3.c | 10 +++++----- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 455d7855b2..0db4403e94 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -52,6 +52,12 @@ typedef struct SMMUTransTableInfo { uint8_t granule_sz; /* granule page shift */ } SMMUTransTableInfo; =20 +typedef struct SMMUTLBEntry { + IOMMUTLBEntry entry; + uint8_t level; + uint8_t granule; +} SMMUTLBEntry; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as @@ -137,7 +143,7 @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) * pair, according to @cfg translation config */ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); =20 /** * select_tt - compute which translation table shall be used according to @@ -150,8 +156,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t= sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr = iova); -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 5e85e30bdf..a3301e56e7 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -47,11 +47,11 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t= iova) return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; } =20 -IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - hwaddr iova) +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + hwaddr iova) { SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); - IOMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); =20 if (entry) { cfg->iotlb_hits++; @@ -69,7 +69,7 @@ IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTrans= Cfg *cfg, return entry; } =20 -void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *en= try) +void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); =20 @@ -77,9 +77,9 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, = IOMMUTLBEntry *entry) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, entry->iova); - trace_smmu_iotlb_insert(cfg->asid, entry->iova); - g_hash_table_insert(bs->iotlb, key, entry); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + g_hash_table_insert(bs->iotlb, key, new); } =20 inline void smmu_iotlb_inv_all(SMMUState *s) @@ -199,7 +199,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * @cfg: translation config * @iova: iova to translate * @perm: access type - * @tlbe: IOMMUTLBEntry (out) + * @tlbe: SMMUTLBEntry (out) * @info: handle to an error info * * Return 0 on success, < 0 on error. In case of error, @info is filled @@ -209,7 +209,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) */ static int smmu_ptw_64(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -229,8 +229,8 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->iova =3D iova; - tlbe->addr_mask =3D (1 << granule_sz) - 1; + tlbe->entry.iova =3D iova; + tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; =20 while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); @@ -281,14 +281,16 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->translated_addr =3D gpa + (iova & mask); - tlbe->perm =3D PTE_AP_TO_PERM(ap); + tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); + tlbe->level =3D level; + tlbe->granule =3D granule_sz; return 0; } info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: - tlbe->perm =3D IOMMU_NONE; + tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } =20 @@ -304,7 +306,7 @@ error: * return 0 on success */ inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags p= erm, - IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { if (!cfg->aa64) { /* diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cd2a2e7e14..db74d27add 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -626,7 +626,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, SMMUTranslationStatus status; SMMUState *bs =3D ARM_SMMU(s); uint64_t page_mask, aligned_addr; - IOMMUTLBEntry *cached_entry =3D NULL; + SMMUTLBEntry *cached_entry =3D NULL; SMMUTransTableInfo *tt; SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { @@ -676,7 +676,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, =20 cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); if (cached_entry) { - if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) { + if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; if (event.record_trans_faults) { event.type =3D SMMU_EVT_F_PERMISSION; @@ -689,7 +689,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, goto epilogue; } =20 - cached_entry =3D g_new0(IOMMUTLBEntry, 1); + cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { g_free(cached_entry); @@ -743,9 +743,9 @@ epilogue: switch (status) { case SMMU_TRANS_SUCCESS: entry.perm =3D flag; - entry.translated_addr =3D cached_entry->translated_addr + + entry.translated_addr =3D cached_entry->entry.translated_addr + (addr & page_mask); - entry.addr_mask =3D cached_entry->addr_mask; + entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); break; --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=NUydCa7fctjP7th4rUdELWWUxIDOm37IGdKZttAnbB8=; b=dQrjsgfspMZI88Z+e6DGEcb2riDNWipBJ1fOSKYu3OZCort00eAI+GZcXHUlqNg4LWJkP/ uYmeqKTzwRK1yTQKP0VtM8DmvdW7yLbOagbEaNZUJ+4MCSBoPtVdcWpaYxBnKH34WBRpi/ 47G47dq2GylpZiKmEjOvcDnU9nOMgjU= X-MC-Unique: etfQ6FK0MaWgtFyW7ckfQQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 6/9] hw/arm/smmu-common: Manage IOTLB block entries Date: Thu, 2 Jul 2020 17:26:56 +0200 Message-Id: <20200702152659.8522-7-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consumes IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or page start address and size). Also the level/tg of the entry is encoded in the key. In subsequent patches we will enable range invalidation. This latter is able to provide the level/tg of the entry. Encoding the level/tg directly in the key will allow to invalidate using g_hash_table_remove() when num_pages equals to 1. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - recompute starting_level --- hw/arm/smmu-internal.h | 9 ++++++ include/hw/arm/smmu-common.h | 8 +++-- hw/arm/smmu-common.c | 63 ++++++++++++++++++++++++++++-------- hw/arm/smmuv3.c | 6 ++-- hw/arm/trace-events | 2 +- 5 files changed, 67 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 2ecb6f1dc6..d57f5c05c2 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -97,7 +97,16 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, } =20 #define SMMU_IOTLB_ASID_SHIFT 40 +#define SMMU_IOTLB_LEVEL_SHIFT 56 +#define SMMU_IOTLB_TG_SHIFT 58 =20 #define SMMU_IOTLB_ASID(key) (((key) >> SMMU_IOTLB_ASID_SHIFT) & 0xFFFF) #define SMMU_IOTLB_IOVA(key) (((key) & MAKE_64BIT_MASK(0, 40)) << 12) + +typedef struct SMMUIOTLBPageInvInfo { + int asid; + uint64_t iova; + uint64_t mask; +} SMMUIOTLBPageInvInfo; + #endif diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 0db4403e94..cc228b51b4 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -156,12 +156,14 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 =20 -SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr i= ova); +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, + SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova); +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index a3301e56e7..5c14127a24 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -42,16 +42,35 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, = gconstpointer v2) return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); } =20 -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova) +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, + uint8_t tg, uint8_t level) { - return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT; + return iova >> 12 | (uint64_t)(asid) << SMMU_IOTLB_ASID_SHIFT | + (uint64_t)(level) << SMMU_IOTLB_LEVEL_SHIFT | + (uint64_t)(tg) << SMMU_IOTLB_TG_SHIFT; } =20 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, - hwaddr iova) + SMMUTransTableInfo *tt, hwaddr iova) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(cfg->asid, iova); - SMMUTLBEntry *entry =3D g_hash_table_lookup(bs->iotlb, &key); + uint8_t tg =3D (tt->granule_sz - 10) / 2; + uint8_t inputsize =3D 64 - tt->tsz; + uint8_t stride =3D tt->granule_sz - 3; + uint8_t level =3D 4 - (inputsize - 4) / stride; + SMMUTLBEntry *entry =3D NULL; + + while (level <=3D 3) { + uint64_t subpage_size =3D 1ULL << level_shift(level, tt->granule_s= z); + uint64_t mask =3D subpage_size - 1; + SMMUIOTLBKey key; + + key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + entry =3D g_hash_table_lookup(bs->iotlb, &key); + if (entry) { + break; + } + level++; + } =20 if (entry) { cfg->iotlb_hits++; @@ -72,13 +91,14 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) { SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); + uint8_t tg =3D (new->granule - 10) / 2; =20 if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova); + *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); + trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -97,12 +117,28 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t io= va) +static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, + gpointer user_data) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova); + SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; + IOMMUTLBEntry *entry =3D &iter->entry; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; + uint64_t *iotlb_key =3D (uint64_t *)key; + + if (info->asid >=3D 0) { + return (info->asid =3D=3D SMMU_IOTLB_ASID(*iotlb_key)) && + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova); + } else { + return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + } +} + +inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +{ + SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; =20 trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_remove(s->iotlb, &key); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) @@ -229,9 +265,6 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - tlbe->entry.iova =3D iova; - tlbe->entry.addr_mask =3D (1 << granule_sz) - 1; - while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; @@ -281,7 +314,9 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, goto error; } =20 - tlbe->entry.translated_addr =3D gpa + (iova & mask); + tlbe->entry.translated_addr =3D gpa; + tlbe->entry.iova =3D iova & ~mask; + tlbe->entry.addr_mask =3D mask; tlbe->entry.perm =3D PTE_AP_TO_PERM(ap); tlbe->level =3D level; tlbe->granule =3D granule_sz; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index db74d27add..b717bde832 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -674,7 +674,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, page_mask =3D (1ULL << (tt->granule_sz)) - 1; aligned_addr =3D addr & ~page_mask; =20 - cached_entry =3D smmu_iotlb_lookup(bs, cfg, aligned_addr); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; @@ -744,7 +744,7 @@ epilogue: case SMMU_TRANS_SUCCESS: entry.perm =3D flag; entry.translated_addr =3D cached_entry->entry.translated_addr + - (addr & page_mask); + (addr & cached_entry->entry.addr_mask); entry.addr_mask =3D cached_entry->entry.addr_mask; trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, entry.translated_addr, entry.perm); @@ -972,7 +972,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_all(bs); + smmu_iotlb_inv_iova(bs, -1, addr); break; } case SMMU_CMD_TLBI_NH_VA: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index b808a1bfc1..f74d3e920f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -16,7 +16,7 @@ smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB = invalidate asid=3D%d addr smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=3D%d addr= =3D0x%"PRIx64 +smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=HN2Tg6cktWjfVh/Lr05cfnKD1TEiS0BORvWfwZryVgo=; b=cpqD+rhHOb6ksLZnHQjGuEFkBXN9PBTSpjx/Z6nVUjtesoil5Q08TdsBB4jj56V8ukHUCr HpVvMH5s2/vbtpcunKAUrhlQMwuTyd8G3pHWvaohxAYJWxq4B66/zt0d/eK0GHPdTKTIUs c9oxAZ7XIW+DP0WudDXc4mxxWApu+/U= X-MC-Unique: 3SCKL8uuPJu_nBRKr58w_Q-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Date: Thu, 2 Jul 2020 17:26:57 +0200 Message-Id: <20200702152659.8522-8-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a single IOVA invalidation. Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA command. At the moment it is only used for tracing. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - added comment about leaf bit and added Peter's R-b --- hw/arm/smmuv3.c | 36 +++++++++++++++++------------------- hw/arm/trace-events | 3 +-- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b717bde832..e4a2cea7ad 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -836,6 +836,22 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, in= t asid, dma_addr_t iova) } } =20 +static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +{ + dma_addr_t addr =3D CMD_ADDR(cmd); + uint8_t type =3D CMD_TYPE(cmd); + uint16_t vmid =3D CMD_VMID(cmd); + bool leaf =3D CMD_LEAF(cmd); + int asid =3D -1; + + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { + asid =3D CMD_ASID(cmd); + } + trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); + smmuv3_inv_notifiers_iova(s, asid, addr); + smmu_iotlb_inv_iova(s, asid, addr); +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -966,27 +982,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) smmu_iotlb_inv_all(bs); break; case SMMU_CMD_TLBI_NH_VAA: - { - dma_addr_t addr =3D CMD_ADDR(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); - smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_iova(bs, -1, addr); - break; - } case SMMU_CMD_TLBI_NH_VA: - { - uint16_t asid =3D CMD_ASID(&cmd); - uint16_t vmid =3D CMD_VMID(&cmd); - dma_addr_t addr =3D CMD_ADDR(&cmd); - bool leaf =3D CMD_LEAF(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(bs, asid, addr); - smmu_iotlb_inv_iova(bs, asid, addr); + smmuv3_s1_range_inval(bs, &cmd); break; - } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f74d3e920f..c219fe9e82 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,8 +45,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0= x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid= =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" -smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"PR= Ix64 +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=QxoFW6hoZksDABSpmYqYrKiiIan582I8JtfglTl03eI=; b=L9tEKTUw4wZ2J2019brbzqnrl8g9GSZUWyWi89D0QzYygnzI2c9zCb5oDRsVW+TPr7pInL sqBetmuGKHGvEiPhyLAezWi2h4QBkQDaEftrfoREVgfi7RD+eNTrVcPb4uxbug1d/2X5QR 9bMLLm0QtrxZ5fqRsDiElo3/PP57yvg= X-MC-Unique: Ijy_va28O9CYCORRwxcXZQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 8/9] hw/arm/smmuv3: Get prepared for range invalidation Date: Thu, 2 Jul 2020 17:26:58 +0200 Message-Id: <20200702152659.8522-9-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger --- hw/arm/smmuv3-internal.h | 4 +++ include/hw/arm/smmu-common.h | 3 +- hw/arm/smmu-common.c | 28 ++++++++++++---- hw/arm/smmuv3.c | 64 +++++++++++++++++++++++------------- hw/arm/trace-events | 4 +-- 5 files changed, 71 insertions(+), 32 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 4112394129..5babf72f7d 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -298,6 +298,8 @@ enum { /* Command completion notification */ }; =20 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) +#define CMD_NUM(x) extract32((x)->word[0], 12 , 5) +#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) #define CMD_SSV(x) extract32((x)->word[0], 11, 1) #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) @@ -310,6 +312,8 @@ enum { /* Command completion notification */ #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16) #define CMD_RESP(x) extract32((x)->word[2], 11, 2) #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1) +#define CMD_TTL(x) extract32((x)->word[2], 8 , 2) +#define CMD_TG(x) extract32((x)->word[2], 10, 2) #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5) #define CMD_ADDR(x) ({ \ uint64_t high =3D (uint64_t)(x)->word[3]; \ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index cc228b51b4..82bd9a4e8c 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -163,7 +163,8 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t= iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova); +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 5c14127a24..198ed6a928 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -127,18 +127,34 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, =20 if (info->asid >=3D 0) { return (info->asid =3D=3D SMMU_IOTLB_ASID(*iotlb_key)) && - ((info->iova & ~entry->addr_mask) =3D=3D entry->iova); + (((entry->iova & ~info->mask) =3D=3D info->iova) || + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova)); } else { - return (info->iova & ~entry->addr_mask) =3D=3D entry->iova; + return (((entry->iova & ~info->mask) =3D=3D info->iova) || + ((info->iova & ~entry->addr_mask) =3D=3D entry->iova)); } } =20 -inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova) +inline void +smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl) { - SMMUIOTLBPageInvInfo info =3D {.asid =3D asid, .iova =3D iova}; + if (ttl && (num_pages =3D=3D 1)) { + uint64_t key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 - trace_smmu_iotlb_inv_iova(asid, iova); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &= info); + g_hash_table_remove(s->iotlb, &key); + } else { + /* if tg is not set we use 4KB range invalidation */ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + + SMMUIOTLBPageInvInfo info =3D { + .asid =3D asid, .iova =3D iova, + .mask =3D (num_pages * 1 << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_asid_iova, + &info); + } } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e4a2cea7ad..89ab11fc36 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -785,42 +785,49 @@ epilogue: * @n: notifier to be called * @asid: address space ID or negative value if we don't care * @iova: iova + * @tg: translation granule (if communicated through range invalidation) + * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, - dma_addr_t iova) + int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; - SMMUTransTableInfo *tt; - SMMUTransCfg *cfg; IOMMUTLBEntry entry; + uint8_t granule =3D tg; =20 - cfg =3D smmuv3_get_config(sdev, &event); - if (!cfg) { - return; - } + if (!tg) { + SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; + SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &event); + SMMUTransTableInfo *tt; =20 - if (asid >=3D 0 && cfg->asid !=3D asid) { - return; - } + if (!cfg) { + return; + } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { - return; + if (asid >=3D 0 && cfg->asid !=3D asid) { + return; + } + + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; } =20 entry.target_as =3D &address_space_memory; entry.iova =3D iova; - entry.addr_mask =3D (1 << tt->granule_sz) - 1; + entry.addr_mask =3D num_pages * (1 << granule) - 1; entry.perm =3D IOMMU_NONE; =20 memory_region_notify_one(n, &entry); } =20 -/* invalidate an asid/iova tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova) +/* invalidate an asid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, + uint8_t tg, uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -828,28 +835,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova) IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, + tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova); + smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); } } } =20 static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) { + uint8_t scale =3D 0, num =3D 0, ttl =3D 0; dma_addr_t addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); uint16_t vmid =3D CMD_VMID(cmd); bool leaf =3D CMD_LEAF(cmd); + uint8_t tg =3D CMD_TG(cmd); + hwaddr num_pages =3D 1; int asid =3D -1; =20 + if (tg) { + scale =3D CMD_SCALE(cmd); + num =3D CMD_NUM(cmd); + ttl =3D CMD_TTL(cmd); + num_pages =3D (num + 1) * (1 << (scale)); + } + if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); } - trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr); - smmu_iotlb_inv_iova(s, asid, addr); + trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf= ); + smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); } =20 static int smmuv3_cmdq_consume(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c219fe9e82..3d905e0f7d 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start= =3D0x%d - end=3D0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid = =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid =3D%d asid =3D%d addr=3D0x%"PR= Ix64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) = "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.21.3 From nobody Mon May 6 06:11:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=m7UIwO4hcxYoI/BNBT1BncFKmWj1KcoaB4NX7cSnyRc=; b=ddD1NaN628plmLFXmraZSU0oWdbqeKkw4Htn3BpNVuCXlG1TOuzlw8M2/G+bGkgpalntbS lWYN1QNr6cbW5ul4jn1nKmHKhNVChbnLhnOOL/LSsUJPevLB9pluZJlifW/FZ7cg8tYLuz MlsYHg/KIfXfLPAz8NNFQ8mQG3kKwHw= X-MC-Unique: xdqQv_LSPe6zuiwI4pkzLg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation Date: Thu, 2 Jul 2020 17:26:59 +0200 Message-Id: <20200702152659.8522-10-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Expose the RIL bit so that the guest driver uses range invalidation. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 5babf72f7d..4e7ec252ed 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -54,6 +54,7 @@ REG32(IDR1, 0x4) =20 REG32(IDR2, 0x8) REG32(IDR3, 0xc) + FIELD(IDR3, RIL, 10, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 89ab11fc36..add4ba4543 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); + /* 4K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); --=20 2.21.3