From nobody Sun May 5 12:18:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1593628875; cv=none; d=zohomail.com; s=zohoarc; b=RYnLeky3T8Kgg21YfuZezA6otqUj3DnptBCbhCrJJLv/N2S2LCbs0MqZ5MqvcddyjJGOEqxBKzVOMIUnktH1dlbTuWWJ9gqCzRadbji05EaVNhjQCNoid4SgoW7On77Z3PBjnyVsbwnC/ju0R5lIbYBbVUIy0Ytws+mlvB68qgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593628875; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0v9dIvbsan8ehv2IVegUzINCfQXgs1/KZZqvxZfRkjw=; b=KINhOqfsJR/29s9jlpSQJaFYwyP5WccGg2KJ2KRMU/4+92H9+qfHbBnMgx/oUwAORfO9q9tSutxUTB79onMJhXOSkeragqPCIIrkK7EbbsXwXJpY96i6vDPQk4Zlao2aT8oxwRRTkHQN+vmTztvsSZobMix0EcrR0C5lNefo29w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593628875852157.54362596330236; Wed, 1 Jul 2020 11:41:15 -0700 (PDT) Received: from localhost ([::1]:59148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqhfW-0002gH-EJ for importer@patchew.org; Wed, 01 Jul 2020 14:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheM-0000zk-Ps; Wed, 01 Jul 2020 14:40:02 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:13131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheJ-0006SU-KX; Wed, 01 Jul 2020 14:40:02 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 02 Jul 2020 02:39:53 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2020 11:28:10 -0700 Received: from cnf006900.ad.shared (HELO yoda.hgst.com) ([10.86.58.95]) by uls-op-cesaip02.wdc.com with ESMTP; 01 Jul 2020 11:39:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1593628799; x=1625164799; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WeVV+ECuPk5S81Hthax5qKFbwjjza9mjQLe8acb8+KE=; b=BPov/QnlNQabUhLzsSjWW6DAMmS2o6yKzl4Izpj2AwXrI4M3P/qC/8og LvIdN2wm3o0EHV7RGxjNfXy2Sh2bDKDhYmI8hBmCcxqutRDKKkfvkIYuK 0lK2cIW33XNwu3ijRuPzV1uKDLZZ7aSHOWnuh39kvaVqEmRo83NtO86ax dpVQ6ALG87yeUH+Hwvabl6/lmExwnsU4lj9Q6pExo9A8XN3snkk+n6div blHFC1Y/8i2d2DSqGgbvexN45Oza0Yx99iiY2A7enfQBjm5H2v0OOukMw e6EHPC/ZvKKC81QdYoa4X3sQDLRi0ZmWi/9MnDNYYeJZBFVhGAGdOj2rK g==; IronPort-SDR: S/SLPMvhTLUxEGPdY/V/7H0cAzgbDSMp9k+W+IOj1xdraezDrUu0IArbl2QJurEBhz2AStmSmO 4nMXLjgal8/OMh8Epv3D0qTUoECetWgtNWlDfSeR+b5tRQTozI7XapTTOURaq+Sl7MSD4/OUoH X/MHTVRCgoX42Uy3q8OTCV4kLMLMLJ90hqs7fA2gs2uXeo2GBF8YJ98Dy/wmCEBMxYbpL7KSG2 ocwCiL9rHEv+VGFmodwaI2LR6vmjCr3u06bOrOZ8vfBQNky3ptJQIvwt9Foz1s2ZIdfKtVb0zh 238= X-IronPort-AV: E=Sophos;i="5.75,301,1589212800"; d="scan'208";a="250642368" IronPort-SDR: g/tvrr31HB5MKjZleoxyWNrzSaotj3e6gkDIkQ7YsaK3uFTuSJO9nWIYjNSKKBZbQtVnqoAkHe oYQj6B8QBmxVMrcIY5k0V6UYmz4aLDLpA= IronPort-SDR: 6ImAleFFqP7dq9OJfXgEkqJEj6XVutTnFD+NgPi8EaaP7nSsIMHgsYCvTuD9APbEzqbzkee8x0 ciYGCo0W4GFQ== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 1/4] riscv: Unify Qemu's reset vector code path Date: Wed, 1 Jul 2020 11:39:46 -0700 Message-Id: <20200701183949.398134-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200701183949.398134-1-atish.patra@wdc.com> References: <20200701183949.398134-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4447ca4a2=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/01 14:39:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Bin Meng , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently, all riscv machines except sifive_u have identical reset vector code implementations with memory addresses being different for all machines. They can be easily combined into a single function in common code. Move it to common function and let all the machines use the common function. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/boot.c | 46 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/sifive_u.c | 1 - hw/riscv/spike.c | 41 +++--------------------------------- hw/riscv/virt.c | 40 +++-------------------------------- include/hw/riscv/boot.h | 2 ++ 5 files changed, 54 insertions(+), 76 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index adb421b91b68..3df802380a36 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -26,8 +26,11 @@ #include "hw/loader.h" #include "hw/riscv/boot.h" #include "elf.h" +#include "sysemu/device_tree.h" #include "sysemu/qtest.h" =20 +#include + #if defined(TARGET_RISCV32) # define KERNEL_BOOT_ADDRESS 0x80400000 #else @@ -155,3 +158,46 @@ hwaddr riscv_load_initrd(const char *filename, uint64_= t mem_size, =20 return *start + size; } + +void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, + hwaddr rom_size, void *fdt) +{ + int i; + + /* reset vector */ + uint32_t reset_vec[8] =3D { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + start_addr, /* start: .dword */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector in little_endian byte order */ + for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] =3D cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + rom_base, &address_space_memory); + + /* copy in the device tree */ + if (fdt_pack(fdt) || fdt_totalsize(fdt) > + rom_size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); + rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt), + rom_base + sizeof(reset_vec), + &address_space_memory); + + return; +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7d051e7c9299..395b21703ab4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -56,7 +56,6 @@ #include "sysemu/device_tree.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" =20 #include =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3c87e04fdceb..c696077cbc16 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -41,9 +41,6 @@ #include "sysemu/device_tree.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" - -#include =20 #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" @@ -165,7 +162,6 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 /* Initialize SOC */ @@ -212,40 +208,9 @@ static void spike_board_init(MachineState *machine) } } =20 - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SPIKE_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SPIKE_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SPIKE_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, + memmap[SPIKE_MROM].size, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 616db6f5aced..8ec77e43de26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,12 +39,9 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" =20 -#include - #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin" #else @@ -535,40 +532,9 @@ static void virt_machine_init(MachineState *machine) start_addr =3D virt_memmap[VIRT_FLASH].base; } =20 - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - start_addr, /* start: .dword */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[VIRT_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[VIRT_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[VIRT_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, + virt_memmap[VIRT_MROM].size, s->fdt); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 9daa98da08d7..3e9759c89aa2 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filenam= e, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); +void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, + hwaddr rom_size, void *fdt); =20 #endif /* RISCV_BOOT_H */ --=20 2.26.2 From nobody Sun May 5 12:18:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1593628950; cv=none; d=zohomail.com; s=zohoarc; b=OGUKjnFaVFiyo/O1q24rLufaJb2G88B7EbuOrqSdkIyekNeSCzX6pJjiGzP8iFxtkdvfXXku3dDn2BZcUuAK8D7PaQ14KrgxDIya9jYOzPKamZ2RgB8ZJXe3IYta0XuFzUTBIOef3Qnck4rQJmIWFPF2XQaOk524/pnQBiYA7k4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593628950; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3rENzOUrE1fmCArSZahRFiPrWoA5okXqLUPa7lSb63U=; b=AVmd0KrzJiZIDzfy562Q0ZgMiNnFFG6GEP5KaR8SjSh/47ZYlme14NtVNLkSmLHQpaYDJKLARntnkiuoraZAZkO4w+/7n8aYJo/kElFLnw19isZ0mUj/k0doqo3BYyn0hfKMx4Q37mXCLmRXA7TxVH9UOeuTbpafHY4g+c9R/Ts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593628950292825.9622350035153; Wed, 1 Jul 2020 11:42:30 -0700 (PDT) Received: from localhost ([::1]:36604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqhgj-0004xm-10 for importer@patchew.org; Wed, 01 Jul 2020 14:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheQ-000143-Og; Wed, 01 Jul 2020 14:40:06 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:13131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheN-0006SU-A5; Wed, 01 Jul 2020 14:40:06 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 02 Jul 2020 02:39:54 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2020 11:28:11 -0700 Received: from cnf006900.ad.shared (HELO yoda.hgst.com) ([10.86.58.95]) by uls-op-cesaip02.wdc.com with ESMTP; 01 Jul 2020 11:39:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1593628803; x=1625164803; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3Zf/h0iJMxOuCa9lL9ARuWO8J3Sh8b0yE0djnI+dK8g=; b=oCGEKfzVPeu8aSVYrJe966mFftZq/RWbu6Pe2lx3Azt/HlgfUIFD3dp5 F6T6zzh1WtNPZublz9u46G9XBOxiGi8vRiHMLmg9c+F2N53182eivvb9n q6jZedr1BRVF4lxizTyVzByVGvYevDzqkJLMq2VYMEtyBwqyLI6UfdE9s D9QhrmYXlg5d2NQ17/9x2ZmBE8ktgGEgD0C1xNLbtfgPQmqebSJ0mRNzA nw1KmHyJtBKAHJUXA52h/J1jRhXhQ0pBu9I0v9ObMzkkMcBjT8CMAJHTA 29bJ0Zbz7MK+aKfPN5Ss3uPC7CPNSEKN/6rXUnFZD2t7NQ8mAldcAIcYJ w==; IronPort-SDR: N3t9WSd0lYuu8v1I0xT6fj4n58WF845ipA3rgoF5RUr11+FuXnygZe13BT8Iw7/AIKvcXsWyj0 /7xt/+9R/WHWujjNQsS/vGcVdLObMY8DokNDRGOgIq+QL9AjXvcFUvi8VVGetBcajLebp0zh5A uxnZXX0Pqfg+6LURZe5Acf9E50KdBASj7P6A0s1R0y8KeaKGNu2QOyz3koDaXarMHxYOX+ZN9h cmFokToZ8ikKQX2LejQ9AI+ONQob2YzHEj/wIyt7NDNB0x5vCr9hXSC5iN1nEOFpvgmIdDKTH8 y70= X-IronPort-AV: E=Sophos;i="5.75,301,1589212800"; d="scan'208";a="250642371" IronPort-SDR: jPygo1kAub3xh7evZAWAeHxGQF1dlNEk9sxNggUdQx5mvIdtZsDcgpJvTLdeXqKVDHl29Zr73W excv+JuQjXg8OylOO1xmYgcbhojLnY6q8= IronPort-SDR: whw3gcJgFugFzSkGShjHL3rpdQu4qP+Xov1SXNsNhu4NWUfOXDQ/oKx+cpPC2cnQcA98pE3uyn VqFdEDWDl37A== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 2/4] RISC-V: Copy the fdt in dram instead of ROM Date: Wed, 1 Jul 2020 11:39:47 -0700 Message-Id: <20200701183949.398134-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200701183949.398134-1-atish.patra@wdc.com> References: <20200701183949.398134-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4447ca4a2=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/01 14:39:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/boot.c | 53 +++++++++++++++++++++++++++++------------ hw/riscv/sifive_u.c | 28 ++++++++++------------ hw/riscv/spike.c | 7 +++++- hw/riscv/virt.c | 7 +++++- include/hw/riscv/boot.h | 4 +++- 5 files changed, 66 insertions(+), 33 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 3df802380a36..c62f545f15e7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -159,45 +159,68 @@ hwaddr riscv_load_initrd(const char *filename, uint64= _t mem_size, return *start + size; } =20 +uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +{ + uint32_t temp, fdt_addr; + hwaddr dram_end =3D dram_base + mem_size; + int fdtsize =3D fdt_totalsize(fdt); + + if (fdtsize <=3D 0) { + error_report("invalid device-tree"); + exit(1); + } + + /* + * We should put fdt as far as possible to avoid kernel/initrd overwri= ting + * its content. But it should be addressable by 32 bit system as well. + * Thus, put it at an aligned address that less than fdt size from end= of + * dram or 4GB whichever is lesser. + */ + temp =3D MIN(dram_end, 4096 * MiB); + fdt_addr =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + + fdt_pack(fdt); + /* copy in the device tree */ + qemu_fdt_dumpdtb(fdt, fdtsize); + + rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, + &address_space_memory); + + return fdt_addr; +} + void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, - hwaddr rom_size, void *fdt) + hwaddr rom_size, + uint32_t fdt_load_addr, void *fdt) { int i; =20 /* reset vector */ - uint32_t reset_vec[8] =3D { + uint32_t reset_vec[10] =3D { 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) + 0x0202a583, /* lw a1, 32(t0) */ 0x0182a283, /* lw t0, 24(t0) */ #elif defined(TARGET_RISCV64) + 0x0202b583, /* ld a1, 32(t0) */ 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ 0x00000000, start_addr, /* start: .dword */ + 0x00000000, + fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, /* dtb: */ }; =20 /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); =20 - /* copy in the device tree */ - if (fdt_pack(fdt) || fdt_totalsize(fdt) > - rom_size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); - rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt), - rom_base + sizeof(reset_vec), - &address_space_memory); - return; } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 395b21703ab4..aed814da9b94 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -379,6 +379,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; int i; + uint32_t fdt_load_addr; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -450,40 +451,37 @@ static void sifive_u_machine_init(MachineState *machi= ne) } } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, + machine->ram_size, s->fdt); + /* reset vector */ - uint32_t reset_vec[8] =3D { + uint32_t reset_vec[11] =3D { s->msel, /* MSEL pin state */ 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x01c28593, /* addi a1, t0, %pcrel_lo(1b)= */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) + 0x0202a583, /* lw a1, 32(t0) */ 0x0182a283, /* lw t0, 24(t0) */ #elif defined(TARGET_RISCV64) - 0x0182e283, /* lwu t0, 24(t0) */ + 0x0202b583, /* ld a1, 32(t0) */ + 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ 0x00000000, start_addr, /* start: .dword */ + 0x00000000, + fdt_load_addr, /* fdt_laddr: .dword */ + 0x00000000, /* dtb: */ }; =20 /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { + for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_MROM].base, &address_space_memor= y); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), - &address_space_memory); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c696077cbc16..5b04562dd106 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -163,6 +163,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); unsigned int smp_cpus =3D machine->smp.cpus; + uint32_t fdt_load_addr; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -208,9 +209,13 @@ static void spike_board_init(MachineState *machine) } } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[SPIKE_DRAM].base, + machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, - memmap[SPIKE_MROM].size, s->fdt); + memmap[SPIKE_MROM].size, + fdt_load_addr, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8ec77e43de26..3b3cc44912f4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -478,6 +478,7 @@ static void virt_machine_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; + uint32_t fdt_load_addr; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -532,9 +533,13 @@ static void virt_machine_init(MachineState *machine) start_addr =3D virt_memmap[VIRT_FLASH].base; } =20 + /* Compute the fdt load address in dram */ + fdt_load_addr =3D riscv_load_fdt(memmap[VIRT_DRAM].base, + machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, s->fdt); + virt_memmap[VIRT_MROM].size, + fdt_load_addr, s->fdt); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 3e9759c89aa2..35b6ddf710d7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -35,7 +35,9 @@ target_ulong riscv_load_kernel(const char *kernel_filenam= e, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); +uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, void *fdt); + hwaddr rom_size, + uint32_t fdt_load_addr, void *fdt); =20 #endif /* RISCV_BOOT_H */ --=20 2.26.2 From nobody Sun May 5 12:18:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1593628951; cv=none; d=zohomail.com; s=zohoarc; b=FaYPKw0PdclzDfKgswSZlLqishowKddBndZFHwWcVAPBpLt7UtrqQYACSsjbmHGyDjIsFculU/OTj65V63V/9/a7wQZ43klZgKiQEPZ24UPHUdFdQl8QYVEv3GBLl2jHRLEgH74q/U1Fx4yGfPIcicmhj25RaChO4yasHSO87eU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593628951; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QNNbbAYbsyq+OXhqycysb5r/n7QLG2KHfATPHsHnx0M=; b=Ds5UOJeeIv8Sp6aPr2r0DwwO9C6Zb9fKKqm6gwPN42Gqx+n/ruKLPizjLiPcqUOBODWHt5wNEL4YO91V7Bp8lfVvYglkhWggBkIu17EaniV6sgE9W5B9TokoPHAzlC611zyd57WIRZH+bu93BRkzFYw6rY0+BATzPBnj7oobNOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593628951552587.545366168427; Wed, 1 Jul 2020 11:42:31 -0700 (PDT) Received: from localhost ([::1]:36648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqhgk-0004yn-40 for importer@patchew.org; Wed, 01 Jul 2020 14:42:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheQ-00012V-0d; Wed, 01 Jul 2020 14:40:06 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:13124) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheN-0006Qb-Jz; Wed, 01 Jul 2020 14:40:05 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 02 Jul 2020 02:39:54 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2020 11:28:11 -0700 Received: from cnf006900.ad.shared (HELO yoda.hgst.com) ([10.86.58.95]) by uls-op-cesaip02.wdc.com with ESMTP; 01 Jul 2020 11:39:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1593628803; x=1625164803; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BvWBvty4qCBpcREE0bbUuxJD53acSp3ctXnMrDTq4Ts=; b=QDYqAUeOriU/PrRRmPynrn7LVIQzFLGoRUkHRoTr5Bnx/Bph+eoirzzZ H4SBh7bLHdhns3q05xR+fY1ihaJJLgigAHPA1pFfY3EXDAP4A9mnmsD2E 44VNmF33oAUf4TseBnSxH+njdxu5gHtdUof/LIlCxmuXfSKAQFifjxLM+ 0SbJgjuM3V/m0zRxKEnumDCB2onmWy0BbC5qEHCPfn1oTrVEtMUI64kXW 8qSSnreZ6L7uHSUxYKIBbMQ4sy068MBPZymNExnYh6tMJcActHL9SWNYt v6bwIxN17jZez5yJd+mZRQKXiPDESPRZcCoAWYfCwARWWuvxnuNJLERVz Q==; IronPort-SDR: 7LRbu3RSuCvqLUDXgD21L0pcKbcyc7OuVz3LRzQSkQyTQi5xBDuI6/aEhXEvLt5PqxEuMD5HpJ xJVn67p7yi2tUkJefnhpWeUETrxgA8Kb5WVNlPbika4YF9/SXsBBY6h/2G7LaV1hto3a3lL+sE Fzat6KQ65TOivVwnH/OSx5Qn9lo3sLVOxW+qB0iEhzPYx4Bfj8WXI0NdYJMM42rF8C5kD+ad4q 0KigFSlaryXbSWJoHd4/HcqB0JWpeNb5EmX+8Myb3v/OXdyUakiJz7sVdQLUmnutkAZ+H4TFQk K8s= X-IronPort-AV: E=Sophos;i="5.75,301,1589212800"; d="scan'208";a="250642375" IronPort-SDR: jjnOKh6XZPCWmFSsLrR7mvk1z2n4jxE9bZVRaRqPwqvI5JE25L8eejYOfpMHQ6feZEDC9NwQEP k5RARxkUYQhNyLq9zZytHAdT0qWhyfS50= IronPort-SDR: 6qIJKJET4wN0F6FtFwDmXUdyiF+tPpCx2X2IwfhNe8xVfBECMiYoyME6JfQW6oXc0tkP6K6FRp i/MmAp24fnNw== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 3/4] riscv: Add opensbi firmware dynamic support Date: Wed, 1 Jul 2020 11:39:48 -0700 Message-Id: <20200701183949.398134-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200701183949.398134-1-atish.patra@wdc.com> References: <20200701183949.398134-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4447ca4a2=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/01 14:39:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" OpenSBI is the default firmware in Qemu and has various firmware loading options. Currently, qemu loader uses fw_jump which has a compile time pre-defined address where fdt & kernel image must reside. This puts a constraint on image size of the Linux kernel depending on the fdt location and available memory. However, fw_dynamic allows the loader to specify the next stage location (i.e. Linux kernel/U-Boot) in memory and other configurable boot options available in OpenSBI. Add support for OpenSBI dynamic firmware loading support. This doesn't break existing setup and fw_jump will continue to work as it is. Any other firmware will continue to work without any issues as long as it doesn't expect anything specific from loader in "a2" register. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/boot.c | 42 +++++++++++++++++++++--- hw/riscv/sifive_u.c | 20 +++++++++--- hw/riscv/spike.c | 13 ++++++-- hw/riscv/virt.c | 12 +++++-- include/hw/riscv/boot.h | 5 ++- include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++++++++++++++++++ 6 files changed, 134 insertions(+), 16 deletions(-) create mode 100644 include/hw/riscv/boot_opensbi.h diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c62f545f15e7..feff6e3f4ed5 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/riscv/boot.h" +#include "hw/riscv/boot_opensbi.h" #include "elf.h" #include "sysemu/device_tree.h" #include "sysemu/qtest.h" @@ -33,8 +34,10 @@ =20 #if defined(TARGET_RISCV32) # define KERNEL_BOOT_ADDRESS 0x80400000 +#define fw_dynamic_info_data(__val) cpu_to_le32(__val) #else # define KERNEL_BOOT_ADDRESS 0x80200000 +#define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif =20 void riscv_find_and_load_firmware(MachineState *machine, @@ -189,15 +192,45 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t me= m_size, void *fdt) return fdt_addr; } =20 +void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, uint64_t kernel_ent= ry) +{ + struct fw_dynamic_info dinfo; + size_t dinfo_len; + + dinfo.magic =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo.version =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); + dinfo.next_mode =3D fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo.next_addr =3D fw_dynamic_info_data(kernel_entry); + dinfo.options =3D 0; + dinfo.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo); + + /** + * copy the dynamic firmware info. This information is specific to + * OpenSBI but doesn't break any other firmware as long as they don't + * expect any certain value in "a2" register. + */ + if (dinfo_len > (rom_size - reset_vec_size)) { + error_report("not enough space to store dynamic firmware info"); + exit(1); + } + + rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, + rom_base + reset_vec_size, + &address_space_memory); +} + void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, - hwaddr rom_size, + hwaddr rom_size, uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt) { int i; =20 /* reset vector */ uint32_t reset_vec[10] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ + 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) 0x0202a583, /* lw a1, 32(t0) */ @@ -207,12 +240,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwa= ddr rom_base, 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ - 0x00000000, start_addr, /* start: .dword */ 0x00000000, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, - /* dtb: */ + /* fw_dyn: */ }; =20 /* copy in the reset vector in little_endian byte order */ @@ -221,6 +253,8 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwadd= r rom_base, } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); + riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), + kernel_entry); =20 return; } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index aed814da9b94..901efab9d5bd 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -380,6 +380,7 @@ static void sifive_u_machine_init(MachineState *machine) target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; int i; uint32_t fdt_load_addr; + uint64_t kernel_entry; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -436,8 +437,7 @@ static void sifive_u_machine_init(MachineState *machine) riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, - NULL); + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); =20 if (machine->initrd_filename) { hwaddr start; @@ -449,6 +449,12 @@ static void sifive_u_machine_init(MachineState *machin= e) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 /* Compute the fdt load address in dram */ @@ -458,7 +464,8 @@ static void sifive_u_machine_init(MachineState *machine) /* reset vector */ uint32_t reset_vec[11] =3D { s->msel, /* MSEL pin state */ - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn)= */ + 0x02828613, /* addi a2, t0, %pcrel_lo(1b)= */ 0xf1402573, /* csrr a0, mhartid */ #if defined(TARGET_RISCV32) 0x0202a583, /* lw a1, 32(t0) */ @@ -468,12 +475,11 @@ static void sifive_u_machine_init(MachineState *machi= ne) 0x0182b283, /* ld t0, 24(t0) */ #endif 0x00028067, /* jr t0 */ - 0x00000000, start_addr, /* start: .dword */ 0x00000000, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, - /* dtb: */ + /* fw_dyn: */ }; =20 /* copy in the reset vector in little_endian byte order */ @@ -482,6 +488,10 @@ static void sifive_u_machine_init(MachineState *machin= e) } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_MROM].base, &address_space_memor= y); + + riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base, + memmap[SIFIVE_U_MROM].size, + sizeof(reset_vec), kernel_entry); } =20 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5b04562dd106..b295a4319775 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -164,6 +164,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); unsigned int smp_cpus =3D machine->smp.cpus; uint32_t fdt_load_addr; + uint64_t kernel_entry; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -194,8 +195,8 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, - htif_symbol_callback); + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, + htif_symbol_callback); =20 if (machine->initrd_filename) { hwaddr start; @@ -207,6 +208,12 @@ static void spike_board_init(MachineState *machine) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 /* Compute the fdt load address in dram */ @@ -214,7 +221,7 @@ static void spike_board_init(MachineState *machine) machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].= base, - memmap[SPIKE_MROM].size, + memmap[SPIKE_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3b3cc44912f4..85e17feaf84b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -479,6 +479,7 @@ static void virt_machine_init(MachineState *machine) size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; uint32_t fdt_load_addr; + uint64_t kernel_entry; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -510,8 +511,7 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_DRAM].base, NULL); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, - NULL); + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); =20 if (machine->initrd_filename) { hwaddr start; @@ -523,6 +523,12 @@ static void virt_machine_init(MachineState *machine) qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } + } else { + /* + * If dynamic firmware is used, it doesn't know where is the next m= ode + * if kernel argument is not set. + */ + kernel_entry =3D 0; } =20 if (drive_get(IF_PFLASH, 0, 0)) { @@ -538,7 +544,7 @@ static void virt_machine_init(MachineState *machine) machine->ram_size, s->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, + virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 35b6ddf710d7..451338780a45 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,7 +37,10 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t = mem_size, uint64_t kernel_entry, hwaddr *start); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, + hwaddr rom_size, uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt); +void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, + uint64_t kernel_entry); =20 #endif /* RISCV_BOOT_H */ diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h new file mode 100644 index 000000000000..0d5ddd6c3daf --- /dev/null +++ b/include/hw/riscv/boot_opensbi.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI proj= ect. + */ +#ifndef OPENSBI_H +#define OPENSBI_H + +/** Expected value of info magic ('OSBI' ascii string in hex) */ +#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f + +/** Maximum supported info version */ +#define FW_DYNAMIC_INFO_VERSION 0x2 + +/** Possible next mode values */ +#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0 +#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1 +#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3 + +enum sbi_scratch_options { + /** Disable prints during boot */ + SBI_SCRATCH_NO_BOOT_PRINTS =3D (1 << 0), + /** Enable runtime debug prints */ + SBI_SCRATCH_DEBUG_PRINTS =3D (1 << 1), +}; + +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info { + /** Info magic */ + target_long magic; + /** Info version */ + target_long version; + /** Next booting stage address */ + target_long next_addr; + /** Next booting stage mode */ + target_long next_mode; + /** Options for OpenSBI library */ + target_long options; + /** + * Preferred boot HART id + * + * It is possible that the previous booting stage uses same link + * address as the FW_DYNAMIC firmware. In this case, the relocation + * lottery mechanism can potentially overwrite the previous booting + * stage while other HARTs are still running in the previous booting + * stage leading to boot-time crash. To avoid this boot-time crash, + * the previous booting stage can specify last HART that will jump + * to the FW_DYNAMIC firmware as the preferred boot HART. + * + * To avoid specifying a preferred boot HART, the previous booting + * stage can set it to -1UL which will force the FW_DYNAMIC firmware + * to use the relocation lottery mechanism. + */ + target_long boot_hart; +}; + +#endif --=20 2.26.2 From nobody Sun May 5 12:18:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1593628881; cv=none; d=zohomail.com; s=zohoarc; b=O8yI45GB6Igad2yXFbvGVZ2vmFXMDUO8DCm+CmTgbOd8Xnfaz+q7dWmq3z+OMM/eIFTkTbH3EY6JKDDW2bsvfNQXwJNbh040RhsG6K5r8SuryrHh7m/h0n0dkvaMDXl/OOBzJsvK6+h4Typ8LYMSh3EJzyifu7C36MCf3kqlcBo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593628881; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MIuYTQUeQBS5K+52N4ss+U6M+WP6qzEWDzxTnQuE2XE=; b=D55wiRdQeTDizbH03h6zG95abLHDhT71vrCgGuPMgDTTVZpE5ejWbqpi2qwHBaRLNsyCdjaz/HU9xZmsQpMjamCP2ToWuPUyN2N2zXKZKV0reXcsa4xXsCoJfFsV1f1UjCOMXiV7oyKGXg87wwFs1lBxxFTs7J4n2J2prGfgxWM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593628881791591.4173733475967; Wed, 1 Jul 2020 11:41:21 -0700 (PDT) Received: from localhost ([::1]:59904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqhfc-0002yY-Ia for importer@patchew.org; Wed, 01 Jul 2020 14:41:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheS-00016c-1F; Wed, 01 Jul 2020 14:40:08 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:13143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqheN-0006V6-SH; Wed, 01 Jul 2020 14:40:07 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 02 Jul 2020 02:39:55 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2020 11:28:12 -0700 Received: from cnf006900.ad.shared (HELO yoda.hgst.com) ([10.86.58.95]) by uls-op-cesaip02.wdc.com with ESMTP; 01 Jul 2020 11:39:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1593628803; x=1625164803; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SFTnFlIICJQUz0ffsBvrvq+0Fk4gFQoQwkbeCbQrNg0=; b=iDd1tbAS7F6tmZtPk/NP7NnWOPZNBR4muJanp/bwuMD7WPyWpavud3hV y+p6zLSt3FegRws1YXRiNjwvfZ9U/gvCiM0eBJKvkG3zVTFoO5pFqcL80 gAHvKZY0daZmdq9HQKLMe0uboa/0KbP62VOp96ySOFX6h7CYt8Rc2sjJl 9rutt3qlhKXGoWwP9H5ysITkLGND7K1S6VhLT0wd1ZF0rqlFv4JsyPqr9 TbFcujfF5vPOAVn1jmUq+XpvwmuaN+/kimJtOfMHsIZ1PLq3oKA8v5H3x exBpkIPwVOqGeWwNBLl4WN74ePX3GDDoZ1cITChtToGcdIcYB7u35JvcK w==; IronPort-SDR: ZcDEmU1Ym0J7B7lUY/JokUDOsLOxawrFqQ22JsxZjS5FNbemCWvKu4lBD7dGo9EXxF0/7wI6et mj1F218PJGDhnkV6bJglE90nQ8TM7SRmSR4rha3iNHxxsJF1RRWvAu8p819t98XZvvtxkgv+vS rlSos0TLFl0yKEVpUcESbcLrjf3ELWat9jmEdK2xI9Hpg9IWfonbyu78WSiMe0MqyjP1h8A3It uY6L1U21Oag2tJ4gyZGn454WtFvXFukVA/llH2Kw92bDUxnxx0gibVb7JPTuQdIP+oSmD2fmLl NWE= X-IronPort-AV: E=Sophos;i="5.75,301,1589212800"; d="scan'208";a="250642378" IronPort-SDR: fraHkk0LluqpOjQlfmSYOcwsdFPHanE2/RtOF5IyVChHpf6zxh1KjLqW3E+q8oR+S1qPAm1ocF 0Q1FBivtlUwY6uFRdDm47Zbwj/zcDE1s8= IronPort-SDR: TTB9c+ZRifkn05sOBkIASo9Jbci22bYtbGasVUtEB9Kls+JrAMkYM3ch2P5TkU77sdcifqRS/g zsrqmyC/TS0Q== WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 4/4] RISC-V: Support 64 bit start address Date: Wed, 1 Jul 2020 11:39:49 -0700 Message-Id: <20200701183949.398134-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200701183949.398134-1-atish.patra@wdc.com> References: <20200701183949.398134-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4447ca4a2=atish.patra@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/01 14:39:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/boot.c | 6 +++++- hw/riscv/sifive_u.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index feff6e3f4ed5..4c6c101ff179 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwad= dr rom_base, uint32_t fdt_load_addr, void *fdt) { int i; + uint32_t start_addr_hi32 =3D 0x00000000; =20 + #if defined(TARGET_RISCV64) + start_addr_hi32 =3D start_addr >> 32; + #endif /* reset vector */ uint32_t reset_vec[10] =3D { 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ @@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwadd= r rom_base, #endif 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ - 0x00000000, + start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, /* fw_dyn: */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 901efab9d5bd..3aaee82f1f28 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; + uint32_t start_addr_hi32 =3D 0x00000000; int i; uint32_t fdt_load_addr; uint64_t kernel_entry; @@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, machine->ram_size, s->fdt); + #if defined(TARGET_RISCV64) + start_addr_hi32 =3D start_addr >> 32; + #endif =20 /* reset vector */ uint32_t reset_vec[11] =3D { @@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ - 0x00000000, + start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, /* fw_dyn: */ --=20 2.26.2