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bh=8c5rpM/uUzeAs95QmaeYXk7xK2+A8aAk2ZuVb9/UVi8=; b=PSdu4yY8WGJxYbdhAar85yGHjfuEq3NiPexARF45F97zBhV1KbG+cK+BXka0206gRxvGli aMJFs6ckuKFfUjPk8Ezc2olnTFv8zaCznLHNTj8lTJ0cNNT2JcKl7wcp0TX4fid6mxmuwy WyL/bTfX74BCysSnpTuHUzQV9nCIxR0= X-MC-Unique: 6oR8ddD8Ms26A-hh5GNbKQ-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Subject: [PULL 08/13] sm501: Convert debug printfs to traces Date: Wed, 1 Jul 2020 17:04:20 +0200 Message-Id: <20200701150425.13739-9-kraxel@redhat.com> In-Reply-To: <20200701150425.13739-1-kraxel@redhat.com> References: <20200701150425.13739-1-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.139.110.120; envelope-from=kraxel@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/30 22:25:53 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell Message-id: caf97bf0c84a440896ddf020e84c312fa5c15076.1592686588.git.balaton= @eik.bme.hu Signed-off-by: Gerd Hoffmann --- hw/display/sm501.c | 50 +++++++++++------------------------------ hw/display/trace-events | 12 ++++++++++ 2 files changed, 25 insertions(+), 37 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 7e4c042d5229..2db347dcbc1c 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -39,15 +39,7 @@ #include "qemu/range.h" #include "ui/pixel_ops.h" #include "qemu/bswap.h" - -/*#define DEBUG_SM501*/ -/*#define DEBUG_BITBLT*/ - -#ifdef DEBUG_SM501 -#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) -#else -#define SM501_DPRINTF(fmt, ...) do {} while (0) -#endif +#include "trace.h" =20 #define MMIO_BASE_OFFSET 0x3e00000 #define MMIO_SIZE 0x200000 @@ -871,7 +863,6 @@ static uint64_t sm501_system_config_read(void *opaque, = hwaddr addr, { SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; - SM501_DPRINTF("sm501 system config regs : read addr=3D%x\n", (int)addr= ); =20 switch (addr) { case SM501_SYSTEM_CONTROL: @@ -923,7 +914,7 @@ static uint64_t sm501_system_config_read(void *opaque, = hwaddr addr, qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" "register read. addr=3D%" HWADDR_PRIx "\n", addr); } - + trace_sm501_system_config_read(addr, ret); return ret; } =20 @@ -931,9 +922,8 @@ static void sm501_system_config_write(void *opaque, hwa= ddr addr, uint64_t value, unsigned size) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 system config regs : write addr=3D%x, val=3D%x\n", - (uint32_t)addr, (uint32_t)value); =20 + trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); switch (addr) { case SM501_SYSTEM_CONTROL: s->system_control &=3D 0x10DB0000; @@ -1019,9 +1009,7 @@ static uint64_t sm501_i2c_read(void *opaque, hwaddr a= ddr, unsigned size) qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register rea= d." " addr=3D0x%" HWADDR_PRIx "\n", addr); } - - SM501_DPRINTF("sm501 i2c regs : read addr=3D%" HWADDR_PRIx " val=3D%x\= n", - addr, ret); + trace_sm501_i2c_read((uint32_t)addr, ret); return ret; } =20 @@ -1029,9 +1017,8 @@ static void sm501_i2c_write(void *opaque, hwaddr addr= , uint64_t value, unsigned size) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 i2c regs : write addr=3D%" HWADDR_PRIx - " val=3D%" PRIx64 "\n", addr, value); =20 + trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); switch (addr) { case SM501_I2C_BYTE_COUNT: s->i2c_byte_count =3D value & 0xf; @@ -1045,25 +1032,19 @@ static void sm501_i2c_write(void *opaque, hwaddr ad= dr, uint64_t value, s->i2c_status |=3D (res ? SM501_I2C_STATUS_ERROR : 0); if (!res) { int i; - SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x= %x\n", - s->i2c_byte_count + 1, s->i2c_addr >> 1); for (i =3D 0; i <=3D s->i2c_byte_count; i++) { res =3D i2c_send_recv(s->i2c_bus, &s->i2c_data[i], !(s->i2c_addr & 1)); if (res) { - SM501_DPRINTF("sm501 i2c : transfer failed" - " i=3D%d, res=3D%d\n", i, res); s->i2c_status |=3D SM501_I2C_STATUS_ERROR; return; } } if (i) { - SM501_DPRINTF("sm501 i2c : transferred %d bytes\n"= , i); s->i2c_status =3D SM501_I2C_STATUS_COMPLETE; } } } else { - SM501_DPRINTF("sm501 i2c : end transfer\n"); i2c_end_transfer(s->i2c_bus); s->i2c_status &=3D ~SM501_I2C_STATUS_ERROR; } @@ -1103,7 +1084,8 @@ static const MemoryRegionOps sm501_i2c_ops =3D { static uint32_t sm501_palette_read(void *opaque, hwaddr addr) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 palette read addr=3D%x\n", (int)addr); + + trace_sm501_palette_read((uint32_t)addr); =20 /* TODO : consider BYTE/WORD access */ /* TODO : consider endian */ @@ -1116,8 +1098,8 @@ static void sm501_palette_write(void *opaque, hwaddr = addr, uint32_t value) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 palette write addr=3D%x, val=3D%x\n", - (int)addr, value); + + trace_sm501_palette_write((uint32_t)addr, value); =20 /* TODO : consider BYTE/WORD access */ /* TODO : consider endian */ @@ -1132,7 +1114,6 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hw= addr addr, { SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; - SM501_DPRINTF("sm501 disp ctrl regs : read addr=3D%x\n", (int)addr); =20 switch (addr) { =20 @@ -1237,7 +1218,7 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hw= addr addr, qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl registe= r " "read. addr=3D%" HWADDR_PRIx "\n", addr); } - + trace_sm501_disp_ctrl_read((uint32_t)addr, ret); return ret; } =20 @@ -1245,9 +1226,8 @@ static void sm501_disp_ctrl_write(void *opaque, hwadd= r addr, uint64_t value, unsigned size) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 disp ctrl regs : write addr=3D%x, val=3D%x\n", - (unsigned)addr, (unsigned)value); =20 + trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); switch (addr) { case SM501_DC_PANEL_CONTROL: s->dc_panel_control =3D value & 0x0FFF73FF; @@ -1392,7 +1372,6 @@ static uint64_t sm501_2d_engine_read(void *opaque, hw= addr addr, { SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; - SM501_DPRINTF("sm501 2d engine regs : read addr=3D%x\n", (int)addr); =20 switch (addr) { case SM501_2D_SOURCE: @@ -1462,7 +1441,7 @@ static uint64_t sm501_2d_engine_read(void *opaque, hw= addr addr, qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl registe= r " "read. addr=3D%" HWADDR_PRIx "\n", addr); } - + trace_sm501_2d_engine_read((uint32_t)addr, ret); return ret; } =20 @@ -1470,9 +1449,8 @@ static void sm501_2d_engine_write(void *opaque, hwadd= r addr, uint64_t value, unsigned size) { SM501State *s =3D (SM501State *)opaque; - SM501_DPRINTF("sm501 2d engine regs : write addr=3D%x, val=3D%x\n", - (unsigned)addr, (unsigned)value); =20 + trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); switch (addr) { case SM501_2D_SOURCE: s->twoD_source =3D value; @@ -1830,8 +1808,6 @@ static void sm501_init(SM501State *s, DeviceState *de= v, uint32_t local_mem_bytes) { s->local_mem_size_index =3D get_local_mem_size_index(local_mem_bytes); - SM501_DPRINTF("sm501 local mem size=3D%x. index=3D%d\n", get_local_mem= _size(s), - s->local_mem_size_index); =20 /* local memory */ memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local= ", diff --git a/hw/display/trace-events b/hw/display/trace-events index 72d4c9812c69..970d6bac5dcf 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -161,3 +161,15 @@ cg3_write(uint32_t addr, uint32_t val, unsigned size) = "write addr:0x%06"PRIx32" # dpcd.c dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x" dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x" + +# sm501.c +sm501_system_config_read(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D= 0x%x" +sm501_system_config_write(uint32_t addr, uint32_t val) "addr=3D0x%x, val= =3D0x%x" +sm501_i2c_read(uint32_t addr, uint8_t val) "addr=3D0x%x, val=3D0x%x" +sm501_i2c_write(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%x" +sm501_palette_read(uint32_t addr) "addr=3D0x%x" +sm501_palette_write(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%x" +sm501_disp_ctrl_read(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%x" +sm501_disp_ctrl_write(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%= x" +sm501_2d_engine_read(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%x" +sm501_2d_engine_write(uint32_t addr, uint32_t val) "addr=3D0x%x, val=3D0x%= x" --=20 2.18.4