From nobody Mon Apr 29 06:47:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1593601667; cv=none; d=zohomail.com; s=zohoarc; b=bxlTa+ktjHEUtIc+qzZWCz7HM69kTNfMuZCU5IzsPr7C1Ccse455FAzUo95iMXS+mqHWTKOi/4lYiBOTesPeTAFBL4llrG8fELnQTTnon04Sv2eZBOeW1eRP6cFuZxL2gxWVW5cw8VW5QLFKa6FG3s689t/wGtOgP1MEdS1tqPY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593601667; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=hTWsmCKFSg3Qd2DPA/2PmvzjBmwImUE44yRbKJHTGrA=; b=fH4W9VFzWPokRUbkTwzu1I8sLCr4dzz1xIfq5qKwOAqVYsGOw9z2X3IPV7UUhEiZEPz+b/MDNUGln+L+8M9e4/enzEfmq4AycwLxiLgF9MXJLyC8zih9cEca0ycz/7glgzyz+AiQcAw60eo8DdnMvQmucsc8kfF+tdTYiE2LJgc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15936016679071020.5278354389923; Wed, 1 Jul 2020 04:07:47 -0700 (PDT) Received: from localhost ([::1]:56592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqaag-00062D-Ke for importer@patchew.org; Wed, 01 Jul 2020 07:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqaZ6-0003xO-Qf for qemu-devel@nongnu.org; Wed, 01 Jul 2020 07:06:08 -0400 Received: from esa3.hc3370-68.iphmx.com ([216.71.145.155]:29827) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqaZ4-0004hH-4l for qemu-devel@nongnu.org; Wed, 01 Jul 2020 07:06:08 -0400 Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: O9QW0YFfOy/Q8znWGSQyuQdD4h7Q1vNcBI3M2+mjz9GEaC7kFJVVDmpxhYneOT9S47gxJiQleo PrCokCKxRoaWButroNqmg9QXKqtyRm2isR7CGli4k57BFDK6r2OYK/eCN3U0B3Xmd2p9RGuBzz P3NuV9pqLTiKNzacmENIeijRLdch6KFftsg/vd8hwvH8qRf+QfUk6TKDh9EAef0BKEUinOAVCO lgcn2sa6Uq7togA1Y5GT//NNLssbHDu30Rd4Bq4xdQX6RzDHsv9UMs7goO6RZ2OrnB3yE9ovUI t0A= X-SBRS: 2.7 X-MesageID: 21375916 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.75,300,1589256000"; d="scan'208";a="21375916" From: Anthony PERARD To: Subject: [PATCH] acpi: Fix access to PM1 control and status registers Date: Wed, 1 Jul 2020 12:05:49 +0100 Message-ID: <20200701110549.148522-1-anthony.perard@citrix.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.145.155; envelope-from=anthony.perard@citrix.com; helo=esa3.hc3370-68.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/01 07:06:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anthony PERARD , Igor Mammedov , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The ACPI spec state that "Accesses to PM1 control registers are accessed through byte and word accesses." (In section 4.7.3.2.1 PM1 Control Registers of my old spec copy rev 4.0a). With commit 5d971f9e6725 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""), it wasn't possible anymore to access the pm1_cnt register by reading a single byte, and that is use by at least a Xen firmware called "hvmloader". Also, take care of the PM1 Status Registers which also have "Accesses to the PM1 status registers are done through byte or word accesses" (In section 4.7.3.1.1 PM1 Status Registers). Signed-off-by: Anthony PERARD --- hw/acpi/core.c | 46 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 45cbed49abdd..31974e2f91bf 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -394,9 +394,17 @@ uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar) return ar->pm1.evt.sts; } =20 -static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) +static void acpi_pm1_evt_write_sts(ACPIREGS *ar, hwaddr addr, uint16_t val, + unsigned width) { uint16_t pm1_sts =3D acpi_pm1_evt_get_sts(ar); + if (width =3D=3D 1) { + if (addr =3D=3D 0) { + val |=3D pm1_sts & 0xff00; + } else if (addr =3D=3D 1) { + val =3D (val << BITS_PER_BYTE) | (pm1_sts & 0xff); + } + } if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) { /* if TMRSTS is reset, then compute the new overflow time */ acpi_pm_tmr_calc_overflow_time(ar); @@ -404,8 +412,16 @@ static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint1= 6_t val) ar->pm1.evt.sts &=3D ~val; } =20 -static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val) +static void acpi_pm1_evt_write_en(ACPIREGS *ar, hwaddr addr, uint16_t val, + unsigned width) { + if (width =3D=3D 1) { + if (addr =3D=3D 0) { + val |=3D ar->pm1.evt.en & 0xff00; + } else if (addr =3D=3D 1) { + val =3D (val << BITS_PER_BYTE) | (ar->pm1.evt.en & 0xff); + } + } ar->pm1.evt.en =3D val; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, val & ACPI_BITMASK_RT_CLOCK_ENABLE); @@ -434,9 +450,11 @@ static uint64_t acpi_pm_evt_read(void *opaque, hwaddr = addr, unsigned width) ACPIREGS *ar =3D opaque; switch (addr) { case 0: - return acpi_pm1_evt_get_sts(ar); + case 1: + return acpi_pm1_evt_get_sts(ar) >> (addr * BITS_PER_BYTE); case 2: - return ar->pm1.evt.en; + case 3: + return ar->pm1.evt.en >> ((addr - 2) * BITS_PER_BYTE); default: return 0; } @@ -448,11 +466,13 @@ static void acpi_pm_evt_write(void *opaque, hwaddr ad= dr, uint64_t val, ACPIREGS *ar =3D opaque; switch (addr) { case 0: - acpi_pm1_evt_write_sts(ar, val); + case 1: + acpi_pm1_evt_write_sts(ar, addr, val, width); ar->pm1.evt.update_sci(ar); break; case 2: - acpi_pm1_evt_write_en(ar, val); + case 3: + acpi_pm1_evt_write_en(ar, addr - 2, val, width); ar->pm1.evt.update_sci(ar); break; } @@ -461,7 +481,7 @@ static void acpi_pm_evt_write(void *opaque, hwaddr addr= , uint64_t val, static const MemoryRegionOps acpi_pm_evt_ops =3D { .read =3D acpi_pm_evt_read, .write =3D acpi_pm_evt_write, - .valid.min_access_size =3D 2, + .valid.min_access_size =3D 1, .valid.max_access_size =3D 2, .endianness =3D DEVICE_LITTLE_ENDIAN, }; @@ -590,19 +610,27 @@ void acpi_pm1_cnt_update(ACPIREGS *ar, static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width) { ACPIREGS *ar =3D opaque; - return ar->pm1.cnt.cnt; + return ar->pm1.cnt.cnt >> (addr * BITS_PER_BYTE); } =20 static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val, unsigned width) { + ACPIREGS *ar =3D opaque; + if (width =3D=3D 1) { + if (addr =3D=3D 0) { + val |=3D ar->pm1.cnt.cnt & 0xff00; + } else if (addr =3D=3D 1) { + val =3D (val << BITS_PER_BYTE) | (ar->pm1.cnt.cnt & 0xff); + } + } acpi_pm1_cnt_write(opaque, val); } =20 static const MemoryRegionOps acpi_pm_cnt_ops =3D { .read =3D acpi_pm_cnt_read, .write =3D acpi_pm_cnt_write, - .valid.min_access_size =3D 2, + .valid.min_access_size =3D 1, .valid.max_access_size =3D 2, .endianness =3D DEVICE_LITTLE_ENDIAN, }; --=20 Anthony PERARD