From nobody Fri Dec 19 19:00:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1593511408; cv=none; d=zohomail.com; s=zohoarc; b=YHYMIP6vuvVEXH+q7kvmqRQCxqDa6HOMqvsdPfMLbGCkm5Tz3g+Bxhx7duZxw4ldp+OUSXFB3KWuVzTZaTw2co76Dth+trE7ccW7svYTkgu1SdxjQ0gtJ6Hdt08qwr/WlSxWRhN+dMUG8YtdMQm45x89mwIyW0c2Is9IZKwzZ9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593511408; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TQy5c9M1SNZYb1RY/0O+SR1nKbTHgbqfh2kx+Sij0Q4=; b=DBkCzPLcNu74w7wQjwrQfYhAaDPoLjDs60HGAzlhgmCeVK/49+NrE2cf+KPWhp+qnYKfZBe8NQsJ8OGamMDEGe/oufWNihxKnNVwZ3XaM8sXbRbC5k3GaXCfB6l3+CncoLoA1ro4xT3jh9JcGiMyWcvOBs7ASWxDHenTEbNYMQk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593511408209400.4082486507573; Tue, 30 Jun 2020 03:03:28 -0700 (PDT) Received: from localhost ([::1]:56100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jqD6r-0000wX-Cf for importer@patchew.org; Tue, 30 Jun 2020 06:03:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqD5Y-0007kP-9O; Tue, 30 Jun 2020 06:02:05 -0400 Received: from charlie.dont.surf ([128.199.63.193]:47600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jqD5T-0004Jy-1E; Tue, 30 Jun 2020 06:02:03 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 19135BF7EC; Tue, 30 Jun 2020 10:01:55 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH 05/10] hw/block/nvme: add the zone management send command Date: Tue, 30 Jun 2020 12:01:34 +0200 Message-Id: <20200630100139.1483002-6-its@irrelevant.dk> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200630100139.1483002-1-its@irrelevant.dk> References: <20200630100139.1483002-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/30 04:46:49 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Niklas Cassel , Damien Le Moal , Dmitry Fomichev , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Matias Bjorling Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add the Zone Management Send command. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 461 ++++++++++++++++++++++++++++++++++++++++++ hw/block/nvme.h | 4 + hw/block/trace-events | 12 ++ 3 files changed, 477 insertions(+) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 7e943dece352..a4527ad9840e 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -748,6 +748,11 @@ static void nvme_submit_aio(NvmeAIO *aio) } =20 break; + + case NVME_AIO_OPC_DISCARD: + aio->aiocb =3D blk_aio_pdiscard(blk, aio->offset, aio->len, nvme_a= io_cb, + aio); + break; } } =20 @@ -1142,6 +1147,46 @@ static void nvme_update_zone_info(NvmeNamespace *ns,= NvmeRequest *req, nvme_req_add_aio(req, aio); } =20 +static void nvme_update_zone_descr(NvmeNamespace *ns, NvmeRequest *req, + NvmeZone *zone) +{ + uint64_t zslba =3D -1; + QEMUIOVector *iov =3D g_new0(QEMUIOVector, 1); + NvmeAIO *aio =3D g_new0(NvmeAIO, 1); + + *aio =3D (NvmeAIO) { + .opc =3D NVME_AIO_OPC_WRITE, + .blk =3D ns->zns.info.blk, + .payload =3D iov, + .offset =3D ns->zns.info.num_zones * sizeof(NvmeZoneDescriptor), + .req =3D req, + .flags =3D NVME_AIO_INTERNAL, + }; + + qemu_iovec_init(iov, 1); + + if (zone) { + zslba =3D nvme_zslba(zone); + trace_pci_nvme_update_zone_descr(nvme_cid(req), ns->params.nsid, + zslba); + + aio->offset +=3D nvme_ns_zone_idx(ns, zslba) * nvme_ns_zdes_bytes(= ns); + qemu_iovec_add(iov, zone->zde, nvme_ns_zdes_bytes(ns)); + } else { + trace_pci_nvme_update_zone_descr(nvme_cid(req), ns->params.nsid, + zslba); + + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + qemu_iovec_add(iov, ns->zns.info.zones[i].zde, + nvme_ns_zdes_bytes(ns)); + } + } + + aio->len =3D iov->size; + + nvme_req_add_aio(req, aio); +} + static void nvme_aio_write_cb(NvmeAIO *aio, void *opaque, int ret) { NvmeRequest *req =3D aio->req; @@ -1206,6 +1251,49 @@ static void nvme_rw_cb(NvmeRequest *req, void *opaqu= e) nvme_enqueue_req_completion(cq, req); } =20 +static void nvme_zone_mgmt_send_reset_cb(NvmeRequest *req, void *opaque) +{ + NvmeSQueue *sq =3D req->sq; + NvmeCtrl *n =3D sq->ctrl; + NvmeCQueue *cq =3D n->cq[sq->cqid]; + NvmeNamespace *ns =3D req->ns; + + trace_pci_nvme_zone_mgmt_send_reset_cb(nvme_cid(req), nvme_nsid(ns)); + + g_free(opaque); + + nvme_enqueue_req_completion(cq, req); +} + +static void nvme_aio_zone_reset_cb(NvmeAIO *aio, void *opaque, int ret) +{ + NvmeRequest *req =3D aio->req; + NvmeZone *zone =3D opaque; + NvmeNamespace *ns =3D req->ns; + + uint64_t zslba =3D nvme_zslba(zone); + uint64_t zcap =3D nvme_zcap(zone); + + if (ret) { + return; + } + + trace_pci_nvme_aio_zone_reset_cb(nvme_cid(req), ns->params.nsid, zslba= ); + + nvme_zs_set(zone, NVME_ZS_ZSE); + NVME_ZA_CLEAR(zone->zd.za); + + zone->zd.wp =3D zone->zd.zslba; + zone->wp_staging =3D zslba; + + nvme_update_zone_info(ns, req, zone); + + if (ns->blk_state) { + bitmap_clear(ns->utilization, zslba, zcap); + nvme_ns_update_util(ns, zslba, zcap, req); + } +} + static void nvme_aio_cb(void *opaque, int ret) { NvmeAIO *aio =3D opaque; @@ -1336,6 +1424,377 @@ static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest= *req) return NVME_NO_COMPLETE; } =20 +static uint16_t nvme_zone_mgmt_send_close(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeNamespace *ns =3D req->ns; + + trace_pci_nvme_zone_mgmt_send_close(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zone= )); + + + switch (nvme_zs(zone)) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + nvme_zs_set(zone, NVME_ZS_ZSC); + + nvme_update_zone_info(ns, req, zone); + + return NVME_NO_COMPLETE; + + case NVME_ZS_ZSC: + return NVME_SUCCESS; + + default: + break; + } + + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), nvme_zslba(zo= ne), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; +} + +static uint16_t nvme_zone_mgmt_send_finish(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeNamespace *ns =3D req->ns; + + trace_pci_nvme_zone_mgmt_send_finish(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zon= e)); + + + switch (nvme_zs(zone)) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + case NVME_ZS_ZSC: + case NVME_ZS_ZSE: + nvme_zs_set(zone, NVME_ZS_ZSF); + + nvme_update_zone_info(ns, req, zone); + + return NVME_NO_COMPLETE; + + case NVME_ZS_ZSF: + return NVME_SUCCESS; + + default: + break; + } + + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), nvme_zslba(zo= ne), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; +} + +static uint16_t nvme_zone_mgmt_send_open(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeNamespace *ns =3D req->ns; + + trace_pci_nvme_zone_mgmt_send_open(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zone)= ); + + switch (nvme_zs(zone)) { + case NVME_ZS_ZSE: + case NVME_ZS_ZSC: + case NVME_ZS_ZSIO: + nvme_zs_set(zone, NVME_ZS_ZSEO); + + nvme_update_zone_info(ns, req, zone); + return NVME_NO_COMPLETE; + + case NVME_ZS_ZSEO: + return NVME_SUCCESS; + + default: + break; + } + + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), nvme_zslba(zo= ne), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; +} + +static uint16_t nvme_zone_mgmt_send_reset(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeAIO *aio; + NvmeNamespace *ns =3D req->ns; + uint64_t zslba =3D nvme_zslba(zone); + uint64_t zcap =3D nvme_zcap(zone); + uint8_t lbads =3D nvme_ns_lbads(ns); + + trace_pci_nvme_zone_mgmt_send_reset(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zone= )); + + switch (nvme_zs(zone)) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + case NVME_ZS_ZSC: + case NVME_ZS_ZSF: + aio =3D g_new0(NvmeAIO, 1); + + *aio =3D (NvmeAIO) { + .opc =3D NVME_AIO_OPC_DISCARD, + .blk =3D ns->blk, + .offset =3D zslba << lbads, + .len =3D zcap << lbads, + .req =3D req, + .cb =3D nvme_aio_zone_reset_cb, + .cb_arg =3D zone, + }; + + nvme_req_add_aio(req, aio); + nvme_req_set_cb(req, nvme_zone_mgmt_send_reset_cb, NULL); + + return NVME_NO_COMPLETE; + + case NVME_ZS_ZSE: + return NVME_SUCCESS; + + case NVME_ZS_ZSRO: + nvme_zs_set(zone, NVME_ZS_ZSO); + + nvme_update_zone_info(ns, req, zone); + + return NVME_NO_COMPLETE; + + default: + break; + } + + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), nvme_zslba(zo= ne), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; +} + +static uint16_t nvme_zone_mgmt_send_offline(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeNamespace *ns =3D req->ns; + + trace_pci_nvme_zone_mgmt_send_offline(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zo= ne)); + + switch (nvme_zs(zone)) { + case NVME_ZS_ZSRO: + nvme_zs_set(zone, NVME_ZS_ZSO); + + nvme_update_zone_info(ns, req, zone); + return NVME_NO_COMPLETE; + + case NVME_ZS_ZSO: + return NVME_SUCCESS; + + default: + break; + } + + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), nvme_zslba(zo= ne), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; +} + +static uint16_t nvme_zone_mgmt_send_set_zde(NvmeCtrl *n, NvmeRequest *req, + NvmeZone *zone) +{ + NvmeNamespace *ns =3D req->ns; + uint16_t status; + + trace_pci_nvme_zone_mgmt_send_set_zde(nvme_cid(req), nvme_nsid(ns), + nvme_zslba(zone), nvme_zs_str(zo= ne)); + + if (nvme_zs(zone) !=3D NVME_ZS_ZSE) { + trace_pci_nvme_err_invalid_zone_condition(nvme_cid(req), + nvme_zslba(zone), + nvme_zs(zone)); + return NVME_INVALID_ZONE_STATE_TRANSITION | NVME_DNR; + } + + nvme_zs_set(zone, NVME_ZS_ZSEO); + + status =3D nvme_dma(n, zone->zde, nvme_ns_zdes_bytes(ns), + DMA_DIRECTION_TO_DEVICE, req); + if (status) { + return status; + } + + NVME_ZA_SET_ZDEV(zone->zd.za, 0x1); + nvme_update_zone_descr(ns, req, zone); + nvme_update_zone_info(ns, req, zone); + + return NVME_NO_COMPLETE; +} + +static uint16_t nvme_zone_mgmt_send_all(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeZoneManagementSendCmd *send =3D (NvmeZoneManagementSendCmd *) &req= ->cmd; + NvmeNamespace *ns =3D req->ns; + NvmeZone *zone; + NvmeZoneState zs; + + uint16_t status =3D NVME_SUCCESS; + + trace_pci_nvme_zone_mgmt_send_all(nvme_cid(req), nvme_nsid(ns), send->= zsa); + + switch (send->zsa) { + case NVME_CMD_ZONE_MGMT_SEND_SET_ZDE: + return NVME_INVALID_FIELD | NVME_DNR; + + case NVME_CMD_ZONE_MGMT_SEND_CLOSE: + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + zone =3D &ns->zns.info.zones[i]; + zs =3D nvme_zs(zone); + + switch (zs) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + status =3D nvme_zone_mgmt_send_close(n, req, zone); + if (status && status !=3D NVME_NO_COMPLETE) { + goto err_out; + } + + default: + continue; + } + } + + break; + + case NVME_CMD_ZONE_MGMT_SEND_FINISH: + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + zone =3D &ns->zns.info.zones[i]; + zs =3D nvme_zs(zone); + + switch (zs) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + case NVME_ZS_ZSC: + status =3D nvme_zone_mgmt_send_finish(n, req, zone); + if (status && status !=3D NVME_NO_COMPLETE) { + goto err_out; + } + + default: + continue; + } + } + + break; + + case NVME_CMD_ZONE_MGMT_SEND_OPEN: + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + zone =3D &ns->zns.info.zones[i]; + zs =3D nvme_zs(zone); + + if (zs =3D=3D NVME_ZS_ZSC) { + status =3D nvme_zone_mgmt_send_open(n, req, zone); + if (status && status !=3D NVME_NO_COMPLETE) { + goto err_out; + } + } + } + + break; + + case NVME_CMD_ZONE_MGMT_SEND_RESET: + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + zone =3D &ns->zns.info.zones[i]; + zs =3D nvme_zs(zone); + + switch (zs) { + case NVME_ZS_ZSIO: + case NVME_ZS_ZSEO: + case NVME_ZS_ZSC: + case NVME_ZS_ZSF: + status =3D nvme_zone_mgmt_send_reset(n, req, zone); + if (status && status !=3D NVME_NO_COMPLETE) { + goto err_out; + } + + default: + continue; + } + } + + break; + + case NVME_CMD_ZONE_MGMT_SEND_OFFLINE: + for (int i =3D 0; i < ns->zns.info.num_zones; i++) { + zone =3D &ns->zns.info.zones[i]; + zs =3D nvme_zs(zone); + + if (zs =3D=3D NVME_ZS_ZSRO) { + status =3D nvme_zone_mgmt_send_offline(n, req, zone); + if (status && status !=3D NVME_NO_COMPLETE) { + goto err_out; + } + } + } + + break; + } + + return status; + +err_out: + req->status =3D status; + + if (!QTAILQ_EMPTY(&req->aio_tailq)) { + return NVME_NO_COMPLETE; + } + + return status; +} + +static uint16_t nvme_zone_mgmt_send(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeZoneManagementSendCmd *send =3D (NvmeZoneManagementSendCmd *) &req= ->cmd; + NvmeZoneManagementSendAction zsa =3D send->zsa; + NvmeNamespace *ns =3D req->ns; + NvmeZone *zone; + uint64_t zslba =3D le64_to_cpu(send->slba); + + if (!nvme_ns_zoned(ns)) { + return NVME_INVALID_OPCODE | NVME_DNR; + } + + trace_pci_nvme_zone_mgmt_send(nvme_cid(req), ns->params.nsid, zslba, z= sa, + send->zsflags); + + if (NVME_CMD_ZONE_MGMT_SEND_SELECT_ALL(send->zsflags)) { + return nvme_zone_mgmt_send_all(n, req); + } + + if (zslba & (nvme_ns_zsze(ns) - 1)) { + trace_pci_nvme_err_invalid_zslba(nvme_cid(req), zslba); + return NVME_INVALID_FIELD | NVME_DNR; + } + + zone =3D nvme_ns_get_zone(ns, zslba); + if (!zone) { + trace_pci_nvme_err_invalid_zone(nvme_cid(req), zslba); + return NVME_INVALID_FIELD | NVME_DNR; + } + + switch (zsa) { + case NVME_CMD_ZONE_MGMT_SEND_CLOSE: + return nvme_zone_mgmt_send_close(n, req, zone); + case NVME_CMD_ZONE_MGMT_SEND_FINISH: + return nvme_zone_mgmt_send_finish(n, req, zone); + case NVME_CMD_ZONE_MGMT_SEND_OPEN: + return nvme_zone_mgmt_send_open(n, req, zone); + case NVME_CMD_ZONE_MGMT_SEND_RESET: + return nvme_zone_mgmt_send_reset(n, req, zone); + case NVME_CMD_ZONE_MGMT_SEND_OFFLINE: + return nvme_zone_mgmt_send_offline(n, req, zone); + case NVME_CMD_ZONE_MGMT_SEND_SET_ZDE: + return nvme_zone_mgmt_send_set_zde(n, req, zone); + } + + return NVME_INVALID_FIELD | NVME_DNR; +} + static uint16_t nvme_do_write_zeroes(NvmeCtrl *n, NvmeRequest *req) { NvmeAIO *aio; @@ -1679,6 +2138,8 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest = *req) case NVME_CMD_WRITE: case NVME_CMD_WRITE_ZEROES: return nvme_rwz(n, req); + case NVME_CMD_ZONE_MGMT_SEND: + return nvme_zone_mgmt_send(n, req); case NVME_CMD_ZONE_MGMT_RECV: return nvme_zone_mgmt_recv(n, req); default: diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 92aebb6a6416..757277d339bf 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -51,6 +51,8 @@ static const NvmeEffectsLog nvme_effects[] =3D { [NVME_IOCS_ZONED] =3D { .iocs =3D { [NVME_CMD_ZONE_MGMT_RECV] =3D NVME_EFFECTS_CSUPP, + [NVME_CMD_ZONE_MGMT_SEND] =3D NVME_EFFECTS_CSUPP | + NVME_EFFECTS_LBCC, } }, }; @@ -127,6 +129,7 @@ typedef enum NvmeAIOOp { NVME_AIO_OPC_READ =3D 0x2, NVME_AIO_OPC_WRITE =3D 0x3, NVME_AIO_OPC_WRITE_ZEROES =3D 0x4, + NVME_AIO_OPC_DISCARD =3D 0x5, } NvmeAIOOp; =20 typedef enum NvmeAIOFlags { @@ -164,6 +167,7 @@ static inline const char *nvme_aio_opc_str(NvmeAIO *aio) case NVME_AIO_OPC_READ: return "NVME_AIO_OP_READ"; case NVME_AIO_OPC_WRITE: return "NVME_AIO_OP_WRITE"; case NVME_AIO_OPC_WRITE_ZEROES: return "NVME_AIO_OP_WRITE_ZEROES"; + case NVME_AIO_OPC_DISCARD: return "NVME_AIO_OP_DISCARD"; default: return "NVME_AIO_OP_UNKNOWN"; } } diff --git a/hw/block/trace-events b/hw/block/trace-events index 9d2a7c2766b6..1da48d1c29d0 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -43,12 +43,22 @@ pci_nvme_aio_cb(uint16_t cid, void *aio, const char *bl= kname, uint64_t offset, c pci_nvme_aio_discard_cb(uint16_t cid, uint32_t nsid, uint64_t slba, uint32= _t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" pci_nvme_aio_write_cb(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t= nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" pci_nvme_aio_zone_write_cb(uint16_t cid, uint64_t lba, uint32_t nlb, uint6= 4_t wp) "cid %"PRIu16" lba 0x%"PRIx64" nlb %"PRIu32" wp 0x%"PRIx64"" +pci_nvme_aio_zone_reset_cb(uint16_t cid, uint32_t nsid, uint64_t zslba) "c= id %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64"" pci_nvme_zone_advance_wp(uint16_t cid, uint64_t lba, uint32_t nlb, uint64_= t wp_old, uint64_t wp) "cid %"PRIu16" lba 0x%"PRIx64" nlb %"PRIu32" wp_old = 0x%"PRIx64" wp 0x%"PRIx64"" pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode= ) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8"" pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode) "cid %"PRI= u16" sqid %"PRIu16" opc 0x%"PRIx8"" pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, u= int64_t count, uint64_t lba) "cid %"PRIu16" %s nsid %"PRIu32" nlb %"PRIu32"= count %"PRIu64" lba 0x%"PRIx64"" pci_nvme_rw_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32"" pci_nvme_write_zeroes(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t= nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32"" +pci_nvme_zone_mgmt_send(uint16_t cid, uint32_t nsid, uint64_t zslba, uint8= _t zsa, uint8_t zsflags) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zs= a 0x%"PRIx8" zsflags 0x%"PRIx8"" +pci_nvme_zone_mgmt_send_all(uint16_t cid, uint32_t nsid, uint8_t za) "cid = %"PRIu16" nsid %"PRIu32" za 0x%"PRIx8"" +pci_nvme_zone_mgmt_send_close(uint16_t cid, uint32_t nsid, uint64_t zslba,= const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\"" +pci_nvme_zone_mgmt_send_finish(uint16_t cid, uint32_t nsid, uint64_t zslba= , const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\"" +pci_nvme_zone_mgmt_send_open(uint16_t cid, uint32_t nsid, uint64_t zslba, = const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\"" +pci_nvme_zone_mgmt_send_reset(uint16_t cid, uint32_t nsid, uint64_t zslba,= const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\"" +pci_nvme_zone_mgmt_send_reset_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu1= 6" nsid %"PRIu32"" +pci_nvme_zone_mgmt_send_offline(uint16_t cid, uint32_t nsid, uint64_t zslb= a, const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\= "" +pci_nvme_zone_mgmt_send_set_zde(uint16_t cid, uint32_t nsid, uint64_t zslb= a, const char *zc) "cid %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64" zc \"%s\= "" pci_nvme_zone_mgmt_recv(uint16_t cid, uint32_t nsid, uint64_t slba, uint64= _t len, uint8_t zra, uint8_t zrasp, uint8_t zrasf) "cid %"PRIu16" nsid %"PR= Iu32" slba 0x%"PRIx64" len %"PRIu64" zra 0x%"PRIx8" zrasp 0x%"PRIx8" zrasf = 0x%"PRIx8"" pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" @@ -85,6 +95,7 @@ pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tai= l) "cqid %"PRIu16" new_ pci_nvme_ns_update_util(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %= "PRIu32"" pci_nvme_zone_pending_writes(uint16_t cid, uint64_t zslba, uint64_t wp, ui= nt64_t wp_staging) "cid %"PRIu16" zslba 0x%"PRIx64" wp 0x%"PRIx64" wp_stagi= ng 0x%"PRIx64"" pci_nvme_update_zone_info(uint16_t cid, uint32_t nsid, uint64_t zslba) "ci= d %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64"" +pci_nvme_update_zone_descr(uint16_t cid, uint32_t nsid, uint64_t zslba) "c= id %"PRIu16" nsid %"PRIu32" zslba 0x%"PRIx64"" pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" @@ -138,6 +149,7 @@ pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid se= t features, dw10=3D0x%"PRIx pci_nvme_err_invalid_log_page(uint16_t cid, uint16_t lid) "cid %"PRIu16" l= id 0x%"PRIx16"" pci_nvme_err_invalid_zone(uint16_t cid, uint64_t lba) "cid %"PRIu16" lba 0= x%"PRIx64"" pci_nvme_err_invalid_zone_condition(uint16_t cid, uint64_t zslba, uint8_t = condition) "cid %"PRIu16" zslba 0x%"PRIx64" condition 0x%"PRIx8"" +pci_nvme_err_invalid_zslba(uint16_t cid, uint64_t zslba) "cid %"PRIu16" zs= lba 0x%"PRIx64"" pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" --=20 2.27.0