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bh=qzTw6UxJ8L4OXqqhniWyy68EfIosOn665HgoDeJSQZw=; b=Gt2/0tk34kEgEnq0gCaGlO7a8zkfbe4yEuGyQq8olqe5hZY/fPK6PH7CW6zAGgrWFqS0Fa VdiuEUohFIBdEO/Yn6SPlOl2/7JF+4/LieCtmg5VAcloPPF/QksFMK+Y2tuJ2qAII8JNzp fRj2pRBPFqpRYC6m4alXS75S20PEDL8= X-MC-Unique: 18bEtuFtMX-gn22hqG8Q8Q-1 From: Markus Armbruster To: qemu-devel@nongnu.org Subject: [PATCH v3 21/26] amd_iommu: Fix amdvi_realize() error API violation Date: Tue, 30 Jun 2020 11:03:46 +0200 Message-Id: <20200630090351.1247703-22-armbru@redhat.com> In-Reply-To: <20200630090351.1247703-1-armbru@redhat.com> References: <20200630090351.1247703-1-armbru@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. amdvi_realize() is wrong that way: it passes @errp to qdev_realize(), object_property_get_int(), and msi_init() without checking it. I can't tell offhand whether qdev_realize() can fail here. Fix by checking it for failure. object_property_get_int() can't. Fix by passing &error_abort instead. Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Markus Armbruster --- hw/i386/amd_iommu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index b26d30da57..087f601666 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1549,7 +1549,9 @@ static void amdvi_realize(DeviceState *dev, Error **e= rrp) =20 /* This device should take care of IOMMU PCI properties */ x86_iommu->type =3D TYPE_AMD; - qdev_realize(DEVICE(&s->pci), &bus->qbus, errp); + if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { + return; + } ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, AMDVI_CAPAB_SIZE, errp); if (ret < 0) { @@ -1578,7 +1580,7 @@ static void amdvi_realize(DeviceState *dev, Error **e= rrp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR); pci_setup_iommu(bus, amdvi_host_dma_iommu, s); - s->devid =3D object_property_get_int(OBJECT(&s->pci), "addr", errp); + s->devid =3D object_property_get_int(OBJECT(&s->pci), "addr", &error_a= bort); msi_init(&s->pci.dev, 0, 1, true, false, errp); amdvi_init(s); } --=20 2.26.2