From nobody Mon Feb 9 18:18:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1593460339; cv=none; d=zohomail.com; s=zohoarc; b=SwNScnfP5qi9D/CnUdPP/qwAMMWQUto7V1ab5HTcNj1A9Y8gsbCDwa4GFVXAmYkKsy1Zt8ebWeg1UmF8pNCbFQPPTLliqhHdeyGpYbtAzVn8kov91snWR4flTBEagV7fhb7qlrIvjRYgVntAs68TCHT7ao9U5dA+z04V19jE+Is= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593460339; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hAvh3cNVJ7Z1s+tlMDn4y2g5vqoMkg/lreIMvL1CzhY=; b=AvUSKoC01w9inRAQYDBuH58GbnUtg6oaIivpls4x+fAPVTpOLBuK9OMszA+uL1tqCQQwnI+NdAXiEnUDCrovmZifjWzlEyX5Mx8Bnxg3vMefx6BQXXgS68FtnifEyXARGxcETQpbAGywEufVsqK7IgxFi19rSP0VHQ3fmzXlkMk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593460339264899.3879385534925; Mon, 29 Jun 2020 12:52:19 -0700 (PDT) Received: from localhost ([::1]:34288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jpzpB-0000mu-Ra for importer@patchew.org; Mon, 29 Jun 2020 15:52:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jpznU-000778-Ki; Mon, 29 Jun 2020 15:50:32 -0400 Received: from charlie.dont.surf ([128.199.63.193]:46168) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jpznS-0005wZ-5W; Mon, 29 Jun 2020 15:50:32 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 25DD7BF7F2; Mon, 29 Jun 2020 19:50:26 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH 06/17] hw/block/nvme: pass request along for tracing Date: Mon, 29 Jun 2020 21:50:06 +0200 Message-Id: <20200629195017.1217056-7-its@irrelevant.dk> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200629195017.1217056-1-its@irrelevant.dk> References: <20200629195017.1217056-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/29 14:26:53 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Maxim Levitsky Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Pass along the NvmeRequest in various functions since it is very useful for tracing. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 67 +++++++++++++++++++++++++------------------ hw/block/trace-events | 1 + 2 files changed, 40 insertions(+), 28 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 86d35547b752..e7b7a1900b0b 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -229,14 +229,18 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList= *qsg, QEMUIOVector *iov, return NVME_SUCCESS; } =20 -static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t = prp1, - uint64_t prp2, uint32_t len, NvmeCtrl *n) +static uint16_t nvme_map_prp(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *i= ov, + uint64_t prp1, uint64_t prp2, uint32_t len, + NvmeRequest *req) { hwaddr trans_len =3D n->page_size - (prp1 % n->page_size); trans_len =3D MIN(len, trans_len); int num_prps =3D (len >> n->page_bits) + 1; uint16_t status; =20 + trace_pci_nvme_map_prp(nvme_cid(req), trans_len, len, prp1, prp2, + num_prps); + if (unlikely(!prp1)) { trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; @@ -327,13 +331,14 @@ unmap: } =20 static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len, - uint64_t prp1, uint64_t prp2, DMADirection di= r) + uint64_t prp1, uint64_t prp2, DMADirection di= r, + NvmeRequest *req) { QEMUSGList qsg; QEMUIOVector iov; uint16_t status =3D NVME_SUCCESS; =20 - status =3D nvme_map_prp(&qsg, &iov, prp1, prp2, len, n); + status =3D nvme_map_prp(n, &qsg, &iov, prp1, prp2, len, req); if (status) { return status; } @@ -578,7 +583,7 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns,= NvmeCmd *cmd, return NVME_LBA_RANGE | NVME_DNR; } =20 - if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) { + if (nvme_map_prp(n, &req->qsg, &req->iov, prp1, prp2, data_size, req))= { block_acct_invalid(blk_get_stats(n->conf.blk), acct); return NVME_INVALID_FIELD | NVME_DNR; } @@ -802,7 +807,7 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, NvmeCmd *c= md, uint8_t rae, } =20 return nvme_dma_prp(n, (uint8_t *) &smart + off, trans_len, prp1, prp2, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_fw_log_info(NvmeCtrl *n, NvmeCmd *cmd, uint32_t buf_l= en, @@ -824,7 +829,7 @@ static uint16_t nvme_fw_log_info(NvmeCtrl *n, NvmeCmd *= cmd, uint32_t buf_len, trans_len =3D MIN(sizeof(fw_log) - off, buf_len); =20 return nvme_dma_prp(n, (uint8_t *) &fw_log + off, trans_len, prp1, prp= 2, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_error_info(NvmeCtrl *n, NvmeCmd *cmd, uint8_t rae, @@ -849,7 +854,7 @@ static uint16_t nvme_error_info(NvmeCtrl *n, NvmeCmd *c= md, uint8_t rae, trans_len =3D MIN(sizeof(errlog) - off, buf_len); =20 return nvme_dma_prp(n, (uint8_t *)&errlog, trans_len, prp1, prp2, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) @@ -997,7 +1002,8 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *c= md) return NVME_SUCCESS; } =20 -static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c) +static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c, + NvmeRequest *req) { uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); @@ -1005,10 +1011,11 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, Nvm= eIdentify *c) trace_pci_nvme_identify_ctrl(); =20 return nvme_dma_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp= 1, - prp2, DMA_DIRECTION_FROM_DEVICE); + prp2, DMA_DIRECTION_FROM_DEVICE, req); } =20 -static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c) +static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c, + NvmeRequest *req) { NvmeNamespace *ns; uint32_t nsid =3D le32_to_cpu(c->nsid); @@ -1025,10 +1032,11 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeI= dentify *c) ns =3D &n->namespaces[nsid - 1]; =20 return nvme_dma_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns), prp1, - prp2, DMA_DIRECTION_FROM_DEVICE); + prp2, DMA_DIRECTION_FROM_DEVICE, req); } =20 -static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c) +static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c, + NvmeRequest *req) { static const int data_len =3D NVME_IDENTIFY_DATA_SIZE; uint32_t min_nsid =3D le32_to_cpu(c->nsid); @@ -1051,12 +1059,13 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, N= vmeIdentify *c) } } ret =3D nvme_dma_prp(n, (uint8_t *)list, data_len, prp1, prp2, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, req); g_free(list); return ret; } =20 -static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeIdentify *c) +static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeIdentify *c, + NvmeRequest *req) { uint32_t nsid =3D le32_to_cpu(c->nsid); uint64_t prp1 =3D le64_to_cpu(c->prp1); @@ -1093,22 +1102,22 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtr= l *n, NvmeIdentify *c) stl_be_p(&ns_descrs->uuid.v, nsid); =20 return nvme_dma_prp(n, list, NVME_IDENTIFY_DATA_SIZE, prp1, prp2, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, req); } =20 -static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd) +static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) { NvmeIdentify *c =3D (NvmeIdentify *)cmd; =20 switch (le32_to_cpu(c->cns)) { case NVME_ID_CNS_NS: - return nvme_identify_ns(n, c); + return nvme_identify_ns(n, c, req); case NVME_ID_CNS_CTRL: - return nvme_identify_ctrl(n, c); + return nvme_identify_ctrl(n, c, req); case NVME_ID_CNS_NS_ACTIVE_LIST: - return nvme_identify_nslist(n, c); + return nvme_identify_nslist(n, c, req); case NVME_ID_CNS_NS_DESCR_LIST: - return nvme_identify_ns_descr_list(n, c); + return nvme_identify_ns_descr_list(n, c, req); default: trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; @@ -1167,7 +1176,8 @@ static inline uint64_t nvme_get_timestamp(const NvmeC= trl *n) return cpu_to_le64(ts.all); } =20 -static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd) +static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd, + NvmeRequest *req) { uint64_t prp1 =3D le64_to_cpu(cmd->dptr.prp1); uint64_t prp2 =3D le64_to_cpu(cmd->dptr.prp2); @@ -1175,7 +1185,7 @@ static uint16_t nvme_get_feature_timestamp(NvmeCtrl *= n, NvmeCmd *cmd) uint64_t timestamp =3D nvme_get_timestamp(n); =20 return nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1, - prp2, DMA_DIRECTION_FROM_DEVICE); + prp2, DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *r= eq) @@ -1249,7 +1259,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) result =3D cpu_to_le32(n->features.async_config); break; case NVME_TIMESTAMP: - return nvme_get_feature_timestamp(n, cmd); + return nvme_get_feature_timestamp(n, cmd, req); default: break; } @@ -1296,7 +1306,8 @@ out: return NVME_SUCCESS; } =20 -static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd) +static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd, + NvmeRequest *req) { uint16_t ret; uint64_t timestamp; @@ -1304,7 +1315,7 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *= n, NvmeCmd *cmd) uint64_t prp2 =3D le64_to_cpu(cmd->dptr.prp2); =20 ret =3D nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1, - prp2, DMA_DIRECTION_TO_DEVICE); + prp2, DMA_DIRECTION_TO_DEVICE, req); if (ret !=3D NVME_SUCCESS) { return ret; } @@ -1406,7 +1417,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) n->features.async_config =3D dw11; break; case NVME_TIMESTAMP: - return nvme_set_feature_timestamp(n, cmd); + return nvme_set_feature_timestamp(n, cmd, req); default: return NVME_FEAT_NOT_CHANGABLE | NVME_DNR; } @@ -1448,7 +1459,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) case NVME_ADM_CMD_CREATE_CQ: return nvme_create_cq(n, cmd); case NVME_ADM_CMD_IDENTIFY: - return nvme_identify(n, cmd); + return nvme_identify(n, cmd, req); case NVME_ADM_CMD_ABORT: return nvme_abort(n, cmd, req); case NVME_ADM_CMD_SET_FEATURES: diff --git a/hw/block/trace-events b/hw/block/trace-events index f3b2d004e078..6d0cd588c786 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -35,6 +35,7 @@ pci_nvme_irq_masked(void) "IRQ is masked" pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRI= u64"" pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %= "PRIu64"" +pci_nvme_map_prp(uint16_t cid, uint64_t trans_len, uint32_t len, uint64_t = prp1, uint64_t prp2, int num_prps) "cid %"PRIu16" trans_len %"PRIu64" len %= "PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d" pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode= ) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8"" pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode) "cid %"PRI= u16" sqid %"PRIu16" opc 0x%"PRIx8"" pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uin= t64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" --=20 2.27.0